Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22656

1

T1

11

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3550

1

T1

7

T6

65

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20009

1

T1

18

T2

20

T3

139

auto[1]

6197

1

T5

32

T6

65

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	428	1			T6	12		T51	27		T45	19
values[0]	32	1			T32	11		T332	9		T267	11
values[1]	795	1			T6	28		T14	22		T161	1
values[2]	458	1			T27	1		T41	16		T136	13
values[3]	980	1			T40	27		T140	8		T157	28
values[4]	622	1			T13	2		T32	1		T155	15
values[5]	3070	1			T1	11		T5	32		T6	25
values[6]	546	1			T134	21		T33	3		T235	3
values[7]	539	1			T27	1		T42	8		T43	2
values[8]	674	1			T7	10		T13	1		T140	12
values[9]	980	1			T1	7		T39	18		T40	33
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	623	1			T6	28		T14	22		T27	1
values[1]	620	1			T136	13		T144	18		T174	6
values[2]	869	1			T13	1		T40	27		T140	8
values[3]	3055	1			T5	32		T9	1		T10	27
values[4]	656	1			T1	11		T6	25		T40	15
values[5]	502	1			T134	21		T43	2		T33	3
values[6]	775	1			T13	1		T27	1		T42	8
values[7]	571	1			T7	10		T40	33		T140	12
values[8]	1003	1			T1	7		T6	12		T39	18
values[9]	181	1			T45	19		T87	12		T186	25
minimum	17351	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	10		T161	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	14		T27	1		T41	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	13		T85	1		T92	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T144	13		T174	6		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T140	1		T157	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T40	15		T34	1		T174	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T5	3		T9	1		T10	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T32	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	11		T40	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	14		T138	10		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	21		T43	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	2		T235	1		T169	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	1		T143	9		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T42	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	6		T92	12		T101	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	13		T140	1		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	14		T135	1		T175	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T1	7		T6	6		T39	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T333	1		T271	9		T277	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T45	11		T87	1		T186	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17063	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T32	7		T164	12		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	12		T235	7		T240	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	14		T41	8		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T92	18		T204	22		T205	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	5		T203	15		T93	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	7		T157	8		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	12		T34	1		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T5	29		T141	8		T172	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T155	14		T143	16		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T40	2		T138	1		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	11		T138	1		T176	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T164	2		T205	1		T275	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T33	1		T235	2		T169	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	4		T138	14		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T214	21		T273	13		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	4		T92	7		T101	32
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	20		T140	11		T41	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T51	13		T175	4		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	6		T39	8		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T271	10		T277	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T45	8		T87	11		T186	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T32	4		T164	12		T296	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T51	14		T150	1		T30	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	6		T45	11		T236	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T332	6		T267	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T32	7		T334	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	10		T161	1		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	14		T136	2		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	13		T85	1		T92	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T27	1		T41	8		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T140	1		T157	20		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T40	15		T34	1		T174	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T137	1		T238	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	1		T32	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T1	11		T5	3		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	14		T138	10		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T134	21		T139	1		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T33	2		T235	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	1		T43	2		T143	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	8		T135	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	6		T138	15		T92	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T140	1		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T135	1		T175	6		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T1	7		T39	10		T40	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T51	13		T150	9		T30	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	6		T45	8		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T332	3		T267	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T32	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	12		T34	1		T235	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	14		T164	12		T296	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T92	6		T240	5		T38	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T41	8		T144	5		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T140	7		T157	8		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	12		T34	1		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T238	6		T244	13		T99	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T155	14		T143	16		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T5	29		T40	2		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	11		T138	1		T21	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T272	3		T195	5		T205	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	1		T235	2		T176	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	4		T243	4		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T262	1		T273	13		T199	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	4		T138	14		T92	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T140	11		T41	7		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T175	4		T237	2		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T39	8		T40	20		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	13		T161	1		T235	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	15		T27	1		T41	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T136	1		T85	1		T92	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T144	6		T174	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T140	8		T157	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T40	13		T34	2		T174	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T5	32		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T32	1		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	2		T40	3		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	12		T138	2		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T134	2		T43	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	3		T235	3		T169	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T27	1		T143	5		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	1		T42	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	8		T92	8		T101	34
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	21		T140	12		T41	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T51	14		T135	1		T175	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T1	1		T6	7		T39	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T333	1		T271	11		T277	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T45	9		T87	12		T186	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17158	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T32	10		T164	13		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	9		T240	17		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	13		T41	7		T136	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T136	12		T92	14		T204	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T144	12		T174	5		T203	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T157	19		T149	17		T151	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	14		T174	10		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T10	24		T12	31		T159	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T143	15		T174	6		T239	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	9		T40	12		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	13		T138	9		T257	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	19		T43	1		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T169	11		T262	1		T280	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T143	8		T138	14		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T42	7		T77	1		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	2		T92	11		T335	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	12		T41	5		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T51	13		T175	5		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T1	6		T6	5		T39	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T271	8		T277	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T45	10		T186	10		T206	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T163	13		T34	1		T89	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T32	1		T164	11		T296	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T51	14		T150	10		T30	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	7		T45	9		T236	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T332	4		T267	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T32	10		T334	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	13		T161	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	15		T136	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	1		T85	1		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T27	1		T41	9		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T140	8		T157	9		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T40	13		T34	2		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T137	1		T238	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T32	1		T155	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T1	2		T5	32		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	12		T138	2		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T134	2		T139	1		T272	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	3		T235	3		T176	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	1		T43	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	1		T135	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	8		T138	15		T92	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T140	12		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T135	1		T175	5		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T1	1		T39	9		T40	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T51	13		T30	9		T200	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	5		T45	10		T236	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T332	5		T267	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T32	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	9		T163	13		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	13		T136	1		T164	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T136	12		T92	4		T240	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T41	7		T144	12		T174	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T157	19		T92	10		T149	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	14		T174	10		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T238	4		T244	11		T99	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T143	15		T174	6		T195	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T1	9		T10	24		T12	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	13		T138	9		T239	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	19		T195	13		T151	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T169	11		T280	4		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	1		T143	8		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	7		T262	1		T77	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	2		T138	14		T92	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	5		T35	1		T77	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T175	5		T237	1		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T1	6		T39	9		T40	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2