Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22711

1

T1

7

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3495

1

T1

11

T6

40

T7

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20007

1

T1

10

T2

20

T3

139

auto[1]

6199

1

T1

8

T5

32

T6

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	156	1			T43	2		T34	2		T243	5
values[0]	47	1			T99	26		T283	16		T24	5
values[1]	939	1			T155	18		T157	28		T136	9
values[2]	606	1			T140	12		T135	1		T136	2
values[3]	650	1			T40	27		T51	27		T134	14
values[4]	593	1			T7	10		T27	1		T40	15
values[5]	663	1			T6	53		T27	1		T40	33
values[6]	579	1			T1	10		T13	1		T158	1
values[7]	859	1			T1	1		T13	1		T39	18
values[8]	3114	1			T1	7		T5	32		T6	12
values[9]	918	1			T13	1		T14	22		T41	13
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T155	18		T157	28		T136	2
values[1]	650	1			T140	12		T135	1		T143	32
values[2]	636	1			T27	1		T40	27		T51	27
values[3]	603	1			T6	28		T7	10		T27	1
values[4]	701	1			T6	25		T32	11		T174	9
values[5]	518	1			T1	11		T13	1		T32	1
values[6]	3238	1			T5	32		T9	1		T10	27
values[7]	732	1			T1	7		T6	12		T14	22
values[8]	753	1			T13	1		T42	10		T43	2
values[9]	172	1			T34	2		T147	2		T45	19
minimum	17364	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T136	2		T138	1		T174	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T155	2		T157	20		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T140	1		T143	16		T238	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T135	1		T235	1		T92	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T27	1		T40	15		T51	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	2		T134	14		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T161	1		T44	1		T225	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	14		T7	6		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	14		T32	7		T174	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	18		T240	12		T18	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T176	1		T233	1		T204	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	11		T13	1		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1715	1			T5	3		T9	1		T10	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	8		T163	14		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	7		T41	6		T143	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	6		T14	10		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T42	10		T135	1		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T13	1		T43	2		T136	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T147	1		T17	5		T149	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T34	1		T45	11		T203	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17023	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T136	9		T92	12		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T138	1		T235	12		T89	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T155	16		T157	8		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T140	11		T143	16		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T235	2		T92	6		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T40	12		T51	13		T138	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	1		T250	13		T264	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T225	11		T205	1		T291	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	14		T7	4		T40	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	11		T32	4		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T149	14		T240	9		T18	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T176	13		T204	4		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	1		T245	10		T21	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T5	29		T39	8		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	16		T272	3		T19	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T41	7		T143	4		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	6		T14	12		T195	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T33	1		T243	4		T87	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T250	12		T35	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T147	1		T17	1		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T34	1		T45	8		T203	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T92	7		T99	11		T335	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T243	1		T17	5		T149	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T43	2		T34	1		T36	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T283	9		T24	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T99	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	1		T235	1		T265	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T155	2		T157	20		T136	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T140	1		T136	2		T238	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T135	1		T235	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	15		T51	14		T143	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	14		T36	4		T204	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	1		T161	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	6		T40	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	14		T32	7		T174	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	14		T27	1		T40	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T146	1		T176	1		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	10		T13	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	1		T39	10		T41	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T42	8		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T1	7		T5	3		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	6		T147	12		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	6		T42	10		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T13	1		T14	10		T136	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T243	4		T17	1		T149	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T34	1		T36	1		T203	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T283	7		T24	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T99	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T138	1		T235	12		T89	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	16		T157	8		T92	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T140	11		T238	6		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T235	2		T35	3		T92	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T40	12		T51	13		T143	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	2		T204	15		T30	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T145	8		T195	10		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	4		T40	2		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	11		T32	4		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	14		T40	20		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T176	13		T18	4		T204	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T34	1		T149	14		T179	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	8		T41	8		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T272	3		T245	10		T21	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T5	29		T141	8		T172	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	6		T147	16		T195	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T41	7		T147	1		T87	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T14	12		T45	8		T250	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T136	1		T138	2		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	18		T157	9		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T140	12		T143	17		T238	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T135	1		T235	3		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T27	1		T40	13		T51	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	2		T134	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T161	1		T44	1		T225	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	15		T7	8		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	12		T32	10		T174	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	15		T240	10		T18	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T176	14		T233	1		T204	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	2		T13	1		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T5	32		T9	1		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T42	1		T163	1		T147	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T41	8		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	7		T14	13		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T42	1		T135	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	1		T43	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T147	2		T17	6		T149	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T34	2		T45	9		T203	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17146	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T136	1		T92	8		T99	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	1		T174	5		T265	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T157	19		T35	3		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T143	15		T238	4		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T92	4		T36	1		T164	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	14		T51	13		T138	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T32	1		T134	13		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T225	10		T280	21		T291	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	13		T7	2		T40	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	13		T32	1		T174	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T149	17		T240	11		T18	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T204	2		T261	4		T276	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	9		T34	1		T245	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T10	24		T12	31		T39	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T42	7		T163	13		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	6		T41	5		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	5		T14	9		T195	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T42	9		T236	4		T296	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T43	1		T136	12		T250	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T149	10		T262	1		T297	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T45	10		T203	5		T298	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T252	12		T283	8		T325	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T136	8		T92	11		T99	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T243	5		T17	6		T149	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T43	1		T34	2		T36	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T283	8		T24	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T99	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T138	2		T235	13		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T155	18		T157	9		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T140	12		T136	1		T238	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	1		T235	3		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	13		T51	14		T143	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T134	1		T36	5		T204	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T27	1		T161	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	8		T40	3		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	12		T32	10		T174	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	15		T27	1		T40	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	1		T176	14		T18	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T13	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T39	9		T41	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T42	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T1	1		T5	32		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	7		T147	17		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	8		T42	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T13	1		T14	13		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T149	10		T262	1		T297	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T43	1		T36	1		T203	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	8		T24	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T99	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T265	2		T89	8		T164	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T157	19		T136	8		T92	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	1		T238	4		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T35	3		T92	4		T164	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	14		T51	13		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	13		T36	1		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T195	11		T225	10		T299	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	2		T40	12		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	13		T32	1		T174	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	13		T40	12		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T204	18		T276	18		T154	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	9		T34	1		T149	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	9		T41	7		T134	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	7		T163	13		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T1	6		T10	24		T12	31
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	5		T147	11		T195	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T41	5		T42	9		T236	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	9		T136	12		T45	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2