CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26206 | 1 | T1 | 18 | T2 | 20 | T3 | 139 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 22857 | 1 | T2 | 20 | T3 | 139 | T5 | 32 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3349 | 1 | T1 | 18 | T6 | 25 | T13 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20163 | 1 | T1 | 7 | T2 | 20 | T3 | 139 | ||||
auto[1] | 6043 | 1 | T1 | 11 | T5 | 32 | T7 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22181 | 1 | T1 | 18 | T2 | 20 | T3 | 139 | ||||
auto[1] | 4025 | 1 | T5 | 29 | T6 | 31 | T7 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 217 | 1 | T140 | 8 | T32 | 11 | T155 | 3 | ||||
values[0] | 29 | 1 | T93 | 6 | T212 | 11 | T336 | 12 | ||||
values[1] | 655 | 1 | T1 | 7 | T41 | 13 | T42 | 10 | ||||
values[2] | 606 | 1 | T14 | 22 | T134 | 14 | T155 | 15 | ||||
values[3] | 537 | 1 | T1 | 11 | T32 | 1 | T135 | 1 | ||||
values[4] | 2884 | 1 | T5 | 32 | T9 | 1 | T10 | 27 | ||||
values[5] | 798 | 1 | T13 | 1 | T51 | 27 | T137 | 1 | ||||
values[6] | 859 | 1 | T6 | 25 | T7 | 10 | T27 | 1 | ||||
values[7] | 761 | 1 | T27 | 1 | T43 | 2 | T136 | 9 | ||||
values[8] | 914 | 1 | T6 | 40 | T13 | 1 | T40 | 15 | ||||
values[9] | 864 | 1 | T13 | 1 | T39 | 18 | T40 | 27 | ||||
minimum | 17082 | 1 | T2 | 20 | T3 | 139 | T6 | 34 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 637 | 1 | T1 | 7 | T42 | 10 | T135 | 1 | ||||
values[1] | 555 | 1 | T14 | 22 | T32 | 1 | T134 | 14 | ||||
values[2] | 556 | 1 | T1 | 11 | T134 | 7 | T157 | 28 | ||||
values[3] | 2916 | 1 | T5 | 32 | T9 | 1 | T10 | 27 | ||||
values[4] | 722 | 1 | T235 | 16 | T92 | 19 | T36 | 4 | ||||
values[5] | 1015 | 1 | T6 | 25 | T7 | 10 | T27 | 1 | ||||
values[6] | 646 | 1 | T27 | 1 | T42 | 8 | T144 | 18 | ||||
values[7] | 936 | 1 | T6 | 40 | T13 | 1 | T40 | 15 | ||||
values[8] | 834 | 1 | T13 | 1 | T39 | 18 | T40 | 27 | ||||
values[9] | 87 | 1 | T139 | 1 | T337 | 1 | T309 | 14 | ||||
minimum | 17302 | 1 | T2 | 20 | T3 | 139 | T6 | 34 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22068 | 1 | T1 | 3 | T2 | 20 | T3 | 139 | ||||
auto[1] | 4138 | 1 | T1 | 15 | T6 | 31 | T7 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 145 | 1 | T155 | 1 | T138 | 15 | T259 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T1 | 7 | T42 | 10 | T135 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 166 | 1 | T14 | 10 | T32 | 1 | T134 | 14 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T163 | 14 | T148 | 1 | T175 | 6 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 99 | 1 | T149 | 12 | T77 | 11 | T81 | 9 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T1 | 11 | T134 | 7 | T157 | 20 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1559 | 1 | T5 | 3 | T9 | 1 | T10 | 27 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T13 | 1 | T40 | 13 | T137 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 239 | 1 | T235 | 1 | T36 | 3 | T225 | 11 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T235 | 1 | T92 | 12 | T168 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 234 | 1 | T7 | 6 | T27 | 1 | T43 | 2 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 317 | 1 | T6 | 14 | T236 | 9 | T164 | 29 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T42 | 8 | T144 | 13 | T145 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 183 | 1 | T27 | 1 | T35 | 4 | T241 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 279 | 1 | T6 | 20 | T13 | 1 | T40 | 13 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 251 | 1 | T161 | 1 | T44 | 1 | T174 | 7 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 260 | 1 | T39 | 10 | T40 | 15 | T140 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 180 | 1 | T13 | 1 | T140 | 1 | T155 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T309 | 1 | T338 | 2 | T270 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 25 | 1 | T139 | 1 | T337 | 1 | T246 | 14 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17040 | 1 | T2 | 20 | T3 | 139 | T6 | 34 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 36 | 1 | T41 | 6 | T93 | 5 | T297 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T155 | 14 | T138 | 14 | T18 | 4 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T238 | 6 | T250 | 12 | T242 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T14 | 12 | T143 | 4 | T34 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 102 | 1 | T175 | 4 | T240 | 1 | T248 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 95 | 1 | T149 | 10 | T81 | 9 | T261 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 142 | 1 | T157 | 8 | T174 | 11 | T92 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1025 | 1 | T5 | 29 | T141 | 8 | T51 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 112 | 1 | T40 | 20 | T138 | 1 | T87 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 188 | 1 | T235 | 2 | T36 | 1 | T225 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T235 | 12 | T92 | 7 | T168 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 253 | 1 | T7 | 4 | T143 | 16 | T34 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 211 | 1 | T6 | 11 | T236 | 3 | T164 | 27 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T144 | 5 | T145 | 8 | T87 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 112 | 1 | T35 | 3 | T241 | 11 | T257 | 9 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 193 | 1 | T6 | 20 | T40 | 2 | T35 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 213 | 1 | T174 | 2 | T176 | 13 | T240 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T39 | 8 | T40 | 12 | T140 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 197 | 1 | T140 | 11 | T155 | 2 | T33 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 32 | 1 | T309 | 13 | T338 | 2 | T270 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 19 | 1 | T246 | 11 | T25 | 5 | T339 | 3 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T7 | 2 | T11 | 2 | T32 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 29 | 1 | T41 | 7 | T93 | 1 | T297 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 2 | 46 | 95.83 | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 78 | 1 | T140 | 1 | T32 | 7 | T243 | 1 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 42 | 1 | T155 | 1 | T244 | 12 | T312 | 5 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 12 | 1 | T212 | 11 | T336 | 1 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 5 | 1 | T93 | 5 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 154 | 1 | T235 | 1 | T89 | 9 | T259 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 181 | 1 | T1 | 7 | T41 | 6 | T42 | 10 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 192 | 1 | T14 | 10 | T134 | 14 | T155 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T163 | 14 | T238 | 5 | T148 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 101 | 1 | T32 | 1 | T135 | 1 | T136 | 2 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 201 | 1 | T1 | 11 | T157 | 20 | T136 | 13 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 1551 | 1 | T5 | 3 | T9 | 1 | T10 | 27 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 202 | 1 | T40 | 13 | T134 | 7 | T138 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T51 | 14 | T143 | 16 | T235 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 214 | 1 | T13 | 1 | T137 | 1 | T235 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T7 | 6 | T27 | 1 | T45 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 260 | 1 | T6 | 14 | T236 | 9 | T164 | 29 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 227 | 1 | T43 | 2 | T136 | 9 | T34 | 2 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 215 | 1 | T27 | 1 | T35 | 4 | T203 | 6 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 284 | 1 | T6 | 20 | T13 | 1 | T40 | 13 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 238 | 1 | T161 | 1 | T44 | 1 | T146 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 221 | 1 | T39 | 10 | T40 | 15 | T137 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 224 | 1 | T13 | 1 | T140 | 1 | T44 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16966 | 1 | T2 | 20 | T3 | 139 | T6 | 34 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 60 | 1 | T140 | 7 | T32 | 4 | T243 | 4 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 37 | 1 | T155 | 2 | T244 | 13 | T312 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T336 | 11 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T93 | 1 | - | - | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 163 | 1 | T235 | 7 | T89 | 8 | T149 | 8 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 157 | 1 | T41 | 7 | T250 | 12 | T242 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 169 | 1 | T14 | 12 | T155 | 14 | T143 | 4 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 82 | 1 | T238 | 6 | T240 | 1 | T328 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T81 | 9 | T260 | 7 | T261 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T157 | 8 | T174 | 11 | T92 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 990 | 1 | T5 | 29 | T141 | 8 | T172 | 5 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 141 | 1 | T40 | 20 | T138 | 1 | T92 | 6 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 238 | 1 | T51 | 13 | T143 | 16 | T235 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 121 | 1 | T235 | 12 | T87 | 10 | T92 | 7 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T7 | 4 | T45 | 8 | T250 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 170 | 1 | T6 | 11 | T236 | 3 | T164 | 27 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T34 | 1 | T144 | 5 | T145 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T35 | 3 | T203 | 14 | T262 | 1 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 176 | 1 | T6 | 20 | T40 | 2 | T41 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 216 | 1 | T240 | 9 | T18 | 8 | T150 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 193 | 1 | T39 | 8 | T40 | 12 | T17 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T140 | 11 | T33 | 1 | T138 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 116 | 1 | T7 | 2 | T11 | 2 | T32 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 187 | 1 | T155 | 15 | T138 | 15 | T259 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T1 | 1 | T42 | 1 | T135 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T14 | 13 | T32 | 1 | T134 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 131 | 1 | T163 | 1 | T148 | 1 | T175 | 5 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 113 | 1 | T149 | 11 | T77 | 1 | T81 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T1 | 2 | T134 | 1 | T157 | 9 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1370 | 1 | T5 | 32 | T9 | 1 | T10 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 169 | 1 | T13 | 1 | T40 | 21 | T137 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T235 | 3 | T36 | 3 | T225 | 12 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T235 | 13 | T92 | 8 | T168 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 294 | 1 | T7 | 8 | T27 | 1 | T43 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 256 | 1 | T6 | 12 | T236 | 4 | T164 | 29 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 189 | 1 | T42 | 1 | T144 | 6 | T145 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T27 | 1 | T35 | 4 | T241 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 248 | 1 | T6 | 22 | T13 | 1 | T40 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 263 | 1 | T161 | 1 | T44 | 1 | T174 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 265 | 1 | T39 | 9 | T40 | 13 | T140 | 8 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 247 | 1 | T13 | 1 | T140 | 12 | T155 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 41 | 1 | T309 | 14 | T338 | 4 | T270 | 11 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 29 | 1 | T139 | 1 | T337 | 1 | T246 | 12 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17171 | 1 | T2 | 20 | T3 | 139 | T6 | 34 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 40 | 1 | T41 | 8 | T93 | 4 | T297 | 12 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 117 | 1 | T138 | 14 | T207 | 11 | T340 | 17 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 156 | 1 | T1 | 6 | T42 | 9 | T238 | 4 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T14 | 9 | T134 | 13 | T136 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T163 | 13 | T175 | 5 | T252 | 6 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 81 | 1 | T149 | 11 | T77 | 10 | T81 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T1 | 9 | T134 | 6 | T157 | 19 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1214 | 1 | T10 | 24 | T12 | 31 | T51 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T40 | 12 | T92 | 4 | T36 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 205 | 1 | T36 | 1 | T225 | 10 | T169 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 146 | 1 | T92 | 11 | T168 | 10 | T299 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 193 | 1 | T7 | 2 | T43 | 1 | T136 | 8 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 272 | 1 | T6 | 13 | T236 | 8 | T164 | 27 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 162 | 1 | T42 | 7 | T144 | 12 | T236 | 4 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T35 | 3 | T257 | 8 | T178 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 224 | 1 | T6 | 18 | T40 | 12 | T174 | 5 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 201 | 1 | T174 | 6 | T240 | 11 | T18 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 192 | 1 | T39 | 9 | T40 | 14 | T41 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T138 | 9 | T147 | 11 | T244 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 2 | 1 | T263 | 2 | - | - | - | - | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 15 | 1 | T246 | 13 | T25 | 2 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 66 | 1 | T89 | 8 | T149 | 10 | T264 | 13 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 25 | 1 | T41 | 5 | T93 | 2 | T297 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 83 | 1 | T140 | 8 | T32 | 10 | T243 | 5 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 51 | 1 | T155 | 3 | T244 | 14 | T312 | 4 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T212 | 1 | T336 | 12 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 4 | 1 | T93 | 4 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 187 | 1 | T235 | 8 | T89 | 9 | T259 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T1 | 1 | T41 | 8 | T42 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 210 | 1 | T14 | 13 | T134 | 1 | T155 | 15 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 110 | 1 | T163 | 1 | T238 | 7 | T148 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T32 | 1 | T135 | 1 | T136 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T1 | 2 | T157 | 9 | T136 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 1331 | 1 | T5 | 32 | T9 | 1 | T10 | 3 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 194 | 1 | T40 | 21 | T134 | 1 | T138 | 2 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 273 | 1 | T51 | 14 | T143 | 17 | T235 | 3 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T13 | 1 | T137 | 1 | T235 | 13 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 240 | 1 | T7 | 8 | T27 | 1 | T45 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 207 | 1 | T6 | 12 | T236 | 4 | T164 | 29 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 236 | 1 | T43 | 1 | T136 | 1 | T34 | 2 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T27 | 1 | T35 | 4 | T203 | 15 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 236 | 1 | T6 | 22 | T13 | 1 | T40 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 261 | 1 | T161 | 1 | T44 | 1 | T146 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 256 | 1 | T39 | 9 | T40 | 13 | T137 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 285 | 1 | T13 | 1 | T140 | 12 | T44 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17082 | 1 | T2 | 20 | T3 | 139 | T6 | 34 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 55 | 1 | T32 | 1 | T280 | 21 | T322 | 2 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T244 | 11 | T312 | 2 | T246 | 13 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 10 | 1 | T212 | 10 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T93 | 2 | - | - | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T89 | 8 | T149 | 10 | T264 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T1 | 6 | T41 | 5 | T42 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T14 | 9 | T134 | 13 | T143 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 135 | 1 | T163 | 13 | T238 | 4 | T252 | 6 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 75 | 1 | T136 | 1 | T265 | 2 | T81 | 5 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T1 | 9 | T157 | 19 | T136 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 1210 | 1 | T10 | 24 | T12 | 31 | T32 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T40 | 12 | T134 | 6 | T92 | 4 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 190 | 1 | T51 | 13 | T143 | 15 | T225 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 180 | 1 | T92 | 11 | T168 | 10 | T275 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 189 | 1 | T7 | 2 | T45 | 10 | T250 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 223 | 1 | T6 | 13 | T236 | 8 | T164 | 27 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 187 | 1 | T43 | 1 | T136 | 8 | T34 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 180 | 1 | T35 | 3 | T203 | 5 | T262 | 1 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 224 | 1 | T6 | 18 | T40 | 12 | T41 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T240 | 11 | T18 | 6 | T99 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T39 | 9 | T40 | 14 | T174 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T138 | 9 | T174 | 6 | T147 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 22068 | 1 | T1 | 3 | T2 | 20 | T3 | 139 | ||||
auto[1] | auto[0] | 4138 | 1 | T1 | 15 | T6 | 31 | T7 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |