Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22724

1

T1

8

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3482

1

T1

10

T6

40

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20024

1

T1

10

T2

20

T3

139

auto[1]

6182

1

T1

8

T5

32

T6

65

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T40	60		T235	13		T265	3
values[0]	63	1			T150	5		T151	10		T324	26
values[1]	735	1			T6	25		T27	1		T140	8
values[2]	3049	1			T1	7		T5	32		T9	1
values[3]	950	1			T40	15		T140	12		T32	1
values[4]	878	1			T1	10		T27	1		T39	18
values[5]	665	1			T1	1		T137	1		T143	13
values[6]	589	1			T6	28		T13	1		T42	8
values[7]	558	1			T7	10		T14	22		T134	7
values[8]	742	1			T6	12		T13	1		T155	3
values[9]	636	1			T13	1		T41	16		T32	14
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	873	1			T6	25		T27	1		T140	8
values[1]	2986	1			T1	7		T5	32		T9	1
values[2]	916	1			T40	15		T140	12		T32	1
values[3]	850	1			T1	10		T27	1		T39	18
values[4]	682	1			T1	1		T13	1		T42	8
values[5]	553	1			T6	28		T136	2		T174	6
values[6]	700	1			T7	10		T14	22		T134	7
values[7]	537	1			T6	12		T13	1		T155	3
values[8]	743	1			T40	33		T41	16		T32	14
values[9]	65	1			T13	1		T40	27		T89	17
minimum	17301	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	14		T27	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T140	1		T34	2		T164	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1664	1			T1	7		T5	3		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	1		T203	6		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T32	1		T134	14		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T40	13		T140	1		T236	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T27	1		T41	6		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	10		T39	10		T51	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T137	1		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	1		T42	8		T143	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	2		T174	6		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	14		T235	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	6		T137	1		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	10		T134	7		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T33	2		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	6		T155	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T40	13		T41	8		T32	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	2		T163	14		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T89	9		T208	3		T341	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T13	1		T40	15		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17059	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T161	1		T176	1		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	11		T157	8		T147	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	7		T34	1		T164	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T5	29		T141	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T138	1		T203	14		T272	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T302	8		T195	15		T149	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T40	2		T140	11		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T41	7		T155	14		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T39	8		T51	13		T45	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T138	14		T186	9		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T143	4		T174	11		T92	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	1		T87	10		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	14		T235	7		T164	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	4		T143	16		T250	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	12		T87	11		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T33	1		T238	6		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	6		T155	2		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	20		T41	8		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	1		T235	12		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T89	8		T255	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T40	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T176	13		T241	5		T342	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T40	13		T265	3		T89	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T40	15		T235	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T151	10		T324	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T150	1		T342	1		T325	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	14		T27	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T140	1		T161	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T1	7		T5	3		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	1		T203	6		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T32	1		T134	14		T174	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T40	13		T140	1		T236	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T27	1		T41	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	10		T39	10		T51	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	1		T137	1		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T143	9		T174	11		T92	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T136	2		T174	6		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	14		T13	1		T42	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	6		T137	1		T186	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	10		T134	7		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T33	2		T143	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	6		T155	1		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T41	8		T32	7		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T32	2		T163	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T40	20		T89	8		T343	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T40	12		T235	12		T241	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T324	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T150	4		T342	1		T325	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	11		T157	8		T147	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	7		T34	1		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T5	29		T141	8		T172	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	1		T203	14		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T174	2		T36	1		T302	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	2		T140	11		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	7		T155	14		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	8		T51	13		T45	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T138	14		T250	13		T186	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T143	4		T174	11		T92	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T35	1		T87	10		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	14		T164	2		T18	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	4		T186	14		T296	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	12		T235	7		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	1		T143	16		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	6		T155	2		T87	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	8		T32	4		T138	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T32	1		T164	15		T203	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	12		T27	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T140	8		T34	2		T164	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	1		T5	32		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	2		T203	15		T272	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T32	1		T134	1		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	3		T140	12		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	1		T41	8		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T1	1		T39	9		T51	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T137	1		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T42	1		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	1		T174	1		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	15		T235	8		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	8		T137	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	13		T134	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	1		T33	3		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	7		T155	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T40	21		T41	9		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T32	2		T163	1		T235	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T89	9		T208	1		T341	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T13	1		T40	13		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17180	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T161	1		T176	14		T241	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	13		T157	19		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T34	1		T164	11		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	6		T10	24		T12	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T203	5		T280	4		T299	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T134	13		T195	24		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	12		T236	4		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T41	5		T144	12		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	9		T39	9		T51	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T138	14		T186	1		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	7		T143	8		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T136	1		T174	5		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	13		T164	2		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	2		T143	15		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	9		T134	6		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T238	4		T236	8		T92	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	5		T37	1		T204	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	12		T41	7		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	1		T163	13		T164	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T89	8		T208	2		T344	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T40	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T307	9		T151	9		T230	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T325	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T40	21		T265	1		T89	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T40	13		T235	13		T241	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T151	1		T324	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T150	5		T342	2		T325	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	12		T27	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T140	8		T161	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T1	1		T5	32		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	2		T203	15		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T32	1		T134	1		T174	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T40	3		T140	12		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	1		T41	8		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	1		T39	9		T51	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T137	1		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T143	5		T174	12		T92	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T136	1		T174	1		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	15		T13	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	8		T137	1		T186	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	13		T134	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T33	3		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	7		T155	3		T87	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	9		T32	10		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	1		T32	2		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T40	12		T265	2		T89	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T40	14		T99	11		T297	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T151	9		T324	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T325	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	13		T157	19		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	1		T164	11		T252	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T1	6		T10	24		T12	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T203	5		T280	4		T178	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T134	13		T174	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	12		T236	4		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	5		T144	12		T206	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	9		T39	9		T51	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T138	14		T250	11		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T143	8		T174	10		T92	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T136	1		T174	5		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	13		T42	7		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	2		T186	10		T296	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T14	9		T134	6		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T143	15		T238	4		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	5		T37	1		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T41	7		T32	1		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T32	1		T163	13		T164	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2