Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T155	15		T138	15		T235	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T41	8		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	1		T134	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	1		T148	1		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	13		T149	11		T81	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	2		T40	21		T157	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T5	32		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	1		T134	1		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T143	17		T235	3		T164	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	1		T235	13		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T7	8		T27	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	12		T27	1		T236	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	1		T144	6		T145	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	4		T241	12		T257	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	22		T13	1		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T161	1		T44	1		T174	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T39	9		T140	8		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T140	12		T155	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	13		T204	16		T258	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T256	7		T246	12		T25	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T138	14		T89	8		T149	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	6		T41	5		T42	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T134	13		T136	1		T143	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	13		T175	5		T252	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T14	9		T149	11		T81	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	9		T40	12		T157	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T10	24		T12	31		T51	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	6		T92	4		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T143	15		T164	2		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T92	11		T164	16		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T43	1		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	13		T236	8		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	7		T144	12		T236	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	3		T257	8		T178	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	18		T40	12		T174	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T174	6		T240	11		T18	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	9		T41	7		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	9		T147	11		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T40	14		T204	13		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T256	7		T246	13		T25	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T253	1		T254	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T155	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T235	8		T89	9		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T41	8		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	13		T134	1		T155	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T163	1		T238	7		T174	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	1		T135	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	2		T157	9		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	32		T9	1		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	21		T134	1		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	8		T51	14		T235	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T137	1		T235	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T27	1		T143	17		T45	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	12		T236	4		T35	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T40	3		T43	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T27	1		T203	15		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	7		T13	1		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T44	1		T146	1		T240	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T6	15		T39	9		T40	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T13	1		T140	12		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T89	8		T149	10		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	6		T41	5		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	9		T134	13		T143	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T163	13		T238	4		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T136	1		T265	2		T77	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	9		T157	19		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T10	24		T12	31		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	12		T134	6		T92	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	2		T51	13		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T92	11		T164	16		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T143	15		T45	10		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	13		T236	8		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	12		T43	1		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T203	5		T239	11		T262	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	5		T41	7		T42	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T240	11		T18	6		T99	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	13		T39	9		T40	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T138	9		T174	6		T147	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2