Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22724

1

T1

11

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3482

1

T1

7

T6

65

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20178

1

T1

18

T2

20

T3

139

auto[1]

6028

1

T5

32

T6

37

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T266	1		-	-		-	-
values[0]	42	1			T161	1		T235	8		T267	11
values[1]	823	1			T6	28		T14	22		T32	11
values[2]	453	1			T27	1		T41	16		T136	13
values[3]	905	1			T40	27		T140	8		T157	28
values[4]	653	1			T13	2		T32	1		T155	15
values[5]	3099	1			T1	11		T5	32		T6	25
values[6]	517	1			T134	14		T33	3		T139	1
values[7]	569	1			T27	1		T42	8		T134	7
values[8]	686	1			T7	10		T13	1		T140	12
values[9]	1376	1			T1	7		T6	12		T39	18
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	854	1			T6	28		T14	22		T27	1
values[1]	673	1			T140	8		T136	13		T144	18
values[2]	830	1			T13	1		T40	27		T157	28
values[3]	3061	1			T5	32		T9	1		T10	27
values[4]	644	1			T1	11		T6	25		T40	15
values[5]	522	1			T134	21		T43	2		T33	3
values[6]	750	1			T13	1		T27	1		T140	12
values[7]	580	1			T7	10		T39	18		T40	33
values[8]	934	1			T6	12		T42	10		T51	27
values[9]	245	1			T1	7		T45	19		T87	12
minimum	17113	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	10		T32	7		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	14		T27	1		T41	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T140	1		T136	13		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T144	13		T174	6		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T157	20		T158	1		T238	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	1		T40	15		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T5	3		T9	1		T10	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T32	1		T143	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	11		T40	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	14		T138	10		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T134	21		T139	1		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	2		T33	2		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T27	1		T135	1		T143	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T140	1		T42	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	6		T92	12		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	10		T40	13		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T51	14		T135	1		T236	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	6		T42	10		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T269	1		T270	1		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	7		T45	11		T87	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16980	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	12		T32	4		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	14		T41	8		T235	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T140	7		T92	18		T149	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	5		T203	15		T204	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T157	8		T238	6		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	12		T34	1		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T5	29		T141	8		T172	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	16		T174	2		T147	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T40	2		T138	1		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	11		T138	1		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T164	2		T272	3		T205	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T33	1		T235	2		T169	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T143	4		T138	14		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	11		T273	13		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	4		T92	7		T101	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	8		T40	20		T41	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T51	13		T175	4		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	6		T32	1		T236	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T269	9		T270	10		T271	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T45	8		T87	11		T186	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	2		T11	2		T32	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T161	1		T267	8		T193	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T235	1		T274	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	10		T32	7		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	14		T44	1		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T136	13		T85	1		T92	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T27	1		T41	8		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T140	1		T157	20		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	15		T34	1		T174	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	1		T137	1		T238	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T32	1		T143	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1731	1			T1	11		T5	3		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	14		T138	10		T174	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	14		T139	1		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T33	2		T176	1		T169	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	1		T134	7		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T42	8		T43	2		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	6		T138	15		T92	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T140	1		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T51	14		T135	1		T236	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	434	1			T1	7		T6	6		T39	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T267	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T235	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	12		T32	4		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	14		T89	8		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T92	6		T240	5		T205	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T41	8		T144	5		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	7		T157	8		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	12		T34	1		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T155	14		T238	6		T99	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	16		T147	1		T195	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T5	29		T40	2		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	11		T138	1		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T272	3		T205	1		T275	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	1		T176	13		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	4		T243	4		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T235	2		T262	1		T260	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	4		T138	14		T92	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	11		T41	7		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T51	13		T175	4		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T6	6		T39	8		T40	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	13		T32	10		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	15		T27	1		T41	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	8		T136	1		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	6		T174	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T157	9		T158	1		T238	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T40	13		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T5	32		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T32	1		T143	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T40	3		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	12		T138	2		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	2		T139	1		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	1		T33	3		T235	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	1		T135	1		T143	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	1		T140	12		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	8		T92	8		T101	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	9		T40	21		T41	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T51	14		T135	1		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	7		T42	1		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T269	10		T270	11		T271	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	1		T45	9		T87	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17101	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	9		T32	1		T163	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	13		T41	7		T89	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	12		T92	14		T149	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T144	12		T174	5		T203	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T157	19		T238	4		T151	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	14		T174	10		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T10	24		T12	31		T159	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T143	15		T174	6		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	9		T40	12		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T6	13		T138	9		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	19		T164	2		T151	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	1		T169	11		T262	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T143	8		T138	14		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T42	7		T77	1		T276	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	2		T92	11		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	9		T40	12		T41	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	13		T236	4		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	5		T42	9		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T271	8		T277	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T1	6		T45	10		T186	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T278	11		T279	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T161	1		T267	4		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T235	8		T274	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	13		T32	10		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	15		T44	1		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T136	1		T85	1		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T27	1		T41	9		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T140	8		T157	9		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T40	13		T34	2		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T155	15		T137	1		T238	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	2		T32	1		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T1	2		T5	32		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	12		T138	2		T174	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T134	1		T139	1		T272	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	3		T176	14		T169	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	1		T134	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T42	1		T43	1		T235	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	8		T138	15		T92	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	1		T140	12		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T51	14		T135	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T1	1		T6	7		T39	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T267	7		T193	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T274	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	9		T32	1		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	13		T89	8		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T136	12		T92	4		T240	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T41	7		T144	12		T174	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T157	19		T92	10		T149	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	14		T174	10		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T238	4		T99	14		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	15		T195	11		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	9		T10	24		T12	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	13		T138	9		T174	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	13		T151	16		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T169	11		T280	4		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T134	6		T143	8		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T42	7		T43	1		T262	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	2		T138	14		T92	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	5		T35	1		T77	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T51	13		T236	4		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T1	6		T6	5		T39	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2