Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23012

1

T2

20

T3

139

T5

32

auto[ADC_CTRL_FILTER_COND_OUT]

3194

1

T1

18

T6

12

T7

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20361

1

T2

20

T3

139

T6

99

auto[1]

5845

1

T1

18

T5

32

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	254	1			T6	28		T136	22		T148	1
values[1]	665	1			T1	7		T40	15		T41	13
values[2]	758	1			T6	25		T13	1		T14	22
values[3]	607	1			T13	2		T32	1		T134	7
values[4]	583	1			T1	10		T6	12		T27	1
values[5]	789	1			T140	8		T42	10		T155	3
values[6]	888	1			T1	1		T42	8		T134	14
values[7]	782	1			T40	27		T44	1		T144	18
values[8]	565	1			T32	11		T135	1		T235	3
values[9]	3233	1			T5	32		T7	10		T9	1
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T1	7		T13	1		T40	15
values[1]	616	1			T6	25		T13	2		T14	22
values[2]	605	1			T140	12		T134	7		T143	32
values[3]	697	1			T1	10		T6	12		T27	1
values[4]	817	1			T140	8		T42	10		T134	14
values[5]	924	1			T1	1		T40	27		T42	8
values[6]	2967	1			T5	32		T9	1		T10	27
values[7]	652	1			T7	10		T51	27		T32	11
values[8]	755	1			T27	1		T39	18		T40	33
values[9]	154	1			T6	28		T136	9		T259	1
minimum	17244	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T18	2		T150	1		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	7		T13	1		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	14		T34	2		T92	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	2		T14	10		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	1		T134	7		T149	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T143	16		T164	3		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	1		T32	2		T157	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	10		T6	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T140	1		T134	14		T238	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T42	10		T147	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T40	15		T42	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T143	9		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T5	3		T9	1		T10	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T239	4		T240	7		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	7		T161	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	6		T51	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	13		T43	2		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	1		T39	10		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T6	14		T259	1		T206	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T136	9		T247	1		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16978	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T136	2		T36	4		T233	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	4		T150	9		T281	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	2		T41	7		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	11		T34	1		T92	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	12		T186	9		T225	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T140	11		T149	14		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T143	16		T164	2		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	1		T157	8		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	6		T155	2		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T140	7		T238	6		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T147	1		T243	4		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	12		T34	1		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T143	4		T138	14		T45	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T5	29		T141	8		T172	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T240	5		T150	4		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	4		T35	1		T92	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	4		T51	13		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	20		T155	14		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	8		T41	8		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T6	14		T246	16		T110	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T247	10		T191	10		T282	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T36	2		T169	8		T283	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T6	14		T136	13		T259	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T136	9		T148	1		T89	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T235	1		T175	6		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	7		T40	13		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	14		T34	2		T92	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T14	10		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T134	7		T149	18		T186	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T32	1		T143	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	1		T140	1		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	10		T6	6		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T140	1		T157	20		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T42	10		T155	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T42	8		T134	14		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T143	9		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T40	15		T44	1		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T195	12		T239	4		T248	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T32	7		T35	2		T92	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	1		T235	1		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T5	3		T9	1		T10	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	6		T27	1		T39	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T6	14		T284	4		T231	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T89	8		T209	8		T285	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T235	7		T175	4		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	2		T41	7		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T34	1		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	12		T186	9		T225	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T149	14		T186	14		T204	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	16		T164	2		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	11		T32	1		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T6	6		T99	13		T101	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T140	7		T157	8		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T155	2		T138	1		T235	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	1		T174	11		T147	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T143	4		T138	14		T147	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	12		T144	5		T138	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T195	10		T248	11		T275	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	4		T35	1		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T235	2		T236	3		T87	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T5	29		T40	20		T141	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	4		T39	8		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T18	6		T150	10		T281	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T13	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	12		T34	2		T92	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	2		T14	13		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T140	12		T134	1		T149	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T143	17		T164	3		T168	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	1		T32	2		T157	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	1		T6	7		T155	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T140	8		T134	1		T238	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	1		T147	2		T243	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T40	13		T42	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	1		T143	5		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T5	32		T9	1		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T239	1		T240	6		T150	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T32	10		T161	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	8		T51	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	21		T43	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T27	1		T39	9		T41	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	15		T259	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T136	1		T247	11		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17106	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T136	1		T36	5		T233	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T79	20		T82	13		T205	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	6		T40	12		T41	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	13		T34	1		T92	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	9		T186	1		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	6		T149	17		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	15		T164	2		T77	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	1		T157	19		T163	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	9		T6	5		T99	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	13		T238	4		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	9		T250	11		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	14		T42	7		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	8		T138	14		T45	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T10	24		T12	31		T159	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T239	3		T240	6		T252	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	1		T35	1		T92	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	2		T51	13		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	12		T43	1		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	9		T41	7		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T6	13		T206	13		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T136	8		T286	14		T191	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T175	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T136	1		T36	1		T169	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	15		T136	1		T259	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T136	1		T148	1		T89	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T235	8		T175	5		T18	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T40	3		T41	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	12		T34	2		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	1		T14	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	1		T149	15		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	2		T32	1		T143	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	1		T140	12		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	1		T6	7		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T140	8		T157	9		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	1		T155	3		T138	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T42	1		T134	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T1	1		T143	5		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	13		T44	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T195	11		T239	1		T248	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T32	10		T35	2		T92	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T135	1		T235	3		T236	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T5	32		T9	1		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	8		T27	1		T39	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T6	13		T136	12		T230	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T136	8		T89	8		T209	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T175	5		T79	20		T82	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	6		T40	12		T41	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	13		T34	1		T92	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	9		T186	1		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	6		T149	17		T186	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T143	15		T164	2		T77	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	1		T163	13		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	9		T6	5		T99	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T157	19		T238	4		T174	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	9		T250	11		T151	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	7		T134	13		T174	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T143	8		T138	14		T45	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T40	14		T144	12		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T195	11		T239	3		T275	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	1		T35	1		T92	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T236	8		T240	6		T252	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T10	24		T12	31		T40	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	2		T39	9		T41	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2