Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22442

1

T1

7

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3764

1

T1

11

T6

53

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20215

1

T1

11

T2

20

T3

139

auto[1]

5991

1

T1

7

T5

32

T6

65

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T195	19		T177	1		-	-
values[0]	56	1			T27	1		T42	10		T271	30
values[1]	889	1			T1	7		T140	8		T41	16
values[2]	831	1			T161	1		T44	1		T174	22
values[3]	577	1			T140	12		T32	1		T43	2
values[4]	632	1			T13	1		T39	18		T134	14
values[5]	2964	1			T1	1		T5	32		T9	1
values[6]	746	1			T1	10		T7	10		T14	22
values[7]	755	1			T6	25		T27	1		T40	27
values[8]	696	1			T40	33		T155	3		T136	2
values[9]	958	1			T6	40		T13	1		T41	13
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1223	1			T1	7		T27	1		T140	8
values[1]	647	1			T32	1		T161	1		T44	1
values[2]	630	1			T13	1		T39	18		T140	12
values[3]	2924	1			T5	32		T9	1		T10	27
values[4]	664	1			T1	1		T40	15		T134	14
values[5]	814	1			T1	10		T7	10		T14	22
values[6]	629	1			T40	60		T32	11		T135	1
values[7]	721	1			T6	25		T137	1		T87	12
values[8]	743	1			T41	13		T51	27		T32	3
values[9]	108	1			T6	40		T13	1		T300	1
minimum	17103	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T1	7		T140	1		T41	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T27	1		T134	7		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T32	1		T161	1		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	11		T236	9		T164	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	10		T43	2		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T140	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T5	3		T9	1		T10	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T157	20		T146	1		T265	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	14		T136	13		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T40	13		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	6		T238	5		T235	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	10		T14	10		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	7		T155	1		T163	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	28		T135	1		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T87	1		T203	14		T204	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	14		T137	1		T272	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	6		T32	2		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T51	14		T136	9		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T6	6		T13	1		T191	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	14		T300	1		T301	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T42	10		T271	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T140	7		T41	8		T138	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T164	15		T240	5		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T174	11		T92	12		T101	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	8		T236	3		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	8		T145	8		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	11		T144	5		T147	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T5	29		T141	8		T172	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T157	8		T164	2		T302	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T33	1		T147	1		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	2		T143	16		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	4		T238	6		T235	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	12		T155	14		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	4		T155	2		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	32		T174	2		T89	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T87	11		T203	15		T204	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	11		T272	3		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T41	7		T32	1		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T51	13		T138	1		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T6	6		T191	11		T303	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T6	14		T301	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T271	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T195	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T177	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T27	1		T42	10		T271	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	7		T140	1		T41	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	7		T158	1		T236	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T161	1		T44	1		T174	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T164	29		T150	1		T169	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	1		T43	2		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	1		T45	11		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	10		T134	14		T149	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	1		T157	20		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T5	3		T9	1		T10	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T135	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	6		T33	2		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	10		T14	10		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	7		T163	14		T143	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	14		T27	1		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T155	1		T138	10		T174	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	13		T136	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	6		T13	1		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T6	14		T51	14		T136	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T195	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T271	19		T301	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T140	7		T41	8		T138	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T236	3		T240	5		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T174	11		T149	8		T186	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T164	27		T150	4		T169	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T145	8		T186	9		T262	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	11		T45	8		T87	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	8		T149	14		T241	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T157	8		T144	5		T147	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T5	29		T141	8		T172	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T143	16		T34	1		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	4		T33	1		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	12		T40	2		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	4		T143	4		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	11		T40	12		T174	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T155	2		T138	1		T87	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	20		T89	8		T272	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	6		T41	7		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	14		T51	13		T138	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T1	1		T140	8		T41	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T27	1		T134	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	1		T161	1		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	9		T236	4		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T39	9		T43	1		T145	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T140	12		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T5	32		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T157	9		T146	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T134	1		T136	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	1		T40	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	8		T238	7		T235	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	1		T14	13		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T32	10		T155	3		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	34		T135	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T87	12		T203	16		T204	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	12		T137	1		T272	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	8		T32	2		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T51	14		T136	1		T138	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T6	7		T13	1		T191	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T6	15		T300	1		T301	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T42	1		T271	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T1	6		T41	7		T42	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T134	6		T164	16		T240	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T174	10		T92	10		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	10		T236	8		T164	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T39	9		T43	1		T236	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	12		T147	11		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T10	24		T12	31		T159	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	19		T265	2		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T134	13		T136	12		T195	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T40	12		T143	15		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	2		T238	4		T250	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	9		T14	9		T99	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	1		T163	13		T143	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	26		T136	1		T174	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T203	13		T204	16		T252	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	13		T99	14		T280	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	5		T32	1		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T51	13		T136	8		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T6	5		T191	11		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T6	13		T301	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T42	9		T271	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T195	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T177	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T27	1		T42	1		T271	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T140	8		T41	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T134	1		T158	1		T236	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T161	1		T44	1		T174	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T164	29		T150	5		T169	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T32	1		T43	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	12		T45	9		T87	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	9		T134	1		T149	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T157	9		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T5	32		T9	1		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T135	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	8		T33	3		T235	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T14	13		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T32	10		T163	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	12		T27	1		T40	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T155	3		T138	2		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	21		T136	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	7		T13	1		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T6	15		T51	14		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T195	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T42	9		T271	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	6		T41	7		T42	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T134	6		T236	8		T240	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T174	10		T149	10		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T164	27		T169	11		T257	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T43	1		T236	4		T186	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	10		T92	15		T18	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	9		T134	13		T149	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	19		T144	12		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T10	24		T12	31		T159	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T143	15		T34	1		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T7	2		T195	11		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	9		T14	9		T40	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	1		T163	13		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	13		T40	14		T174	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	9		T174	5		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	12		T136	1		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	5		T41	5		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	13		T51	13		T136	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2