Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20123

1

T1

8

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

6083

1

T1

10

T5

32

T6

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20155

1

T1

17

T2

20

T3

139

auto[1]

6051

1

T1

1

T5

32

T6

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T258	16		T304	1		T305	13
values[0]	42	1			T40	15		T146	1		T233	1
values[1]	681	1			T6	12		T27	1		T41	16
values[2]	642	1			T235	3		T250	22		T87	12
values[3]	787	1			T13	1		T41	13		T43	2
values[4]	705	1			T140	12		T32	1		T144	18
values[5]	707	1			T1	8		T6	28		T13	1
values[6]	595	1			T1	10		T51	27		T137	1
values[7]	553	1			T13	1		T137	1		T34	5
values[8]	744	1			T14	22		T155	15		T163	14
values[9]	3638	1			T5	32		T6	25		T7	10
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	806	1			T27	1		T40	15		T42	8
values[1]	3126	1			T5	32		T6	12		T9	1
values[2]	765	1			T41	13		T143	32		T238	11
values[3]	590	1			T13	1		T140	12		T32	1
values[4]	682	1			T1	8		T6	28		T13	1
values[5]	713	1			T1	10		T51	27		T137	2
values[6]	559	1			T13	1		T14	22		T163	14
values[7]	753	1			T155	15		T34	3		T138	2
values[8]	1022	1			T6	25		T7	10		T27	1
values[9]	107	1			T143	13		T148	1		T92	19
minimum	17083	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	2		T145	1		T85	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T27	1		T40	13		T42	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T41	8		T235	2		T36	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1700	1			T5	3		T6	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	16		T174	7		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T41	6		T238	5		T250	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T174	17		T146	1		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T140	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	8		T6	14		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T42	10		T134	14		T157	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T51	14		T137	1		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	10		T137	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T14	10		T163	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	1		T35	2		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T155	1		T34	2		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T147	12		T195	12		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T6	14		T7	6		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T136	13		T268	1		T250	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T143	9		T148	1		T92	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T149	18		T30	10		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16967	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	1		T145	8		T99	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	2		T32	4		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T41	8		T235	9		T36	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1158	1			T5	29		T6	6		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T143	16		T174	2		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T41	7		T238	6		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T174	11		T204	15		T81	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	11		T144	5		T138	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	14		T39	8		T40	32
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	8		T204	18		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	13		T237	2		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T243	4		T92	12		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	12		T45	8		T307	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T34	1		T35	1		T87	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T155	14		T34	1		T138	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	16		T195	10		T176	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	11		T7	4		T138	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T250	13		T176	13		T296	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T143	4		T92	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T149	14		T30	9		T213	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T305	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T258	9		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T233	1		T308	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T40	13		T146	1		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T41	8		T32	2		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	6		T27	1		T42	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T235	1		T150	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T250	10		T87	1		T89	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	16		T174	7		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T13	1		T41	6		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T174	11		T146	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T140	1		T32	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	8		T6	14		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	10		T134	14		T157	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	14		T139	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	10		T137	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T137	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	1		T243	1		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	10		T155	1		T163	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T147	12		T195	12		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T6	14		T7	6		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1827	1			T5	3		T9	1		T10	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T258	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T40	2		T309	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	8		T32	1		T145	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	6		T32	4		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T235	2		T150	4		T21	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T250	12		T87	11		T89	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T143	16		T174	2		T235	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T41	7		T238	6		T147	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T174	11		T36	1		T272	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	11		T144	5		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	14		T39	8		T40	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T157	8		T164	27		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	13		T237	2		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T87	10		T92	12		T205	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	1		T45	8		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	1		T243	4		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	12		T155	14		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T147	16		T195	10		T176	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	11		T7	4		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T5	29		T141	8		T172	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T32	2		T145	9		T85	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T27	1		T40	3		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T41	9		T235	11		T36	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1520	1			T5	32		T6	7		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	17		T174	3		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T41	8		T238	7		T250	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T174	13		T146	1		T204	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T140	12		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	2		T6	15		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	1		T134	1		T157	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T51	14		T137	1		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T137	1		T243	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	1		T14	13		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	2		T35	2		T87	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T155	15		T34	2		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T147	17		T195	11		T176	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T6	12		T7	8		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T136	1		T268	1		T250	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T143	5		T148	1		T92	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T149	15		T30	10		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17083	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	1		T99	14		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	12		T42	7		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	7		T36	1		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T6	5		T10	24		T12	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T143	15		T174	6		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	5		T238	4		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T174	15		T204	13		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	12		T138	14		T164	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	6		T6	13		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T42	9		T134	13		T157	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	13		T237	1		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	9		T92	10		T206	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	9		T163	13		T45	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T35	1		T99	11		T81	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	1		T236	8		T92	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	11		T195	11		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	13		T7	2		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T136	12		T250	11		T296	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T143	8		T92	11		T286	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T149	17		T30	9		T213	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T305	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T258	8		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T233	1		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T40	3		T146	1		T309	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T41	9		T32	2		T145	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	7		T27	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T235	3		T150	5		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T250	13		T87	12		T89	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	17		T174	3		T235	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	1		T41	8		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T174	12		T146	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	12		T32	1		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	2		T6	15		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T42	1		T134	1		T157	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T51	14		T139	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T137	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T137	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	2		T243	5		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	13		T155	15		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T147	17		T195	11		T176	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T6	12		T7	8		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1589	1			T5	32		T9	1		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T258	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T308	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T40	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T41	7		T32	1		T99	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	5		T42	7		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	1		T154	7		T283	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T250	9		T89	8		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T143	15		T174	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T41	5		T43	1		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T174	10		T36	1		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	12		T138	14		T203	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	6		T6	13		T39	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T42	9		T134	13		T157	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	13		T237	1		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	9		T92	10		T206	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T34	1		T45	10		T236	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	1		T99	11		T81	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	9		T163	13		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T147	11		T195	11		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	13		T7	2		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1441	1			T10	24		T12	31		T159	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2