Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22977

1

T1

7

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3229

1

T1

11

T6

28

T7

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19860

1

T1

10

T2

20

T3

132

auto[1]

6346

1

T1

8

T3

7

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	495	1			T3	7		T7	2		T32	2
values[0]	27	1			T205	2		T283	16		T311	1
values[1]	612	1			T140	12		T41	13		T174	6
values[2]	3097	1			T5	32		T6	25		T9	1
values[3]	820	1			T41	16		T51	27		T32	3
values[4]	696	1			T40	27		T140	8		T42	8
values[5]	619	1			T1	7		T7	10		T40	33
values[6]	709	1			T1	1		T6	12		T134	7
values[7]	600	1			T13	2		T14	22		T27	1
values[8]	592	1			T1	10		T13	1		T39	18
values[9]	1290	1			T6	28		T27	1		T40	15
minimum	16649	1			T2	20		T3	132		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	863	1			T6	25		T41	13		T163	14
values[1]	2971	1			T5	32		T9	1		T10	27
values[2]	940	1			T140	8		T41	16		T51	27
values[3]	598	1			T1	7		T40	60		T42	8
values[4]	708	1			T7	10		T134	21		T157	28
values[5]	494	1			T1	1		T13	1		T158	1
values[6]	786	1			T1	10		T6	12		T13	1
values[7]	696	1			T13	1		T27	1		T39	18
values[8]	864	1			T6	28		T43	2		T135	1
values[9]	185	1			T27	1		T155	3		T138	2
minimum	17101	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	14		T41	6		T163	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T174	6		T243	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T5	3		T9	1		T10	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T42	10		T32	7		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T41	8		T51	14		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	1		T32	2		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	7		T42	8		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	28		T135	1		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	14		T157	20		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	6		T134	7		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	1		T268	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T158	1		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	6		T13	1		T174	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	10		T14	10		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T39	10		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T27	1		T136	11		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T43	2		T135	1		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	14		T161	1		T89	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T155	1		T233	1		T204	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T27	1		T138	1		T81	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	11		T41	7		T92	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T243	4		T87	11		T149	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T5	29		T141	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	4		T155	14		T45	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T41	8		T51	13		T238	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	7		T32	1		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T145	8		T35	1		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	32		T235	7		T302	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T157	8		T144	5		T87	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	4		T138	1		T186	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T150	9		T205	8		T312	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	1		T147	1		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	6		T174	2		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	12		T143	4		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	8		T40	2		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T176	13		T99	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T235	2		T92	7		T296	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	14		T89	8		T203	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	2		T204	4		T178	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T138	1		T81	9		T313	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	2		T11	2		T140	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T3	7		T7	2		T32	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T21	1		T314	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T283	9		T311	1		T282	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T205	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T140	1		T41	6		T225	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T174	6		T243	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T5	3		T6	14		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	10		T32	7		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T41	8		T51	14		T238	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	2		T155	1		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T42	8		T32	1		T157	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	15		T140	1		T174	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	7		T134	14		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	6		T40	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	6		T144	13		T174	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T134	7		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	2		T235	1		T240	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	10		T27	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T39	10		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	10		T136	11		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	418	1			T40	13		T135	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T6	14		T27	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16533	1			T2	20		T3	132		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T260	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T21	3		T314	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	7		T282	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T205	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	11		T41	7		T225	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T243	4		T87	11		T149	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T5	29		T6	11		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	4		T45	8		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T41	8		T51	13		T238	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T32	1		T155	14		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T157	8		T145	8		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	12		T140	7		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T87	10		T248	11		T284	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	4		T40	20		T186	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	6		T144	5		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	1		T138	1		T147	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T235	12		T240	5		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	12		T143	4		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	8		T250	13		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T17	1		T176	13		T315	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T40	2		T155	2		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	14		T138	1		T89	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	12		T41	8		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T174	1		T243	5		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T5	32		T9	1		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	1		T32	10		T155	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T41	9		T51	14		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T140	8		T32	2		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	1		T42	1		T145	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	34		T135	1		T235	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T134	1		T157	9		T144	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	8		T134	1		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T268	1		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T158	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	7		T13	1		T174	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T14	13		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T39	9		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T27	1		T136	2		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T43	1		T135	1		T235	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	15		T161	1		T89	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T155	3		T233	1		T204	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T27	1		T138	2		T81	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17100	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	13		T41	5		T163	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T174	5		T149	17		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T10	24		T12	31		T159	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T42	9		T32	1		T45	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	7		T51	13		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T32	1		T174	10		T236	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	6		T42	7		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	26		T168	10		T316	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	13		T157	19		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	2		T134	6		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T252	12		T205	2		T312	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T136	12		T34	1		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	5		T174	6		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	9		T14	9		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	9		T40	12		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T136	9		T99	11		T317	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T43	1		T92	11		T296	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	13		T89	8		T203	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T204	2		T206	13		T178	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T81	5		T200	16		T313	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T254	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	448	1			T3	7		T7	2		T32	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T21	4		T314	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T283	8		T311	1		T282	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T140	12		T41	8		T225	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T174	1		T243	5		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T5	32		T6	12		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	1		T32	10		T45	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T41	9		T51	14		T238	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T32	2		T155	15		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	1		T32	1		T157	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	13		T140	8		T174	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T134	1		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	8		T40	21		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	7		T144	6		T174	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	1		T134	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	2		T235	13		T240	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	13		T27	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T39	9		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T136	2		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T40	3		T135	1		T155	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T6	15		T27	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16649	1			T2	20		T3	132		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T260	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T314	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T283	8		T282	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	5		T225	10		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T174	5		T149	17		T240	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T6	13		T10	24		T12	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	9		T32	1		T45	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	7		T51	13		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	1		T164	16		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T42	7		T157	19		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	14		T174	10		T236	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	6		T134	13		T284	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	2		T40	12		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	5		T144	12		T174	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	6		T34	1		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T240	6		T100	14		T252	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T14	9		T143	8		T92	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	9		T43	1		T250	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	9		T136	9		T317	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T40	12		T147	11		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	13		T89	8		T203	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2