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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 919
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T792 /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2961296923 Aug 10 05:59:19 PM PDT 24 Aug 10 05:59:30 PM PDT 24 32365153925 ps
T793 /workspace/coverage/default/33.adc_ctrl_lowpower_counter.353786634 Aug 10 06:00:52 PM PDT 24 Aug 10 06:01:52 PM PDT 24 32699154248 ps
T794 /workspace/coverage/default/12.adc_ctrl_stress_all.2259348530 Aug 10 05:59:26 PM PDT 24 Aug 10 06:11:38 PM PDT 24 208117027961 ps
T795 /workspace/coverage/default/37.adc_ctrl_smoke.1894043878 Aug 10 06:01:17 PM PDT 24 Aug 10 06:01:30 PM PDT 24 5935882547 ps
T48 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3739240806 Aug 10 05:17:37 PM PDT 24 Aug 10 05:17:41 PM PDT 24 2565543607 ps
T55 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1761065766 Aug 10 05:17:28 PM PDT 24 Aug 10 05:17:31 PM PDT 24 912220500 ps
T49 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3903605076 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:41 PM PDT 24 4885100429 ps
T796 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2296919334 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:14 PM PDT 24 369398511 ps
T797 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2118308037 Aug 10 05:17:56 PM PDT 24 Aug 10 05:17:57 PM PDT 24 358220668 ps
T52 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2873751767 Aug 10 05:17:34 PM PDT 24 Aug 10 05:17:46 PM PDT 24 8649138281 ps
T53 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.107890082 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:40 PM PDT 24 4037010947 ps
T60 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1567544530 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:25 PM PDT 24 455489016 ps
T54 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.58932186 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:40 PM PDT 24 4849611753 ps
T798 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2429766384 Aug 10 05:17:49 PM PDT 24 Aug 10 05:17:50 PM PDT 24 374394073 ps
T61 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2755130022 Aug 10 05:17:44 PM PDT 24 Aug 10 05:17:46 PM PDT 24 737969776 ps
T799 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.206132711 Aug 10 05:17:48 PM PDT 24 Aug 10 05:17:49 PM PDT 24 486378224 ps
T800 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.262979942 Aug 10 05:17:41 PM PDT 24 Aug 10 05:17:42 PM PDT 24 402981220 ps
T62 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4030384892 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:33 PM PDT 24 4376483557 ps
T131 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2480046414 Aug 10 05:17:28 PM PDT 24 Aug 10 05:17:32 PM PDT 24 1066045995 ps
T50 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1789961804 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:59 PM PDT 24 10478726449 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.468612480 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:15 PM PDT 24 300531910 ps
T801 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.847054999 Aug 10 05:17:44 PM PDT 24 Aug 10 05:17:46 PM PDT 24 358856741 ps
T802 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1476048197 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:14 PM PDT 24 458581258 ps
T113 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3479085777 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:31 PM PDT 24 933999070 ps
T127 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1311778462 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:35 PM PDT 24 437583674 ps
T69 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3890859159 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:32 PM PDT 24 326699077 ps
T128 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3626706389 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:26 PM PDT 24 3833865650 ps
T803 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2406275062 Aug 10 05:17:20 PM PDT 24 Aug 10 05:17:22 PM PDT 24 441625977 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3690887675 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:42 PM PDT 24 648849195 ps
T56 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.405573696 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:43 PM PDT 24 8884643943 ps
T804 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1751108172 Aug 10 05:17:51 PM PDT 24 Aug 10 05:17:52 PM PDT 24 305079129 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2281022932 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:15 PM PDT 24 391243942 ps
T805 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.943976294 Aug 10 05:17:22 PM PDT 24 Aug 10 05:17:23 PM PDT 24 479598593 ps
T129 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2481536001 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:38 PM PDT 24 2466676312 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2298415842 Aug 10 05:17:24 PM PDT 24 Aug 10 05:17:29 PM PDT 24 1040609518 ps
T122 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4021678922 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:24 PM PDT 24 505315538 ps
T65 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3384219141 Aug 10 05:17:27 PM PDT 24 Aug 10 05:17:29 PM PDT 24 455738718 ps
T806 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1608444848 Aug 10 05:17:42 PM PDT 24 Aug 10 05:17:44 PM PDT 24 524655484 ps
T807 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2156561359 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:39 PM PDT 24 1138063183 ps
T130 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1496598386 Aug 10 05:17:41 PM PDT 24 Aug 10 05:17:45 PM PDT 24 2621291783 ps
T67 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2528215492 Aug 10 05:17:37 PM PDT 24 Aug 10 05:17:38 PM PDT 24 398135696 ps
T116 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4066230800 Aug 10 05:17:21 PM PDT 24 Aug 10 05:17:23 PM PDT 24 340579427 ps
T808 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3917209586 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:34 PM PDT 24 2191647916 ps
T117 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4219142400 Aug 10 05:17:34 PM PDT 24 Aug 10 05:17:35 PM PDT 24 408032739 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3757896970 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:39 PM PDT 24 4773781809 ps
T810 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1087925738 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:40 PM PDT 24 499959472 ps
T811 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1271922939 Aug 10 05:17:26 PM PDT 24 Aug 10 05:17:27 PM PDT 24 397966336 ps
T118 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3070549802 Aug 10 05:17:43 PM PDT 24 Aug 10 05:17:45 PM PDT 24 316476620 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4129591985 Aug 10 05:17:25 PM PDT 24 Aug 10 05:17:29 PM PDT 24 2336883585 ps
T813 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4182968576 Aug 10 05:17:45 PM PDT 24 Aug 10 05:17:46 PM PDT 24 491489696 ps
T814 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2474350513 Aug 10 05:17:39 PM PDT 24 Aug 10 05:17:40 PM PDT 24 530044085 ps
T70 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4137871540 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:42 PM PDT 24 4268422267 ps
T815 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.900820460 Aug 10 05:17:43 PM PDT 24 Aug 10 05:17:44 PM PDT 24 491535603 ps
T816 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.849427618 Aug 10 05:17:43 PM PDT 24 Aug 10 05:17:45 PM PDT 24 376520222 ps
T119 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.519082317 Aug 10 05:17:12 PM PDT 24 Aug 10 05:17:18 PM PDT 24 1016139531 ps
T103 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.329062121 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:31 PM PDT 24 401154296 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1694945207 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:39 PM PDT 24 451699663 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1435660394 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:32 PM PDT 24 893445523 ps
T818 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.572273014 Aug 10 05:17:55 PM PDT 24 Aug 10 05:17:55 PM PDT 24 480249100 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1285959809 Aug 10 05:17:14 PM PDT 24 Aug 10 05:17:16 PM PDT 24 659173440 ps
T819 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.472090240 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:33 PM PDT 24 384490773 ps
T66 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3031962902 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:38 PM PDT 24 611430616 ps
T820 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.739487714 Aug 10 05:17:44 PM PDT 24 Aug 10 05:17:45 PM PDT 24 389468980 ps
T68 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3693708157 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:26 PM PDT 24 528159667 ps
T821 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1856340574 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:26 PM PDT 24 403627827 ps
T822 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.702347898 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:32 PM PDT 24 393669115 ps
T823 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134682788 Aug 10 05:17:22 PM PDT 24 Aug 10 05:17:23 PM PDT 24 575045259 ps
T824 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.597926821 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:35 PM PDT 24 473196876 ps
T825 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2261129965 Aug 10 05:17:32 PM PDT 24 Aug 10 05:17:34 PM PDT 24 471781654 ps
T121 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.838508076 Aug 10 05:17:14 PM PDT 24 Aug 10 05:17:16 PM PDT 24 981082613 ps
T826 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2334278391 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:34 PM PDT 24 397829185 ps
T827 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2997645112 Aug 10 05:17:42 PM PDT 24 Aug 10 05:17:43 PM PDT 24 558737232 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.129949486 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:37 PM PDT 24 605101612 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1281339985 Aug 10 05:17:21 PM PDT 24 Aug 10 05:17:26 PM PDT 24 8861734708 ps
T123 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2729826164 Aug 10 05:17:30 PM PDT 24 Aug 10 05:18:03 PM PDT 24 47795331694 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.750477340 Aug 10 05:17:21 PM PDT 24 Aug 10 05:18:09 PM PDT 24 13767000052 ps
T829 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3468196868 Aug 10 05:17:39 PM PDT 24 Aug 10 05:17:42 PM PDT 24 537228228 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2115406457 Aug 10 05:17:26 PM PDT 24 Aug 10 05:17:28 PM PDT 24 425017297 ps
T831 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3242406161 Aug 10 05:17:34 PM PDT 24 Aug 10 05:17:37 PM PDT 24 618362334 ps
T125 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3971416191 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:32 PM PDT 24 666908369 ps
T832 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1353588433 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:45 PM PDT 24 4975969130 ps
T833 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1694387710 Aug 10 05:17:43 PM PDT 24 Aug 10 05:17:44 PM PDT 24 486641521 ps
T834 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.867191256 Aug 10 05:17:44 PM PDT 24 Aug 10 05:17:45 PM PDT 24 393576465 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.626212047 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:28 PM PDT 24 4453459605 ps
T836 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1993035955 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:25 PM PDT 24 403755788 ps
T837 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4092879292 Aug 10 05:17:27 PM PDT 24 Aug 10 05:17:31 PM PDT 24 4221397330 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1155442699 Aug 10 05:17:41 PM PDT 24 Aug 10 05:17:42 PM PDT 24 475760267 ps
T839 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1792670567 Aug 10 05:17:41 PM PDT 24 Aug 10 05:17:42 PM PDT 24 308057849 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3511393579 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:31 PM PDT 24 876619149 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3665933455 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:34 PM PDT 24 362681662 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.960242636 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:37 PM PDT 24 4655816845 ps
T843 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.265606523 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:52 PM PDT 24 4720418730 ps
T844 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4263135572 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:43 PM PDT 24 2440900238 ps
T845 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.98813137 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:41 PM PDT 24 299905632 ps
T846 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.379929400 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:37 PM PDT 24 499636742 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.791994534 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:40 PM PDT 24 475249973 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1117562596 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:38 PM PDT 24 506558804 ps
T849 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.400020815 Aug 10 05:17:39 PM PDT 24 Aug 10 05:17:40 PM PDT 24 329009037 ps
T850 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2969637902 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:37 PM PDT 24 809679971 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.61303927 Aug 10 05:17:49 PM PDT 24 Aug 10 05:17:50 PM PDT 24 357750278 ps
T852 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3466100352 Aug 10 05:17:24 PM PDT 24 Aug 10 05:17:25 PM PDT 24 348451324 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4083456035 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:33 PM PDT 24 758102255 ps
T854 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.905833242 Aug 10 05:17:16 PM PDT 24 Aug 10 05:17:20 PM PDT 24 525307557 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.704935549 Aug 10 05:17:26 PM PDT 24 Aug 10 05:17:30 PM PDT 24 2089303652 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1818905573 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:15 PM PDT 24 552562395 ps
T857 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2177276139 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:47 PM PDT 24 4447280332 ps
T858 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2307531073 Aug 10 05:17:34 PM PDT 24 Aug 10 05:17:36 PM PDT 24 2421098377 ps
T859 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4095977248 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:42 PM PDT 24 479585941 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4118446569 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:34 PM PDT 24 447658366 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1408179701 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:26 PM PDT 24 1266497893 ps
T862 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.500681272 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:41 PM PDT 24 380994465 ps
T863 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2535885525 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:36 PM PDT 24 871242602 ps
T864 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1326950672 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:34 PM PDT 24 299586863 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2948880607 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:36 PM PDT 24 519214504 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4242529264 Aug 10 05:17:37 PM PDT 24 Aug 10 05:17:39 PM PDT 24 435589419 ps
T867 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.279311466 Aug 10 05:17:44 PM PDT 24 Aug 10 05:17:46 PM PDT 24 554802209 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1652206915 Aug 10 05:17:34 PM PDT 24 Aug 10 05:17:37 PM PDT 24 3337020043 ps
T869 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1043399565 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:32 PM PDT 24 387833861 ps
T870 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1872686392 Aug 10 05:17:32 PM PDT 24 Aug 10 05:17:38 PM PDT 24 4369848345 ps
T871 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1220099585 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:40 PM PDT 24 346757410 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3957616191 Aug 10 05:17:32 PM PDT 24 Aug 10 05:17:33 PM PDT 24 354558328 ps
T873 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.656126502 Aug 10 05:17:24 PM PDT 24 Aug 10 05:17:25 PM PDT 24 452887904 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2901244373 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:32 PM PDT 24 444983990 ps
T875 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.278465812 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:39 PM PDT 24 444852014 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2272098183 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:33 PM PDT 24 3255692248 ps
T877 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1004486577 Aug 10 05:17:54 PM PDT 24 Aug 10 05:17:55 PM PDT 24 535760959 ps
T878 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2770783180 Aug 10 05:17:39 PM PDT 24 Aug 10 05:17:40 PM PDT 24 410018492 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.605688246 Aug 10 05:17:42 PM PDT 24 Aug 10 05:17:49 PM PDT 24 4737747376 ps
T880 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.405669090 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:34 PM PDT 24 340148575 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2960735741 Aug 10 05:17:13 PM PDT 24 Aug 10 05:17:17 PM PDT 24 3838642180 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2558665315 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:27 PM PDT 24 8948098439 ps
T883 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1163271861 Aug 10 05:17:41 PM PDT 24 Aug 10 05:17:48 PM PDT 24 8122258662 ps
T884 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.685944513 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:37 PM PDT 24 444699976 ps
T885 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.987612150 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:36 PM PDT 24 539225853 ps
T886 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3632755913 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:33 PM PDT 24 428771226 ps
T887 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1340766274 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:31 PM PDT 24 480865750 ps
T888 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2346916593 Aug 10 05:17:30 PM PDT 24 Aug 10 05:17:37 PM PDT 24 2016740158 ps
T889 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4020878058 Aug 10 05:17:15 PM PDT 24 Aug 10 05:18:54 PM PDT 24 26657712073 ps
T890 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.289182696 Aug 10 05:17:42 PM PDT 24 Aug 10 05:17:44 PM PDT 24 525523615 ps
T891 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2770297565 Aug 10 05:17:38 PM PDT 24 Aug 10 05:17:39 PM PDT 24 298752610 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2219628526 Aug 10 05:17:31 PM PDT 24 Aug 10 05:17:33 PM PDT 24 452498617 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1331227578 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:37 PM PDT 24 488217686 ps
T894 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.58785468 Aug 10 05:17:39 PM PDT 24 Aug 10 05:17:50 PM PDT 24 4466638521 ps
T895 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3313205809 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:37 PM PDT 24 366549337 ps
T896 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1373995412 Aug 10 05:17:42 PM PDT 24 Aug 10 05:17:43 PM PDT 24 387561708 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3297925665 Aug 10 05:17:37 PM PDT 24 Aug 10 05:17:45 PM PDT 24 2562368016 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1194551535 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:35 PM PDT 24 583789486 ps
T899 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2402685966 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:41 PM PDT 24 513990606 ps
T72 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4284528839 Aug 10 05:17:33 PM PDT 24 Aug 10 05:17:40 PM PDT 24 4460677019 ps
T900 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1808678089 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:33 PM PDT 24 613014293 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.608617914 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:38 PM PDT 24 455900710 ps
T902 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1395592096 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:40 PM PDT 24 549263341 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3391109511 Aug 10 05:17:25 PM PDT 24 Aug 10 05:17:27 PM PDT 24 499347073 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2090340457 Aug 10 05:17:14 PM PDT 24 Aug 10 05:17:15 PM PDT 24 405267515 ps
T905 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2078690735 Aug 10 05:17:50 PM PDT 24 Aug 10 05:17:51 PM PDT 24 389390884 ps
T906 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2220810757 Aug 10 05:17:29 PM PDT 24 Aug 10 05:17:36 PM PDT 24 8414551362 ps
T907 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2968332796 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:38 PM PDT 24 511937228 ps
T908 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1832483427 Aug 10 05:17:36 PM PDT 24 Aug 10 05:17:37 PM PDT 24 319647275 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1324416040 Aug 10 05:17:32 PM PDT 24 Aug 10 05:17:34 PM PDT 24 445388173 ps
T910 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.689659717 Aug 10 05:17:40 PM PDT 24 Aug 10 05:18:00 PM PDT 24 7950579714 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3042144939 Aug 10 05:17:35 PM PDT 24 Aug 10 05:17:37 PM PDT 24 367816921 ps
T912 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3900511375 Aug 10 05:17:40 PM PDT 24 Aug 10 05:17:41 PM PDT 24 354020806 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3672378620 Aug 10 05:17:24 PM PDT 24 Aug 10 05:17:25 PM PDT 24 367596533 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3332241492 Aug 10 05:17:24 PM PDT 24 Aug 10 05:17:26 PM PDT 24 495459735 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.633944064 Aug 10 05:17:22 PM PDT 24 Aug 10 05:17:24 PM PDT 24 1088505097 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.12049382 Aug 10 05:17:23 PM PDT 24 Aug 10 05:17:25 PM PDT 24 472135238 ps
T917 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.297567864 Aug 10 05:17:26 PM PDT 24 Aug 10 05:17:28 PM PDT 24 2685060441 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4019194723 Aug 10 05:17:25 PM PDT 24 Aug 10 05:17:36 PM PDT 24 3953030269 ps
T919 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1841508168 Aug 10 05:17:22 PM PDT 24 Aug 10 05:17:30 PM PDT 24 4470251941 ps

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.731298514
Short name T7
Test name
Test status
Simulation time 99443112452 ps
CPU time 230.12 seconds
Started Aug 10 06:02:02 PM PDT 24
Finished Aug 10 06:05:52 PM PDT 24
Peak memory 217440 kb
Host smart-b8f098fe-634e-4e99-b6ec-1b82cfaf6cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731298514 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.731298514
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.45450844
Short name T1
Test name
Test status
Simulation time 535104284320 ps
CPU time 335.13 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:05:21 PM PDT 24
Peak memory 201444 kb
Host smart-1cdc2db1-da89-48e4-9f90-ad0b1835111c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45450844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_w
akeup.45450844
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.321100179
Short name T44
Test name
Test status
Simulation time 468165957273 ps
CPU time 1428.8 seconds
Started Aug 10 05:59:20 PM PDT 24
Finished Aug 10 06:23:09 PM PDT 24
Peak memory 209968 kb
Host smart-ad9fed56-9e32-44ee-a871-f78e3fc0a000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321100179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.321100179
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4007753159
Short name T6
Test name
Test status
Simulation time 516429423897 ps
CPU time 1031.14 seconds
Started Aug 10 06:03:04 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 201472 kb
Host smart-cd54f2ad-0e62-4d2b-9861-437427b6591b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007753159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4007753159
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.507428459
Short name T149
Test name
Test status
Simulation time 498790119963 ps
CPU time 417.95 seconds
Started Aug 10 06:01:19 PM PDT 24
Finished Aug 10 06:08:17 PM PDT 24
Peak memory 201408 kb
Host smart-4733be12-dcfa-4f81-bd41-235d5e58a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507428459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.507428459
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3190438316
Short name T164
Test name
Test status
Simulation time 493720433871 ps
CPU time 1162.52 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:18:53 PM PDT 24
Peak memory 201516 kb
Host smart-c8dc943f-4ebe-467a-9e1a-584be216bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190438316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3190438316
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3992491997
Short name T92
Test name
Test status
Simulation time 518982662181 ps
CPU time 1127.05 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 201464 kb
Host smart-2d82910c-aa09-4ddb-b9bb-f538ab295c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992491997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3992491997
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2648541126
Short name T32
Test name
Test status
Simulation time 100655339012 ps
CPU time 233.3 seconds
Started Aug 10 06:02:52 PM PDT 24
Finished Aug 10 06:06:45 PM PDT 24
Peak memory 210140 kb
Host smart-a332e994-91a3-490f-a723-a88d8877b10b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648541126 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2648541126
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.681750680
Short name T35
Test name
Test status
Simulation time 157696498726 ps
CPU time 89 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:02:32 PM PDT 24
Peak memory 209748 kb
Host smart-b77c98b5-8064-48f5-b767-c57b6f4c47e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681750680 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.681750680
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3018023979
Short name T40
Test name
Test status
Simulation time 500665667328 ps
CPU time 1133.58 seconds
Started Aug 10 06:00:13 PM PDT 24
Finished Aug 10 06:19:07 PM PDT 24
Peak memory 201460 kb
Host smart-37793939-4488-4850-93b7-5d79a2aa0006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018023979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3018023979
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2873751767
Short name T52
Test name
Test status
Simulation time 8649138281 ps
CPU time 12.32 seconds
Started Aug 10 05:17:34 PM PDT 24
Finished Aug 10 05:17:46 PM PDT 24
Peak memory 201584 kb
Host smart-e571e8ca-5019-4346-bfa6-69a65855f046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873751767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2873751767
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2654725156
Short name T150
Test name
Test status
Simulation time 479677025015 ps
CPU time 87.85 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:02:38 PM PDT 24
Peak memory 201432 kb
Host smart-e9cc589b-3014-4f0d-93cf-16dd96f9768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654725156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2654725156
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3462076538
Short name T204
Test name
Test status
Simulation time 506502022772 ps
CPU time 1079.22 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:19:02 PM PDT 24
Peak memory 201360 kb
Host smart-f3bc74db-ca1b-4fb9-b6ab-79890c1bee38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462076538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3462076538
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3482577807
Short name T41
Test name
Test status
Simulation time 346325658001 ps
CPU time 147.6 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:01:49 PM PDT 24
Peak memory 201488 kb
Host smart-f7383ce0-30a8-4512-b2b3-39b9be2019ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482577807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3482577807
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.4075419319
Short name T138
Test name
Test status
Simulation time 527295151129 ps
CPU time 846.45 seconds
Started Aug 10 06:02:14 PM PDT 24
Finished Aug 10 06:16:21 PM PDT 24
Peak memory 201468 kb
Host smart-ce74b43b-8da7-444e-ab38-cfc43cf4ec05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075419319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.4075419319
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4265296457
Short name T354
Test name
Test status
Simulation time 383984319 ps
CPU time 1.04 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 05:59:28 PM PDT 24
Peak memory 201192 kb
Host smart-52fac247-ba6e-4ebe-b075-84d65c0ea0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265296457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4265296457
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1789961804
Short name T50
Test name
Test status
Simulation time 10478726449 ps
CPU time 36.02 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:59 PM PDT 24
Peak memory 201476 kb
Host smart-af19e8ab-85b8-4d54-a6c9-15ccea8d18be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789961804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1789961804
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3069804970
Short name T195
Test name
Test status
Simulation time 358793116623 ps
CPU time 161.32 seconds
Started Aug 10 05:59:56 PM PDT 24
Finished Aug 10 06:02:38 PM PDT 24
Peak memory 201432 kb
Host smart-0a8fcba7-2eba-4343-8349-30fac913465f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069804970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3069804970
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1171895050
Short name T283
Test name
Test status
Simulation time 497791687015 ps
CPU time 303.2 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:04:51 PM PDT 24
Peak memory 201436 kb
Host smart-3648beb0-ce08-4d92-8a61-e6f6cf10bf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171895050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1171895050
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1761065766
Short name T55
Test name
Test status
Simulation time 912220500 ps
CPU time 2.56 seconds
Started Aug 10 05:17:28 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201588 kb
Host smart-64b24826-2334-4fa9-acfd-2601ae7deac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761065766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1761065766
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1633618801
Short name T42
Test name
Test status
Simulation time 342383008532 ps
CPU time 800.7 seconds
Started Aug 10 05:59:11 PM PDT 24
Finished Aug 10 06:12:32 PM PDT 24
Peak memory 201448 kb
Host smart-fba5bcf8-6c67-4f75-ac50-9c5408d7373e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633618801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1633618801
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2054043029
Short name T141
Test name
Test status
Simulation time 162095301423 ps
CPU time 158.67 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:02:10 PM PDT 24
Peak memory 201464 kb
Host smart-c0ae8771-d643-4326-a33c-f1ad79778da7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054043029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2054043029
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2290552003
Short name T252
Test name
Test status
Simulation time 530574785580 ps
CPU time 1150.1 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 201520 kb
Host smart-5fd580d1-bd3a-4b30-a19e-146d9eb4ba14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290552003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2290552003
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2860512297
Short name T241
Test name
Test status
Simulation time 496704319763 ps
CPU time 107.08 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:01:53 PM PDT 24
Peak memory 201324 kb
Host smart-37b42cd5-1f34-4b1b-bc61-4af614a3bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860512297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2860512297
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.45411021
Short name T291
Test name
Test status
Simulation time 350856279430 ps
CPU time 746.91 seconds
Started Aug 10 05:59:01 PM PDT 24
Finished Aug 10 06:11:28 PM PDT 24
Peak memory 201476 kb
Host smart-fe8c7bed-027c-4eee-8c66-de1d5c196438
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45411021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating
.45411021
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2195495591
Short name T258
Test name
Test status
Simulation time 510007552910 ps
CPU time 351.82 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:06:04 PM PDT 24
Peak memory 201424 kb
Host smart-f206d1c1-acd1-445c-a207-3edc9bddd049
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195495591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2195495591
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3136283308
Short name T136
Test name
Test status
Simulation time 562607752007 ps
CPU time 521.58 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:09:04 PM PDT 24
Peak memory 201444 kb
Host smart-6eec1e76-a593-47b3-a1c7-e81ab4d133a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136283308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3136283308
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3928170802
Short name T57
Test name
Test status
Simulation time 7986516924 ps
CPU time 5.67 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 218232 kb
Host smart-30a9b550-c205-4f25-b718-f76e913e8e16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928170802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3928170802
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.548255883
Short name T246
Test name
Test status
Simulation time 1669037981818 ps
CPU time 1704.44 seconds
Started Aug 10 06:00:13 PM PDT 24
Finished Aug 10 06:28:38 PM PDT 24
Peak memory 210024 kb
Host smart-d0f11fc8-4e1c-499d-a695-7729fb824229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548255883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
548255883
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3103381947
Short name T271
Test name
Test status
Simulation time 500196557349 ps
CPU time 559.44 seconds
Started Aug 10 06:02:49 PM PDT 24
Finished Aug 10 06:12:09 PM PDT 24
Peak memory 201460 kb
Host smart-8cf19e2b-1b71-4cc6-ad19-6fd35ebd43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103381947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3103381947
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.11024773
Short name T13
Test name
Test status
Simulation time 484048717050 ps
CPU time 262.86 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:04:14 PM PDT 24
Peak memory 201448 kb
Host smart-dd0257f6-1023-40d9-b256-c0e0c6a69399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11024773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.11024773
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1400610940
Short name T316
Test name
Test status
Simulation time 559436078968 ps
CPU time 106.32 seconds
Started Aug 10 05:59:37 PM PDT 24
Finished Aug 10 06:01:24 PM PDT 24
Peak memory 201444 kb
Host smart-beb1f711-87f5-4469-8de1-4d0d4f2fe9a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400610940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1400610940
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2379833842
Short name T205
Test name
Test status
Simulation time 579400185746 ps
CPU time 479.25 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:07:02 PM PDT 24
Peak memory 201488 kb
Host smart-90c914c7-3fe9-4b82-ae78-33a5ff00d57b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379833842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2379833842
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.963620736
Short name T43
Test name
Test status
Simulation time 4558826893741 ps
CPU time 3081.84 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:50:44 PM PDT 24
Peak memory 218220 kb
Host smart-6a09ec26-5820-4f7d-a4ed-c133b848df9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963620736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
963620736
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2084166333
Short name T19
Test name
Test status
Simulation time 233207453330 ps
CPU time 218.58 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 06:02:33 PM PDT 24
Peak memory 210184 kb
Host smart-a2ca8249-e673-47da-a458-a9470d8a88b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084166333 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2084166333
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3864245047
Short name T179
Test name
Test status
Simulation time 516772171027 ps
CPU time 291.77 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:04:41 PM PDT 24
Peak memory 201400 kb
Host smart-afef761d-36c7-47f6-9679-25a47f4f0a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864245047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3864245047
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1856340574
Short name T821
Test name
Test status
Simulation time 403627827 ps
CPU time 3.19 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 218072 kb
Host smart-84e41811-7e34-4719-a241-7d0b7536dfe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856340574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1856340574
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1417025212
Short name T309
Test name
Test status
Simulation time 329650273422 ps
CPU time 717.49 seconds
Started Aug 10 05:59:27 PM PDT 24
Finished Aug 10 06:11:24 PM PDT 24
Peak memory 201400 kb
Host smart-f570cb2c-a2d9-483f-aae1-188f338f7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417025212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1417025212
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2159249346
Short name T324
Test name
Test status
Simulation time 518551481470 ps
CPU time 351.64 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:07:02 PM PDT 24
Peak memory 201416 kb
Host smart-32d2db28-c869-4757-9f5c-5fed83c11471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159249346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2159249346
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.623217743
Short name T267
Test name
Test status
Simulation time 536181223020 ps
CPU time 301.55 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:04:09 PM PDT 24
Peak memory 201336 kb
Host smart-38031493-fd71-4e8c-9528-1c3d61fd588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623217743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.623217743
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2661914872
Short name T203
Test name
Test status
Simulation time 384385567868 ps
CPU time 945.56 seconds
Started Aug 10 05:59:05 PM PDT 24
Finished Aug 10 06:14:51 PM PDT 24
Peak memory 201392 kb
Host smart-6e9a28cc-4b58-4074-b28a-50a90b3295a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661914872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2661914872
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1805390111
Short name T175
Test name
Test status
Simulation time 516545087297 ps
CPU time 889.33 seconds
Started Aug 10 06:00:21 PM PDT 24
Finished Aug 10 06:15:11 PM PDT 24
Peak memory 210044 kb
Host smart-90267de0-487b-4110-9453-8b2ef140ac73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805390111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1805390111
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.369250762
Short name T255
Test name
Test status
Simulation time 200786100657 ps
CPU time 16.95 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 05:59:47 PM PDT 24
Peak memory 201568 kb
Host smart-fa153736-542c-4f6a-9358-e344d8eab6da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369250762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.369250762
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.468612480
Short name T126
Test name
Test status
Simulation time 300531910 ps
CPU time 1.4 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:15 PM PDT 24
Peak memory 201248 kb
Host smart-5bf33f1b-66ab-47a4-946e-d81335a20bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468612480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.468612480
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1823204012
Short name T143
Test name
Test status
Simulation time 340341123046 ps
CPU time 735.42 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 06:11:57 PM PDT 24
Peak memory 201440 kb
Host smart-beadccf1-f44a-4cc7-8c01-9c7693b2400b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823204012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1823204012
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4192055489
Short name T308
Test name
Test status
Simulation time 516193795134 ps
CPU time 1140.99 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 06:17:59 PM PDT 24
Peak memory 201456 kb
Host smart-275f22ba-9627-41ec-82eb-ab6096f7a46c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192055489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4192055489
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.358647711
Short name T266
Test name
Test status
Simulation time 486550377549 ps
CPU time 1049.47 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 06:17:14 PM PDT 24
Peak memory 201480 kb
Host smart-17ebd2ce-1f05-4a28-ad60-f7cdf0361584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358647711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.358647711
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4239326981
Short name T212
Test name
Test status
Simulation time 539412576244 ps
CPU time 357.8 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:05:17 PM PDT 24
Peak memory 201452 kb
Host smart-320e0935-e717-4cef-8a7e-220e9ba49b7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239326981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4239326981
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.503132710
Short name T234
Test name
Test status
Simulation time 523882724564 ps
CPU time 211.85 seconds
Started Aug 10 05:59:43 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 201452 kb
Host smart-992f2220-10d4-466f-9f27-6a6e7b818ca0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503132710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.503132710
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.953233258
Short name T84
Test name
Test status
Simulation time 665889573809 ps
CPU time 654.61 seconds
Started Aug 10 06:01:25 PM PDT 24
Finished Aug 10 06:12:20 PM PDT 24
Peak memory 210092 kb
Host smart-0db18fbd-a9a7-49ed-ac2f-2f5a84a67def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953233258 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.953233258
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4012378952
Short name T254
Test name
Test status
Simulation time 524849073720 ps
CPU time 1020.73 seconds
Started Aug 10 06:03:12 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 201452 kb
Host smart-bea65814-d363-4882-93de-782747f338f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012378952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4012378952
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2031122176
Short name T21
Test name
Test status
Simulation time 395400791585 ps
CPU time 617.28 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:09:37 PM PDT 24
Peak memory 210124 kb
Host smart-5086cc17-7022-4399-9800-b77362fbdb64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031122176 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2031122176
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3708251427
Short name T287
Test name
Test status
Simulation time 165680519515 ps
CPU time 93.28 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:01:12 PM PDT 24
Peak memory 201632 kb
Host smart-7fe7c6a8-8fda-44d3-879c-f54671d5e3d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708251427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3708251427
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3993330895
Short name T235
Test name
Test status
Simulation time 497120506085 ps
CPU time 276.04 seconds
Started Aug 10 06:01:26 PM PDT 24
Finished Aug 10 06:06:02 PM PDT 24
Peak memory 201432 kb
Host smart-773ebe9e-e96b-4a79-be20-5cf5e6a6c084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993330895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3993330895
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3639030725
Short name T99
Test name
Test status
Simulation time 354546197185 ps
CPU time 769.01 seconds
Started Aug 10 06:02:33 PM PDT 24
Finished Aug 10 06:15:22 PM PDT 24
Peak memory 201480 kb
Host smart-9f07efa2-20c4-4aee-9be6-3085bc30d2c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639030725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3639030725
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2174902088
Short name T140
Test name
Test status
Simulation time 342697615208 ps
CPU time 402.71 seconds
Started Aug 10 05:59:12 PM PDT 24
Finished Aug 10 06:05:55 PM PDT 24
Peak memory 201452 kb
Host smart-21a51c90-93c2-46eb-8d8b-7b2dd50824ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174902088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2174902088
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1100063180
Short name T93
Test name
Test status
Simulation time 33953543429 ps
CPU time 101.85 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:00:59 PM PDT 24
Peak memory 210080 kb
Host smart-42881a0b-6b7d-493a-9a7e-f6c1e4de0c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100063180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1100063180
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1335644954
Short name T191
Test name
Test status
Simulation time 507207314760 ps
CPU time 111.53 seconds
Started Aug 10 05:59:13 PM PDT 24
Finished Aug 10 06:01:05 PM PDT 24
Peak memory 201444 kb
Host smart-57b45699-5c67-404e-babd-52fd80323b16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335644954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1335644954
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.21638016
Short name T10
Test name
Test status
Simulation time 595988095289 ps
CPU time 1347.33 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:22:00 PM PDT 24
Peak memory 201464 kb
Host smart-c0c34649-fbaf-4a8d-9fbd-e59640173f44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.21638016
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.360380212
Short name T45
Test name
Test status
Simulation time 332311989573 ps
CPU time 804.9 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 210024 kb
Host smart-08b06582-5e2a-438c-9677-72a09e1c60e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360380212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
360380212
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3863988982
Short name T155
Test name
Test status
Simulation time 332035252503 ps
CPU time 831.18 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:13:28 PM PDT 24
Peak memory 201440 kb
Host smart-34dd33b3-f8f9-452e-946e-c07f221746c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863988982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3863988982
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.969945532
Short name T305
Test name
Test status
Simulation time 323505482430 ps
CPU time 336.16 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:05:23 PM PDT 24
Peak memory 201468 kb
Host smart-1fa2a436-9a24-4178-8281-f66bd05814a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969945532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.969945532
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.49065905
Short name T232
Test name
Test status
Simulation time 160189619263 ps
CPU time 269.8 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:04:21 PM PDT 24
Peak memory 201344 kb
Host smart-29f5d1c5-fbc7-4b01-b472-18d9a14d767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49065905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.49065905
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1835333224
Short name T310
Test name
Test status
Simulation time 64770154538 ps
CPU time 143.84 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:02:30 PM PDT 24
Peak memory 209796 kb
Host smart-ac2a363a-5120-4987-aea1-bf2bc29fc0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835333224 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1835333224
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1526938401
Short name T24
Test name
Test status
Simulation time 89573114588 ps
CPU time 94.6 seconds
Started Aug 10 06:00:24 PM PDT 24
Finished Aug 10 06:01:59 PM PDT 24
Peak memory 209780 kb
Host smart-81b1dee8-ef04-422e-ba94-f6be450e5055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526938401 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1526938401
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1085042936
Short name T321
Test name
Test status
Simulation time 388627452443 ps
CPU time 206 seconds
Started Aug 10 06:01:18 PM PDT 24
Finished Aug 10 06:04:44 PM PDT 24
Peak memory 201428 kb
Host smart-838e0d30-6624-4da7-8259-54c4fd9640c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085042936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1085042936
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2193284913
Short name T325
Test name
Test status
Simulation time 170038371241 ps
CPU time 153.15 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:01:51 PM PDT 24
Peak memory 201388 kb
Host smart-b768e613-8287-4f63-91b6-11b58fb2d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193284913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2193284913
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.58932186
Short name T54
Test name
Test status
Simulation time 4849611753 ps
CPU time 4.38 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201648 kb
Host smart-b669ec0d-8d5d-4a19-912f-903ef7a7e258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58932186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_int
g_err.58932186
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1389151190
Short name T572
Test name
Test status
Simulation time 173994936549 ps
CPU time 398.19 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:06:00 PM PDT 24
Peak memory 201456 kb
Host smart-553fc599-f1c7-43ab-99e9-66b91d0a1741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389151190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1389151190
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1877221751
Short name T260
Test name
Test status
Simulation time 345523086535 ps
CPU time 683.96 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:11:10 PM PDT 24
Peak memory 201324 kb
Host smart-1a747daf-4695-4c5a-925f-d03e91b160e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877221751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1877221751
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1558640744
Short name T296
Test name
Test status
Simulation time 498080763531 ps
CPU time 1094.18 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 212432 kb
Host smart-ecedd49d-cd98-4718-8611-70b3e738a933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558640744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1558640744
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3771685475
Short name T226
Test name
Test status
Simulation time 109138123343 ps
CPU time 392.4 seconds
Started Aug 10 06:00:33 PM PDT 24
Finished Aug 10 06:07:06 PM PDT 24
Peak memory 201940 kb
Host smart-b3e76fce-1526-4783-8240-7fe86e0cb8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771685475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3771685475
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2820418215
Short name T177
Test name
Test status
Simulation time 496044104961 ps
CPU time 1140.08 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 201400 kb
Host smart-45249ad2-78c0-4da2-ae7a-85d50c0d90c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820418215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2820418215
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1642730808
Short name T210
Test name
Test status
Simulation time 500397560691 ps
CPU time 322.3 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 06:04:45 PM PDT 24
Peak memory 201452 kb
Host smart-8f4c6590-4f18-4f53-b403-1ed475f54935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642730808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1642730808
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1786485004
Short name T348
Test name
Test status
Simulation time 119019006161 ps
CPU time 472.31 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 06:07:07 PM PDT 24
Peak memory 201812 kb
Host smart-a68ebc53-0812-412d-a0e7-97559c1b11e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786485004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1786485004
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3487753092
Short name T261
Test name
Test status
Simulation time 159502712615 ps
CPU time 98.52 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:01:09 PM PDT 24
Peak memory 201468 kb
Host smart-1fc9c82a-9b6b-45ba-9f3f-90f8cf18ea07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487753092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3487753092
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1788801370
Short name T611
Test name
Test status
Simulation time 421617732064 ps
CPU time 1227.53 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 210136 kb
Host smart-c29f1fde-5cd4-4d7b-87e3-9118c38ccb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788801370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1788801370
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4197249447
Short name T347
Test name
Test status
Simulation time 76355348224 ps
CPU time 302.32 seconds
Started Aug 10 05:59:37 PM PDT 24
Finished Aug 10 06:04:39 PM PDT 24
Peak memory 202000 kb
Host smart-3e12fb3d-e2bb-4d2c-a34e-e09480e9d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197249447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4197249447
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3347427005
Short name T81
Test name
Test status
Simulation time 743630798339 ps
CPU time 182.77 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:02:37 PM PDT 24
Peak memory 210160 kb
Host smart-45e4e000-8076-4535-8c16-11107f28747f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347427005 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3347427005
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2864394049
Short name T336
Test name
Test status
Simulation time 490613031340 ps
CPU time 552.08 seconds
Started Aug 10 05:59:47 PM PDT 24
Finished Aug 10 06:08:59 PM PDT 24
Peak memory 201444 kb
Host smart-76df55a1-d04a-4c4a-9563-afd90f6a0dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864394049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2864394049
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4017969849
Short name T220
Test name
Test status
Simulation time 104228506112 ps
CPU time 562.11 seconds
Started Aug 10 06:00:16 PM PDT 24
Finished Aug 10 06:09:39 PM PDT 24
Peak memory 201740 kb
Host smart-4782597d-9e45-4268-b732-29d447184c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017969849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4017969849
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.961435356
Short name T279
Test name
Test status
Simulation time 570989894638 ps
CPU time 864.87 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:14:48 PM PDT 24
Peak memory 201328 kb
Host smart-ad83845c-12dd-4050-b489-f923c40628ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961435356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.961435356
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3204422826
Short name T314
Test name
Test status
Simulation time 494899513130 ps
CPU time 101.67 seconds
Started Aug 10 06:00:41 PM PDT 24
Finished Aug 10 06:02:23 PM PDT 24
Peak memory 201468 kb
Host smart-2b8fffda-b9ce-428d-9479-1ef3712b1f20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204422826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3204422826
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2751751011
Short name T263
Test name
Test status
Simulation time 168274833323 ps
CPU time 194.58 seconds
Started Aug 10 06:01:05 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 201448 kb
Host smart-1864537e-f034-49a1-be9f-0d7042e3a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751751011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2751751011
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4150157236
Short name T274
Test name
Test status
Simulation time 182719766204 ps
CPU time 27.84 seconds
Started Aug 10 06:01:26 PM PDT 24
Finished Aug 10 06:01:54 PM PDT 24
Peak memory 201452 kb
Host smart-11b541ec-8155-4911-8d4a-53fad5d277c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150157236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4150157236
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1370353355
Short name T208
Test name
Test status
Simulation time 580108361078 ps
CPU time 309.04 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:07:32 PM PDT 24
Peak memory 201444 kb
Host smart-9b4f27e5-f081-465d-8fc2-57db55f39a20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370353355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1370353355
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3971416191
Short name T125
Test name
Test status
Simulation time 666908369 ps
CPU time 1.83 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201468 kb
Host smart-dadf920e-5c31-4981-b500-41b47eb375dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971416191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3971416191
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.519082317
Short name T119
Test name
Test status
Simulation time 1016139531 ps
CPU time 5.59 seconds
Started Aug 10 05:17:12 PM PDT 24
Finished Aug 10 05:17:18 PM PDT 24
Peak memory 201376 kb
Host smart-f91273d1-1742-464c-a574-7d5d6e65528b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519082317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.519082317
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2480046414
Short name T131
Test name
Test status
Simulation time 1066045995 ps
CPU time 3.15 seconds
Started Aug 10 05:17:28 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201356 kb
Host smart-743d4396-aad6-4f73-aeae-ddafbabd7e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480046414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2480046414
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2090340457
Short name T904
Test name
Test status
Simulation time 405267515 ps
CPU time 1.03 seconds
Started Aug 10 05:17:14 PM PDT 24
Finished Aug 10 05:17:15 PM PDT 24
Peak memory 201512 kb
Host smart-d0c14848-2778-409e-8ea8-c4a0e7982b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090340457 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2090340457
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1832483427
Short name T908
Test name
Test status
Simulation time 319647275 ps
CPU time 1.39 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201264 kb
Host smart-4b10f63b-76eb-4992-89ee-54e5e2c0d968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832483427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1832483427
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4129591985
Short name T812
Test name
Test status
Simulation time 2336883585 ps
CPU time 3.35 seconds
Started Aug 10 05:17:25 PM PDT 24
Finished Aug 10 05:17:29 PM PDT 24
Peak memory 201408 kb
Host smart-06e0c573-1412-4632-bfb5-7a36dc9e584c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129591985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4129591985
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.905833242
Short name T854
Test name
Test status
Simulation time 525307557 ps
CPU time 4.24 seconds
Started Aug 10 05:17:16 PM PDT 24
Finished Aug 10 05:17:20 PM PDT 24
Peak memory 201668 kb
Host smart-c0abb807-d0d6-4e2c-b5cd-c2652f107a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905833242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.905833242
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2177276139
Short name T857
Test name
Test status
Simulation time 4447280332 ps
CPU time 10.52 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:47 PM PDT 24
Peak memory 201556 kb
Host smart-ea526ddc-ab97-4031-96ca-2a014005924d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177276139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2177276139
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3479085777
Short name T113
Test name
Test status
Simulation time 933999070 ps
CPU time 1.94 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201520 kb
Host smart-ab20e3e6-4d02-410a-8e4d-e7e4283546b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479085777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3479085777
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4020878058
Short name T889
Test name
Test status
Simulation time 26657712073 ps
CPU time 99.4 seconds
Started Aug 10 05:17:15 PM PDT 24
Finished Aug 10 05:18:54 PM PDT 24
Peak memory 201616 kb
Host smart-b903d8a3-f5e4-4837-b71a-ef6174842e28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020878058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4020878058
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.838508076
Short name T121
Test name
Test status
Simulation time 981082613 ps
CPU time 1.78 seconds
Started Aug 10 05:17:14 PM PDT 24
Finished Aug 10 05:17:16 PM PDT 24
Peak memory 201248 kb
Host smart-c3a0999f-8471-4334-98a3-e3f4c7b413b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838508076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.838508076
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2528215492
Short name T67
Test name
Test status
Simulation time 398135696 ps
CPU time 1.28 seconds
Started Aug 10 05:17:37 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201408 kb
Host smart-ba127724-14c9-43a3-bce3-a99d89f91241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528215492 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2528215492
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2281022932
Short name T114
Test name
Test status
Simulation time 391243942 ps
CPU time 1.02 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:15 PM PDT 24
Peak memory 201384 kb
Host smart-4e20744e-9491-4ace-9a6c-ee0611c78090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281022932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2281022932
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2296919334
Short name T796
Test name
Test status
Simulation time 369398511 ps
CPU time 1.43 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:14 PM PDT 24
Peak memory 201320 kb
Host smart-d039e3f6-083f-482d-b8a3-3d6a03be0301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296919334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2296919334
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.704935549
Short name T855
Test name
Test status
Simulation time 2089303652 ps
CPU time 3.91 seconds
Started Aug 10 05:17:26 PM PDT 24
Finished Aug 10 05:17:30 PM PDT 24
Peak memory 201344 kb
Host smart-c63af758-5abc-4817-8f74-614ea872e660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704935549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.704935549
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.633944064
Short name T915
Test name
Test status
Simulation time 1088505097 ps
CPU time 2.25 seconds
Started Aug 10 05:17:22 PM PDT 24
Finished Aug 10 05:17:24 PM PDT 24
Peak memory 201656 kb
Host smart-29a55a32-af13-447e-8fbb-ac4d22d340aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633944064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.633944064
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2960735741
Short name T881
Test name
Test status
Simulation time 3838642180 ps
CPU time 4 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:17 PM PDT 24
Peak memory 201584 kb
Host smart-f1924c08-6fb7-4a3f-8721-ed628843b2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960735741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2960735741
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.656126502
Short name T873
Test name
Test status
Simulation time 452887904 ps
CPU time 1.09 seconds
Started Aug 10 05:17:24 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201488 kb
Host smart-b246d96e-26bc-467b-9988-e84fda7521b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656126502 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.656126502
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1117562596
Short name T848
Test name
Test status
Simulation time 506558804 ps
CPU time 1.45 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201540 kb
Host smart-d8390cc5-f4e7-46e0-afa8-beb7fd7beed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117562596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1117562596
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1271922939
Short name T811
Test name
Test status
Simulation time 397966336 ps
CPU time 0.87 seconds
Started Aug 10 05:17:26 PM PDT 24
Finished Aug 10 05:17:27 PM PDT 24
Peak memory 201364 kb
Host smart-d3af5e57-c777-4762-a176-b933e2bed161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271922939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1271922939
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3917209586
Short name T808
Test name
Test status
Simulation time 2191647916 ps
CPU time 1.94 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201312 kb
Host smart-217f2f54-7a42-491f-9f58-2d6ad8c7e8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917209586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3917209586
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2220810757
Short name T906
Test name
Test status
Simulation time 8414551362 ps
CPU time 7.31 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201528 kb
Host smart-eea5270e-0ad2-452a-bb43-9e14f9b9c1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220810757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2220810757
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2901244373
Short name T874
Test name
Test status
Simulation time 444983990 ps
CPU time 2.1 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201512 kb
Host smart-648e9430-90a4-4861-82cf-f623753fa290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901244373 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2901244373
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3070549802
Short name T118
Test name
Test status
Simulation time 316476620 ps
CPU time 1.41 seconds
Started Aug 10 05:17:43 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201392 kb
Host smart-f32bc3fe-2165-4303-874c-bffb4ed77863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070549802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3070549802
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.987612150
Short name T885
Test name
Test status
Simulation time 539225853 ps
CPU time 0.78 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201376 kb
Host smart-7ae49177-a908-432a-babf-ffe266444be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987612150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.987612150
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2307531073
Short name T858
Test name
Test status
Simulation time 2421098377 ps
CPU time 1.82 seconds
Started Aug 10 05:17:34 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201224 kb
Host smart-67df9408-2aa9-4550-907f-0a6a0419bfe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307531073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2307531073
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1808678089
Short name T900
Test name
Test status
Simulation time 613014293 ps
CPU time 3.12 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 209816 kb
Host smart-b2b18449-a9dd-48b8-9e64-dc0793ab57c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808678089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1808678089
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.405573696
Short name T56
Test name
Test status
Simulation time 8884643943 ps
CPU time 7.53 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:43 PM PDT 24
Peak memory 201684 kb
Host smart-421f3d51-5cfc-4d98-a50b-10f59ba0fd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405573696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.405573696
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.329062121
Short name T103
Test name
Test status
Simulation time 401154296 ps
CPU time 1.14 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201508 kb
Host smart-fbbaa5ba-bdc6-4de1-a28b-74ef3b176a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329062121 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.329062121
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1311778462
Short name T127
Test name
Test status
Simulation time 437583674 ps
CPU time 1.75 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:35 PM PDT 24
Peak memory 201216 kb
Host smart-cfcadf46-e3ae-4e66-bf15-874e5c3cb143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311778462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1311778462
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3042144939
Short name T911
Test name
Test status
Simulation time 367816921 ps
CPU time 1.46 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201284 kb
Host smart-1e937650-5907-4f90-b916-a3beaeea2cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042144939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3042144939
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3903605076
Short name T49
Test name
Test status
Simulation time 4885100429 ps
CPU time 5.38 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201448 kb
Host smart-fa83b3a1-b709-4f2c-b7e8-e1484e0976b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903605076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3903605076
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.597926821
Short name T824
Test name
Test status
Simulation time 473196876 ps
CPU time 1.42 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:35 PM PDT 24
Peak memory 209680 kb
Host smart-61867cf1-f763-46de-a734-d3041dd739ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597926821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.597926821
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.58785468
Short name T894
Test name
Test status
Simulation time 4466638521 ps
CPU time 10.81 seconds
Started Aug 10 05:17:39 PM PDT 24
Finished Aug 10 05:17:50 PM PDT 24
Peak memory 201688 kb
Host smart-08b99614-2cfb-4c6c-8907-0b306f368de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58785468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_int
g_err.58785468
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.685944513
Short name T884
Test name
Test status
Simulation time 444699976 ps
CPU time 1.22 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201488 kb
Host smart-7486bed1-9bfd-4fe1-b1f0-8b0d9688be00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685944513 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.685944513
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4219142400
Short name T117
Test name
Test status
Simulation time 408032739 ps
CPU time 0.94 seconds
Started Aug 10 05:17:34 PM PDT 24
Finished Aug 10 05:17:35 PM PDT 24
Peak memory 201316 kb
Host smart-d16f6ac3-8a4d-4ece-a621-9854c05edf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219142400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4219142400
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.472090240
Short name T819
Test name
Test status
Simulation time 384490773 ps
CPU time 1.47 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201364 kb
Host smart-2255a888-681d-4e9e-bbca-274e80da98ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472090240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.472090240
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3739240806
Short name T48
Test name
Test status
Simulation time 2565543607 ps
CPU time 3.75 seconds
Started Aug 10 05:17:37 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201416 kb
Host smart-56dee659-344c-4964-8d4a-543132f5e58a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739240806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3739240806
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3690887675
Short name T63
Test name
Test status
Simulation time 648849195 ps
CPU time 2.3 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 210872 kb
Host smart-1b4059fc-b055-4203-b84b-40d6e14b4310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690887675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3690887675
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2948880607
Short name T865
Test name
Test status
Simulation time 519214504 ps
CPU time 1.4 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201524 kb
Host smart-0a6f0948-39ce-4c80-95c2-6aad76c916cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948880607 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2948880607
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1694945207
Short name T817
Test name
Test status
Simulation time 451699663 ps
CPU time 1.27 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201368 kb
Host smart-43d7fc6a-87d8-480a-bdb3-54f4288b3362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694945207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1694945207
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3665933455
Short name T841
Test name
Test status
Simulation time 362681662 ps
CPU time 0.83 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201364 kb
Host smart-83fbb8e6-8e5e-42a5-9df6-8d26b121e71d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665933455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3665933455
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.265606523
Short name T843
Test name
Test status
Simulation time 4720418730 ps
CPU time 10.41 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:52 PM PDT 24
Peak memory 201460 kb
Host smart-f74505af-a658-45ff-8bd5-90e3517eecea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265606523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.265606523
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2334278391
Short name T826
Test name
Test status
Simulation time 397829185 ps
CPU time 2.42 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 209696 kb
Host smart-279c82e5-9a13-44d2-9a2b-6a43734d1f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334278391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2334278391
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.107890082
Short name T53
Test name
Test status
Simulation time 4037010947 ps
CPU time 6.44 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201500 kb
Host smart-82026a4a-e540-4f64-8983-cd01f135e937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107890082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.107890082
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3957616191
Short name T872
Test name
Test status
Simulation time 354558328 ps
CPU time 1.05 seconds
Started Aug 10 05:17:32 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201404 kb
Host smart-ee5fd4b7-c9fb-484f-a787-88ab0378349a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957616191 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3957616191
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4242529264
Short name T866
Test name
Test status
Simulation time 435589419 ps
CPU time 1.21 seconds
Started Aug 10 05:17:37 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201380 kb
Host smart-0d1a8ecd-8e0a-472b-aa37-6ae2b4b49a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242529264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4242529264
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2770297565
Short name T891
Test name
Test status
Simulation time 298752610 ps
CPU time 0.84 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201240 kb
Host smart-72355b18-d32b-44d6-8572-b594dfc544f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770297565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2770297565
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.960242636
Short name T842
Test name
Test status
Simulation time 4655816845 ps
CPU time 4.08 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201464 kb
Host smart-1a610414-6f35-4ad2-9c85-b3e7c10d6b9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960242636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.960242636
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3031962902
Short name T66
Test name
Test status
Simulation time 611430616 ps
CPU time 1.9 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201596 kb
Host smart-4399558a-e570-4d00-a0d9-abaf112744d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031962902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3031962902
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.605688246
Short name T879
Test name
Test status
Simulation time 4737747376 ps
CPU time 6.91 seconds
Started Aug 10 05:17:42 PM PDT 24
Finished Aug 10 05:17:49 PM PDT 24
Peak memory 201652 kb
Host smart-513c5c3f-4ad7-4181-8146-86b7290cc16f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605688246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.605688246
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.279311466
Short name T867
Test name
Test status
Simulation time 554802209 ps
CPU time 2.13 seconds
Started Aug 10 05:17:44 PM PDT 24
Finished Aug 10 05:17:46 PM PDT 24
Peak memory 201516 kb
Host smart-2fcc19b8-7024-46ae-a8e7-c9edfac335af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279311466 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.279311466
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2968332796
Short name T907
Test name
Test status
Simulation time 511937228 ps
CPU time 1.33 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201192 kb
Host smart-2f50f671-058e-4e4c-b5c1-06dfa65be0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968332796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2968332796
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1340766274
Short name T887
Test name
Test status
Simulation time 480865750 ps
CPU time 1.61 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201372 kb
Host smart-f1717aab-0aa3-41e2-b07d-ecd32856c5d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340766274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1340766274
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3757896970
Short name T809
Test name
Test status
Simulation time 4773781809 ps
CPU time 5.74 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201516 kb
Host smart-5d381acb-f2a3-463a-bf09-d66209678538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757896970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3757896970
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3468196868
Short name T829
Test name
Test status
Simulation time 537228228 ps
CPU time 2.67 seconds
Started Aug 10 05:17:39 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201532 kb
Host smart-f9207626-a39b-4ead-ac25-411a5b54c054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468196868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3468196868
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1353588433
Short name T832
Test name
Test status
Simulation time 4975969130 ps
CPU time 4.58 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201708 kb
Host smart-2e37ea51-d631-4fc3-b3d3-48ab257a679d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353588433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1353588433
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2261129965
Short name T825
Test name
Test status
Simulation time 471781654 ps
CPU time 1.94 seconds
Started Aug 10 05:17:32 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201388 kb
Host smart-fc543262-c466-4291-bc43-af300bf6614a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261129965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2261129965
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.278465812
Short name T875
Test name
Test status
Simulation time 444852014 ps
CPU time 1.17 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201320 kb
Host smart-fbc1b765-545d-47ba-9668-09d6b74ef2f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278465812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.278465812
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.405669090
Short name T880
Test name
Test status
Simulation time 340148575 ps
CPU time 1.04 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201176 kb
Host smart-4972c647-b85b-4f27-82ad-caa6d75c792f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405669090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.405669090
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3297925665
Short name T897
Test name
Test status
Simulation time 2562368016 ps
CPU time 8.08 seconds
Started Aug 10 05:17:37 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201428 kb
Host smart-356e4a84-97c0-4c65-9ed6-f1da9c37b45f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297925665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3297925665
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1395592096
Short name T902
Test name
Test status
Simulation time 549263341 ps
CPU time 3.28 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201680 kb
Host smart-e23b5019-4f8a-48c4-88b1-75942d6835b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395592096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1395592096
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1163271861
Short name T883
Test name
Test status
Simulation time 8122258662 ps
CPU time 7 seconds
Started Aug 10 05:17:41 PM PDT 24
Finished Aug 10 05:17:48 PM PDT 24
Peak memory 201664 kb
Host smart-70af0286-d5f5-4d49-8401-c6a61587bafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163271861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1163271861
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2969637902
Short name T850
Test name
Test status
Simulation time 809679971 ps
CPU time 1.12 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201360 kb
Host smart-be3b77e7-c5f7-4596-b96c-516d23d00501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969637902 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2969637902
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.608617914
Short name T901
Test name
Test status
Simulation time 455900710 ps
CPU time 1.87 seconds
Started Aug 10 05:17:36 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201192 kb
Host smart-ebe48347-5be8-421d-9ee2-a61bbfff533f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608617914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.608617914
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.379929400
Short name T846
Test name
Test status
Simulation time 499636742 ps
CPU time 1.93 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201320 kb
Host smart-bfdf98a7-9a49-4355-8dc7-5085cac66908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379929400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.379929400
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1872686392
Short name T870
Test name
Test status
Simulation time 4369848345 ps
CPU time 5.36 seconds
Started Aug 10 05:17:32 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201636 kb
Host smart-c2babcd2-f614-4e07-ab16-4e68a792c0be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872686392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1872686392
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2755130022
Short name T61
Test name
Test status
Simulation time 737969776 ps
CPU time 1.47 seconds
Started Aug 10 05:17:44 PM PDT 24
Finished Aug 10 05:17:46 PM PDT 24
Peak memory 201512 kb
Host smart-cb2fec43-8bac-4ab6-8b04-069f9bfd6c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755130022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2755130022
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1155442699
Short name T838
Test name
Test status
Simulation time 475760267 ps
CPU time 1.35 seconds
Started Aug 10 05:17:41 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201520 kb
Host smart-75a7cd4c-07c7-4d42-96bc-3104a90ed8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155442699 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1155442699
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.61303927
Short name T851
Test name
Test status
Simulation time 357750278 ps
CPU time 1.01 seconds
Started Aug 10 05:17:49 PM PDT 24
Finished Aug 10 05:17:50 PM PDT 24
Peak memory 201336 kb
Host smart-4f9ace2b-20e2-4f3e-ab7b-ea5027696763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61303927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.61303927
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1751108172
Short name T804
Test name
Test status
Simulation time 305079129 ps
CPU time 0.96 seconds
Started Aug 10 05:17:51 PM PDT 24
Finished Aug 10 05:17:52 PM PDT 24
Peak memory 201244 kb
Host smart-59b73c2c-04bc-4dde-bcf2-f008d865e8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751108172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1751108172
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1496598386
Short name T130
Test name
Test status
Simulation time 2621291783 ps
CPU time 4.56 seconds
Started Aug 10 05:17:41 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201428 kb
Host smart-0f1ca18a-00a0-4c57-b7d4-f542e21adff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496598386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1496598386
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3242406161
Short name T831
Test name
Test status
Simulation time 618362334 ps
CPU time 2.39 seconds
Started Aug 10 05:17:34 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 209616 kb
Host smart-fb45fd70-1929-437a-a77b-8fbb90785459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242406161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3242406161
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.689659717
Short name T910
Test name
Test status
Simulation time 7950579714 ps
CPU time 20.2 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:18:00 PM PDT 24
Peak memory 201684 kb
Host smart-f6815141-f33a-4410-86cd-230629d527b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689659717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.689659717
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1435660394
Short name T120
Test name
Test status
Simulation time 893445523 ps
CPU time 2.46 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201544 kb
Host smart-9d64c0aa-edde-4d14-a486-5878d91e5a45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435660394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1435660394
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2729826164
Short name T123
Test name
Test status
Simulation time 47795331694 ps
CPU time 32.78 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:18:03 PM PDT 24
Peak memory 201528 kb
Host smart-4f2a7ca8-ccc5-4bb8-9e97-1e050e2f93ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729826164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2729826164
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3511393579
Short name T840
Test name
Test status
Simulation time 876619149 ps
CPU time 2.11 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201360 kb
Host smart-2a8ef100-122d-4ee2-be59-d36cf4d0f93f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511393579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3511393579
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1331227578
Short name T893
Test name
Test status
Simulation time 488217686 ps
CPU time 2.02 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201404 kb
Host smart-f91f5358-e25e-4922-9774-d2e9ea2919e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331227578 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1331227578
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1818905573
Short name T856
Test name
Test status
Simulation time 552562395 ps
CPU time 1.81 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:15 PM PDT 24
Peak memory 201332 kb
Host smart-b41b0d95-2a35-4d09-947f-cadfb5003e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818905573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1818905573
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1476048197
Short name T802
Test name
Test status
Simulation time 458581258 ps
CPU time 1.15 seconds
Started Aug 10 05:17:13 PM PDT 24
Finished Aug 10 05:17:14 PM PDT 24
Peak memory 201364 kb
Host smart-aef297b9-7ede-4ccd-a301-b9e25a32cb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476048197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1476048197
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2346916593
Short name T888
Test name
Test status
Simulation time 2016740158 ps
CPU time 6.92 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201368 kb
Host smart-94a07d42-3ef0-40aa-ab19-df61135b16dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346916593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2346916593
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1285959809
Short name T64
Test name
Test status
Simulation time 659173440 ps
CPU time 1.77 seconds
Started Aug 10 05:17:14 PM PDT 24
Finished Aug 10 05:17:16 PM PDT 24
Peak memory 201648 kb
Host smart-4d3df5d8-12fa-4392-9379-f9ce8ba1792b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285959809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1285959809
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1281339985
Short name T71
Test name
Test status
Simulation time 8861734708 ps
CPU time 4.98 seconds
Started Aug 10 05:17:21 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 201712 kb
Host smart-a779560a-0d05-4950-8dad-b4b100475874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281339985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1281339985
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2997645112
Short name T827
Test name
Test status
Simulation time 558737232 ps
CPU time 0.8 seconds
Started Aug 10 05:17:42 PM PDT 24
Finished Aug 10 05:17:43 PM PDT 24
Peak memory 201216 kb
Host smart-bc794738-d91b-4585-8561-513c179850fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997645112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2997645112
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.98813137
Short name T845
Test name
Test status
Simulation time 299905632 ps
CPU time 1.07 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201216 kb
Host smart-fe63d3a4-b071-4157-8b48-c2dcc4699c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98813137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.98813137
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.289182696
Short name T890
Test name
Test status
Simulation time 525523615 ps
CPU time 1.64 seconds
Started Aug 10 05:17:42 PM PDT 24
Finished Aug 10 05:17:44 PM PDT 24
Peak memory 201216 kb
Host smart-e8fee1f1-0afc-4060-9e6b-38452f28a615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289182696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.289182696
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2474350513
Short name T814
Test name
Test status
Simulation time 530044085 ps
CPU time 0.85 seconds
Started Aug 10 05:17:39 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201256 kb
Host smart-d68520ea-8ffa-4d9f-814f-825b53b4c0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474350513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2474350513
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4182968576
Short name T813
Test name
Test status
Simulation time 491489696 ps
CPU time 1.19 seconds
Started Aug 10 05:17:45 PM PDT 24
Finished Aug 10 05:17:46 PM PDT 24
Peak memory 201384 kb
Host smart-d92bc808-417b-4d91-9031-e10d983818e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182968576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4182968576
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1373995412
Short name T896
Test name
Test status
Simulation time 387561708 ps
CPU time 1.36 seconds
Started Aug 10 05:17:42 PM PDT 24
Finished Aug 10 05:17:43 PM PDT 24
Peak memory 201336 kb
Host smart-8ed775a6-315b-4874-83d3-bb4f9efd8076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373995412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1373995412
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2429766384
Short name T798
Test name
Test status
Simulation time 374394073 ps
CPU time 0.87 seconds
Started Aug 10 05:17:49 PM PDT 24
Finished Aug 10 05:17:50 PM PDT 24
Peak memory 201280 kb
Host smart-1a1f4823-649d-45c0-a652-772853566491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429766384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2429766384
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.847054999
Short name T801
Test name
Test status
Simulation time 358856741 ps
CPU time 1.41 seconds
Started Aug 10 05:17:44 PM PDT 24
Finished Aug 10 05:17:46 PM PDT 24
Peak memory 201532 kb
Host smart-b2d45221-c03c-4a4f-bc1e-3401e232e3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847054999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.847054999
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.849427618
Short name T816
Test name
Test status
Simulation time 376520222 ps
CPU time 1.52 seconds
Started Aug 10 05:17:43 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201204 kb
Host smart-487e88f1-f03b-4ce4-a3f7-21788667419e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849427618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.849427618
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.206132711
Short name T799
Test name
Test status
Simulation time 486378224 ps
CPU time 0.92 seconds
Started Aug 10 05:17:48 PM PDT 24
Finished Aug 10 05:17:49 PM PDT 24
Peak memory 201176 kb
Host smart-29c045a0-629b-4ddd-951b-3ebd9b8f7c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206132711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.206132711
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2298415842
Short name T115
Test name
Test status
Simulation time 1040609518 ps
CPU time 4.69 seconds
Started Aug 10 05:17:24 PM PDT 24
Finished Aug 10 05:17:29 PM PDT 24
Peak memory 201524 kb
Host smart-9b08ca61-2544-4de8-8713-a52413c651f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298415842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2298415842
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.750477340
Short name T124
Test name
Test status
Simulation time 13767000052 ps
CPU time 46.98 seconds
Started Aug 10 05:17:21 PM PDT 24
Finished Aug 10 05:18:09 PM PDT 24
Peak memory 201612 kb
Host smart-25136286-2a4a-46af-9cc0-d41d5d4b3fef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750477340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.750477340
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4083456035
Short name T853
Test name
Test status
Simulation time 758102255 ps
CPU time 1.96 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201396 kb
Host smart-56bfa7fd-3471-4bd5-92ad-0782adde8fab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083456035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4083456035
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3890859159
Short name T69
Test name
Test status
Simulation time 326699077 ps
CPU time 1.6 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201408 kb
Host smart-0403abc4-aee7-492b-b454-2d052b37fb81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890859159 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3890859159
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3672378620
Short name T913
Test name
Test status
Simulation time 367596533 ps
CPU time 0.96 seconds
Started Aug 10 05:17:24 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201252 kb
Host smart-7da25861-1d1c-4fef-a351-8241c93867b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672378620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3672378620
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3391109511
Short name T903
Test name
Test status
Simulation time 499347073 ps
CPU time 0.9 seconds
Started Aug 10 05:17:25 PM PDT 24
Finished Aug 10 05:17:27 PM PDT 24
Peak memory 201200 kb
Host smart-e2e3ab19-7fb8-40f6-96ca-b4ea1d699c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391109511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3391109511
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2481536001
Short name T129
Test name
Test status
Simulation time 2466676312 ps
CPU time 7.44 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:38 PM PDT 24
Peak memory 201456 kb
Host smart-4f4cde54-4b22-4334-ab7b-d2e70f4a53b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481536001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2481536001
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.129949486
Short name T828
Test name
Test status
Simulation time 605101612 ps
CPU time 1.68 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201552 kb
Host smart-26b90318-141f-493a-96d8-af4647ea4bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129949486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.129949486
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4284528839
Short name T72
Test name
Test status
Simulation time 4460677019 ps
CPU time 6.68 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201676 kb
Host smart-ae515bb8-2b68-4851-9f93-17e447fb3328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284528839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4284528839
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.400020815
Short name T849
Test name
Test status
Simulation time 329009037 ps
CPU time 0.83 seconds
Started Aug 10 05:17:39 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201204 kb
Host smart-6743be0d-fcb8-4b29-9c2e-8b4515ce4cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400020815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.400020815
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1792670567
Short name T839
Test name
Test status
Simulation time 308057849 ps
CPU time 1.02 seconds
Started Aug 10 05:17:41 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201356 kb
Host smart-b1a62f6c-8b0d-4c92-b187-a4dfdb31f9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792670567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1792670567
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2118308037
Short name T797
Test name
Test status
Simulation time 358220668 ps
CPU time 0.88 seconds
Started Aug 10 05:17:56 PM PDT 24
Finished Aug 10 05:17:57 PM PDT 24
Peak memory 201232 kb
Host smart-ed84f383-4b33-41d7-9755-49425148e41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118308037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2118308037
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.262979942
Short name T800
Test name
Test status
Simulation time 402981220 ps
CPU time 0.72 seconds
Started Aug 10 05:17:41 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201272 kb
Host smart-fcf7bfc2-4847-4023-85e2-82b782042e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262979942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.262979942
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.500681272
Short name T862
Test name
Test status
Simulation time 380994465 ps
CPU time 1.52 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201384 kb
Host smart-dd916c65-6289-4ece-97c6-f75f70a2e3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500681272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.500681272
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1004486577
Short name T877
Test name
Test status
Simulation time 535760959 ps
CPU time 1.26 seconds
Started Aug 10 05:17:54 PM PDT 24
Finished Aug 10 05:17:55 PM PDT 24
Peak memory 201176 kb
Host smart-68687331-c5a1-4ab3-ae1e-d9f7f20bc2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004486577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1004486577
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.900820460
Short name T815
Test name
Test status
Simulation time 491535603 ps
CPU time 1.62 seconds
Started Aug 10 05:17:43 PM PDT 24
Finished Aug 10 05:17:44 PM PDT 24
Peak memory 201120 kb
Host smart-962bdf45-3287-4d2b-b460-a5dd45e85cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900820460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.900820460
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1694387710
Short name T833
Test name
Test status
Simulation time 486641521 ps
CPU time 1.72 seconds
Started Aug 10 05:17:43 PM PDT 24
Finished Aug 10 05:17:44 PM PDT 24
Peak memory 201328 kb
Host smart-fa6afa2d-0f1e-4ce5-a196-58c56990d4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694387710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1694387710
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2078690735
Short name T905
Test name
Test status
Simulation time 389390884 ps
CPU time 0.86 seconds
Started Aug 10 05:17:50 PM PDT 24
Finished Aug 10 05:17:51 PM PDT 24
Peak memory 201208 kb
Host smart-d45aa9b3-2f69-47c9-91e6-d3f57851996b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078690735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2078690735
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1608444848
Short name T806
Test name
Test status
Simulation time 524655484 ps
CPU time 1.77 seconds
Started Aug 10 05:17:42 PM PDT 24
Finished Aug 10 05:17:44 PM PDT 24
Peak memory 201436 kb
Host smart-95ad7db2-08fd-4925-9359-bf75092bf827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608444848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1608444848
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1408179701
Short name T861
Test name
Test status
Simulation time 1266497893 ps
CPU time 2.83 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 201500 kb
Host smart-d1155086-152f-411d-b4b8-ab86efa80431
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408179701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1408179701
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2156561359
Short name T807
Test name
Test status
Simulation time 1138063183 ps
CPU time 3.42 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 201244 kb
Host smart-4723fc7f-dcbf-4d31-89fb-17eb1ad25a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156561359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2156561359
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3332241492
Short name T914
Test name
Test status
Simulation time 495459735 ps
CPU time 2.07 seconds
Started Aug 10 05:17:24 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 201416 kb
Host smart-5296f172-7fbf-415a-9672-d90942f39d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332241492 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3332241492
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.12049382
Short name T916
Test name
Test status
Simulation time 472135238 ps
CPU time 0.99 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201220 kb
Host smart-4d1bc767-a3cd-4cee-8644-c0ffeb0e7928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12049382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.12049382
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.943976294
Short name T805
Test name
Test status
Simulation time 479598593 ps
CPU time 0.88 seconds
Started Aug 10 05:17:22 PM PDT 24
Finished Aug 10 05:17:23 PM PDT 24
Peak memory 201216 kb
Host smart-78d4c804-64f7-4540-bdf3-1ac5c3a51acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943976294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.943976294
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3626706389
Short name T128
Test name
Test status
Simulation time 3833865650 ps
CPU time 2.63 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 201580 kb
Host smart-aa5aa143-c41e-4ee3-9233-41f559bb7a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626706389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3626706389
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4030384892
Short name T62
Test name
Test status
Simulation time 4376483557 ps
CPU time 4.13 seconds
Started Aug 10 05:17:29 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201656 kb
Host smart-ee13217c-ec0e-4f89-9286-204b349f2b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030384892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4030384892
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.867191256
Short name T834
Test name
Test status
Simulation time 393576465 ps
CPU time 0.88 seconds
Started Aug 10 05:17:44 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201352 kb
Host smart-782f25df-90a2-4462-a473-a698a9dfd4d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867191256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.867191256
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4095977248
Short name T859
Test name
Test status
Simulation time 479585941 ps
CPU time 1.59 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201336 kb
Host smart-446d0638-37d1-4304-818c-6753662cf7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095977248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4095977248
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2770783180
Short name T878
Test name
Test status
Simulation time 410018492 ps
CPU time 1.61 seconds
Started Aug 10 05:17:39 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201256 kb
Host smart-97e0e3dd-038b-4caa-83cc-153ba2736cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770783180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2770783180
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.739487714
Short name T820
Test name
Test status
Simulation time 389468980 ps
CPU time 0.8 seconds
Started Aug 10 05:17:44 PM PDT 24
Finished Aug 10 05:17:45 PM PDT 24
Peak memory 201368 kb
Host smart-94e20152-b967-4bba-a7ac-1ee6d74063c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739487714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.739487714
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1087925738
Short name T810
Test name
Test status
Simulation time 499959472 ps
CPU time 1.7 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201236 kb
Host smart-0572c9b9-d10e-426e-92d9-82ffd22446c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087925738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1087925738
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.791994534
Short name T847
Test name
Test status
Simulation time 475249973 ps
CPU time 1.77 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201236 kb
Host smart-e4c948ad-1858-4544-b369-05ea9d7559a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791994534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.791994534
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1220099585
Short name T871
Test name
Test status
Simulation time 346757410 ps
CPU time 1.47 seconds
Started Aug 10 05:17:38 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 201192 kb
Host smart-93e1b79b-c145-418b-a206-08d8f7cddf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220099585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1220099585
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3900511375
Short name T912
Test name
Test status
Simulation time 354020806 ps
CPU time 0.85 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201348 kb
Host smart-b24af393-54c8-44eb-b003-abd1b6bd1f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900511375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3900511375
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.572273014
Short name T818
Test name
Test status
Simulation time 480249100 ps
CPU time 0.83 seconds
Started Aug 10 05:17:55 PM PDT 24
Finished Aug 10 05:17:55 PM PDT 24
Peak memory 201268 kb
Host smart-e9b8f4d5-5cf8-482e-8f78-f1979a7d1fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572273014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.572273014
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2402685966
Short name T899
Test name
Test status
Simulation time 513990606 ps
CPU time 1.21 seconds
Started Aug 10 05:17:40 PM PDT 24
Finished Aug 10 05:17:41 PM PDT 24
Peak memory 201368 kb
Host smart-d19f32db-be01-48d5-b0fb-e96ac7a47eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402685966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2402685966
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2115406457
Short name T830
Test name
Test status
Simulation time 425017297 ps
CPU time 1.86 seconds
Started Aug 10 05:17:26 PM PDT 24
Finished Aug 10 05:17:28 PM PDT 24
Peak memory 201512 kb
Host smart-50327051-3c0d-4d21-a955-a4782c9a28f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115406457 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2115406457
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4118446569
Short name T860
Test name
Test status
Simulation time 447658366 ps
CPU time 1.78 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201220 kb
Host smart-1904fcda-0f19-4bee-a7be-928bc1742b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118446569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4118446569
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3313205809
Short name T895
Test name
Test status
Simulation time 366549337 ps
CPU time 1.05 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201236 kb
Host smart-884adc20-9bb5-405f-a61b-edca1bcfb75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313205809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3313205809
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.297567864
Short name T917
Test name
Test status
Simulation time 2685060441 ps
CPU time 2.51 seconds
Started Aug 10 05:17:26 PM PDT 24
Finished Aug 10 05:17:28 PM PDT 24
Peak memory 201328 kb
Host smart-103410dc-c6df-4249-b990-7387bbc088bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297567864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.297567864
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3384219141
Short name T65
Test name
Test status
Simulation time 455738718 ps
CPU time 2.55 seconds
Started Aug 10 05:17:27 PM PDT 24
Finished Aug 10 05:17:29 PM PDT 24
Peak memory 201560 kb
Host smart-a2901dda-c397-45b8-8d8f-06ec431ab47f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384219141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3384219141
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4137871540
Short name T70
Test name
Test status
Simulation time 4268422267 ps
CPU time 11.48 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:42 PM PDT 24
Peak memory 201596 kb
Host smart-1d9c8d47-7554-48fe-ad33-33f6a76f9fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137871540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4137871540
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1324416040
Short name T909
Test name
Test status
Simulation time 445388173 ps
CPU time 1.8 seconds
Started Aug 10 05:17:32 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201516 kb
Host smart-4ca231ea-abcc-4776-ad54-20dab271eae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324416040 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1324416040
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3466100352
Short name T852
Test name
Test status
Simulation time 348451324 ps
CPU time 1.12 seconds
Started Aug 10 05:17:24 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201232 kb
Host smart-7083de1f-daad-47a0-850b-ead7013fe34a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466100352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3466100352
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3632755913
Short name T886
Test name
Test status
Simulation time 428771226 ps
CPU time 1.54 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201376 kb
Host smart-8bfdd758-f7de-48de-9b46-2506f6985856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632755913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3632755913
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4263135572
Short name T844
Test name
Test status
Simulation time 2440900238 ps
CPU time 7.77 seconds
Started Aug 10 05:17:35 PM PDT 24
Finished Aug 10 05:17:43 PM PDT 24
Peak memory 201404 kb
Host smart-79a59a32-2b79-49ba-8a5a-aa002bdb3a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263135572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4263135572
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1993035955
Short name T836
Test name
Test status
Simulation time 403755788 ps
CPU time 2.43 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201512 kb
Host smart-7319fe05-b580-43f7-b160-da70b52731b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993035955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1993035955
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.626212047
Short name T835
Test name
Test status
Simulation time 4453459605 ps
CPU time 4.32 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:28 PM PDT 24
Peak memory 201564 kb
Host smart-9d67f42a-9ccf-43f2-8a82-0e327dba24d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626212047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.626212047
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134682788
Short name T823
Test name
Test status
Simulation time 575045259 ps
CPU time 1.11 seconds
Started Aug 10 05:17:22 PM PDT 24
Finished Aug 10 05:17:23 PM PDT 24
Peak memory 201408 kb
Host smart-f00038a5-c5b2-4094-be49-70930d506837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134682788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1134682788
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4021678922
Short name T122
Test name
Test status
Simulation time 505315538 ps
CPU time 1.28 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:24 PM PDT 24
Peak memory 201248 kb
Host smart-cd1c082b-c6d4-4a89-a4fc-2916887b91ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021678922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4021678922
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2406275062
Short name T803
Test name
Test status
Simulation time 441625977 ps
CPU time 1.62 seconds
Started Aug 10 05:17:20 PM PDT 24
Finished Aug 10 05:17:22 PM PDT 24
Peak memory 201300 kb
Host smart-ecb31c45-9e70-447d-b67a-87a0d4e16807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406275062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2406275062
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2272098183
Short name T876
Test name
Test status
Simulation time 3255692248 ps
CPU time 2.54 seconds
Started Aug 10 05:17:30 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201616 kb
Host smart-032f9130-38cc-4a4c-8950-c6ce09da27d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272098183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2272098183
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3693708157
Short name T68
Test name
Test status
Simulation time 528159667 ps
CPU time 3.45 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 201516 kb
Host smart-101b5b9c-4fbd-4f8e-99a3-7cf42f6738d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693708157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3693708157
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4092879292
Short name T837
Test name
Test status
Simulation time 4221397330 ps
CPU time 4.24 seconds
Started Aug 10 05:17:27 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 201440 kb
Host smart-0d677f3c-3672-4d1c-868e-ca05e572ea6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092879292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4092879292
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1567544530
Short name T60
Test name
Test status
Simulation time 455489016 ps
CPU time 1.24 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:25 PM PDT 24
Peak memory 201344 kb
Host smart-68379a8b-7cad-4138-92bf-457ae5a6c6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567544530 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1567544530
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1043399565
Short name T869
Test name
Test status
Simulation time 387833861 ps
CPU time 1.09 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201340 kb
Host smart-f3852762-8355-44da-918d-3db84c6ce3fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043399565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1043399565
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.702347898
Short name T822
Test name
Test status
Simulation time 393669115 ps
CPU time 0.72 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:32 PM PDT 24
Peak memory 201360 kb
Host smart-5fa81328-3753-4eb2-b0a1-36dfb7b4d2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702347898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.702347898
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1652206915
Short name T868
Test name
Test status
Simulation time 3337020043 ps
CPU time 2.79 seconds
Started Aug 10 05:17:34 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 201612 kb
Host smart-2e34fe48-c917-47a4-9009-aef233f28ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652206915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1652206915
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2535885525
Short name T863
Test name
Test status
Simulation time 871242602 ps
CPU time 3.03 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201584 kb
Host smart-15c5aa62-0417-444a-92f8-4a08e7a81fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535885525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2535885525
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2558665315
Short name T882
Test name
Test status
Simulation time 8948098439 ps
CPU time 3.6 seconds
Started Aug 10 05:17:23 PM PDT 24
Finished Aug 10 05:17:27 PM PDT 24
Peak memory 201544 kb
Host smart-04374bd5-83b7-4ddf-a189-812d660e653a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558665315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2558665315
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2219628526
Short name T892
Test name
Test status
Simulation time 452498617 ps
CPU time 1.95 seconds
Started Aug 10 05:17:31 PM PDT 24
Finished Aug 10 05:17:33 PM PDT 24
Peak memory 201536 kb
Host smart-d3ee3911-1b16-4247-a857-d731eb69cfc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219628526 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2219628526
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4066230800
Short name T116
Test name
Test status
Simulation time 340579427 ps
CPU time 1.51 seconds
Started Aug 10 05:17:21 PM PDT 24
Finished Aug 10 05:17:23 PM PDT 24
Peak memory 201356 kb
Host smart-a36ac729-6167-4541-a49f-85cdc2f6b69e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066230800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4066230800
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1326950672
Short name T864
Test name
Test status
Simulation time 299586863 ps
CPU time 1.04 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 201356 kb
Host smart-27e7196d-c242-4898-8430-a98d4c9d29fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326950672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1326950672
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1841508168
Short name T919
Test name
Test status
Simulation time 4470251941 ps
CPU time 8.02 seconds
Started Aug 10 05:17:22 PM PDT 24
Finished Aug 10 05:17:30 PM PDT 24
Peak memory 201460 kb
Host smart-08252eee-7b35-4c8f-acd0-f95de30bec91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841508168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1841508168
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1194551535
Short name T898
Test name
Test status
Simulation time 583789486 ps
CPU time 2.54 seconds
Started Aug 10 05:17:33 PM PDT 24
Finished Aug 10 05:17:35 PM PDT 24
Peak memory 201588 kb
Host smart-15de8da5-81b3-4563-8351-90fdd031b5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194551535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1194551535
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4019194723
Short name T918
Test name
Test status
Simulation time 3953030269 ps
CPU time 10.61 seconds
Started Aug 10 05:17:25 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 201640 kb
Host smart-d9f2faee-0afa-4f38-8526-8174867b9233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019194723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4019194723
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2113557059
Short name T497
Test name
Test status
Simulation time 480173030 ps
CPU time 1.66 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 201232 kb
Host smart-3c166582-5708-4dd9-a870-16b54a379938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113557059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2113557059
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4221608130
Short name T303
Test name
Test status
Simulation time 332184631981 ps
CPU time 342.39 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 06:04:39 PM PDT 24
Peak memory 201420 kb
Host smart-cb9af6be-9177-45fb-896e-a6822b7ae4c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221608130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4221608130
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4040954310
Short name T257
Test name
Test status
Simulation time 333080235150 ps
CPU time 162.42 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 06:01:31 PM PDT 24
Peak memory 201444 kb
Host smart-a828fc4a-827e-4794-829e-861375e8ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040954310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4040954310
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.397570991
Short name T242
Test name
Test status
Simulation time 501739101173 ps
CPU time 1168.7 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 201448 kb
Host smart-5fc58ca5-86a0-4c48-956f-14fc26567bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397570991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.397570991
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4153428660
Short name T379
Test name
Test status
Simulation time 170071862178 ps
CPU time 385.77 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:05:28 PM PDT 24
Peak memory 201484 kb
Host smart-580420e3-4474-4851-a012-5cf3bbac6de8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153428660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4153428660
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3935254196
Short name T76
Test name
Test status
Simulation time 166544667433 ps
CPU time 181.18 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 06:01:51 PM PDT 24
Peak memory 201412 kb
Host smart-b80b4314-15ef-4cea-80ef-ec01038aa4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935254196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3935254196
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4097492905
Short name T511
Test name
Test status
Simulation time 497583395066 ps
CPU time 261.7 seconds
Started Aug 10 05:59:09 PM PDT 24
Finished Aug 10 06:03:31 PM PDT 24
Peak memory 201452 kb
Host smart-f209b724-6211-4b5b-b01c-523111004baf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097492905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4097492905
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1611092114
Short name T331
Test name
Test status
Simulation time 173688425036 ps
CPU time 105.53 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 06:00:33 PM PDT 24
Peak memory 201436 kb
Host smart-a30057dc-fa42-4966-9f2e-0ec49326207b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611092114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1611092114
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.64949764
Short name T494
Test name
Test status
Simulation time 601825629792 ps
CPU time 103.52 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 06:00:33 PM PDT 24
Peak memory 201428 kb
Host smart-6246c8b1-3bf8-4423-a7f8-14c98209cdc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64949764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.64949764
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2315012280
Short name T592
Test name
Test status
Simulation time 77266024026 ps
CPU time 315.77 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 201824 kb
Host smart-9a8fdc1a-13ae-4353-9f5f-cece38aa07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315012280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2315012280
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3692388738
Short name T446
Test name
Test status
Simulation time 33452875404 ps
CPU time 20.56 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:59:15 PM PDT 24
Peak memory 201244 kb
Host smart-6de67618-2706-43e2-ab6e-1b1f681d3e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692388738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3692388738
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.56262344
Short name T415
Test name
Test status
Simulation time 4525157525 ps
CPU time 10.31 seconds
Started Aug 10 05:59:11 PM PDT 24
Finished Aug 10 05:59:21 PM PDT 24
Peak memory 201344 kb
Host smart-e5fe035d-1542-4b7d-9315-b1566691da96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56262344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.56262344
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3245031790
Short name T376
Test name
Test status
Simulation time 5669694933 ps
CPU time 7.75 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 201336 kb
Host smart-601e6426-3d08-4ed3-ae55-cb5a5d0d1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245031790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3245031790
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3849295000
Short name T661
Test name
Test status
Simulation time 358907864559 ps
CPU time 778.32 seconds
Started Aug 10 05:59:04 PM PDT 24
Finished Aug 10 06:12:02 PM PDT 24
Peak memory 201392 kb
Host smart-ac5eb066-40cd-45ac-8bce-177394c38d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849295000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3849295000
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2086581068
Short name T680
Test name
Test status
Simulation time 448557752 ps
CPU time 0.86 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 05:58:59 PM PDT 24
Peak memory 201244 kb
Host smart-ebb3ead2-2e92-4aba-852d-3a35de1a7e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086581068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2086581068
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.928798329
Short name T237
Test name
Test status
Simulation time 201467730590 ps
CPU time 114.22 seconds
Started Aug 10 05:59:29 PM PDT 24
Finished Aug 10 06:01:23 PM PDT 24
Peak memory 201404 kb
Host smart-d962eee1-717a-4ec6-b7f4-db1e5d691831
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928798329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.928798329
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2028514647
Short name T82
Test name
Test status
Simulation time 162383095804 ps
CPU time 102.55 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:00:46 PM PDT 24
Peak memory 201440 kb
Host smart-ae13528f-8227-4274-b32d-f044dc08cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028514647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2028514647
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.433187562
Short name T690
Test name
Test status
Simulation time 161016570712 ps
CPU time 356.2 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 06:04:45 PM PDT 24
Peak memory 201432 kb
Host smart-9d2e893c-5965-455f-a769-4e5b364d6384
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=433187562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.433187562
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2712608399
Short name T329
Test name
Test status
Simulation time 490317843378 ps
CPU time 1096.27 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 06:17:06 PM PDT 24
Peak memory 201464 kb
Host smart-c3307ca1-f84a-4f6b-b367-894c2ffd9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712608399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2712608399
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2505630474
Short name T360
Test name
Test status
Simulation time 165369802257 ps
CPU time 99.05 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 06:00:33 PM PDT 24
Peak memory 201480 kb
Host smart-146e880b-ff06-4c58-8c1e-5a73778daa0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505630474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2505630474
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1181311685
Short name T299
Test name
Test status
Simulation time 178992806712 ps
CPU time 416.33 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 06:05:53 PM PDT 24
Peak memory 201424 kb
Host smart-c7cf34b4-55cf-4ea1-815e-8fb344cf7398
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181311685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1181311685
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4269995907
Short name T166
Test name
Test status
Simulation time 393969936445 ps
CPU time 135.09 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:01:18 PM PDT 24
Peak memory 201472 kb
Host smart-24f5c79a-bda9-4b58-b7f6-cc7ba374cb66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269995907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4269995907
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4127154731
Short name T427
Test name
Test status
Simulation time 39646314711 ps
CPU time 26.82 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:59:22 PM PDT 24
Peak memory 201340 kb
Host smart-dd3b5b6c-06d7-4d9e-aeeb-4de5fd663b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127154731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4127154731
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3452107559
Short name T473
Test name
Test status
Simulation time 3465008744 ps
CPU time 4.15 seconds
Started Aug 10 05:59:01 PM PDT 24
Finished Aug 10 05:59:06 PM PDT 24
Peak memory 201372 kb
Host smart-84fbad74-3c92-4117-a335-46def81978da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452107559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3452107559
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3033127536
Short name T58
Test name
Test status
Simulation time 7809823733 ps
CPU time 10.67 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 05:59:13 PM PDT 24
Peak memory 218240 kb
Host smart-35a1f70c-4e9a-4154-a7ea-487408e1bb02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033127536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3033127536
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1330531574
Short name T411
Test name
Test status
Simulation time 6088423569 ps
CPU time 14.95 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:59:09 PM PDT 24
Peak memory 201368 kb
Host smart-0b657193-e95c-414e-94e2-0a71a24500fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330531574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1330531574
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.795936795
Short name T30
Test name
Test status
Simulation time 362906984686 ps
CPU time 742.98 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:11:30 PM PDT 24
Peak memory 201500 kb
Host smart-e8cd428b-f26d-4dc1-8440-dd74d4b68d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795936795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.795936795
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.944546889
Short name T213
Test name
Test status
Simulation time 29614496046 ps
CPU time 62.29 seconds
Started Aug 10 05:58:59 PM PDT 24
Finished Aug 10 06:00:01 PM PDT 24
Peak memory 209760 kb
Host smart-c3d323cd-9237-461e-80c8-0e1dd700f45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944546889 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.944546889
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3249353038
Short name T238
Test name
Test status
Simulation time 169826845482 ps
CPU time 185.33 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:02:22 PM PDT 24
Peak memory 201456 kb
Host smart-5c24e52f-1d74-4239-99b4-94e9059194a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249353038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3249353038
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2252410639
Short name T619
Test name
Test status
Simulation time 163690874395 ps
CPU time 363 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:05:20 PM PDT 24
Peak memory 201344 kb
Host smart-99a45cb2-3405-4343-a90b-e5828bd40b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252410639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2252410639
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3639506973
Short name T450
Test name
Test status
Simulation time 328812954710 ps
CPU time 717.62 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:11:15 PM PDT 24
Peak memory 201476 kb
Host smart-65f956c4-7f71-4864-958f-93b45937d83c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639506973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3639506973
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2374831665
Short name T435
Test name
Test status
Simulation time 165238722233 ps
CPU time 187.88 seconds
Started Aug 10 05:59:26 PM PDT 24
Finished Aug 10 06:02:34 PM PDT 24
Peak memory 201312 kb
Host smart-2463fc68-2610-49bb-8404-a96ba310cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374831665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2374831665
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3474260360
Short name T624
Test name
Test status
Simulation time 489736181621 ps
CPU time 308.38 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:04:42 PM PDT 24
Peak memory 201292 kb
Host smart-c7795e59-01c9-4168-8877-f055ccd21c8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474260360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3474260360
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1048449174
Short name T654
Test name
Test status
Simulation time 588094282972 ps
CPU time 325.45 seconds
Started Aug 10 05:59:20 PM PDT 24
Finished Aug 10 06:04:46 PM PDT 24
Peak memory 201376 kb
Host smart-cfd3471c-77f2-433a-9b5c-185c944bd073
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048449174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1048449174
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4210649548
Short name T216
Test name
Test status
Simulation time 138239355555 ps
CPU time 479.9 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:07:21 PM PDT 24
Peak memory 201796 kb
Host smart-57742f87-9191-43a3-8f01-ca8d97f13888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210649548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4210649548
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1830455236
Short name T574
Test name
Test status
Simulation time 37123649138 ps
CPU time 45.25 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:00:20 PM PDT 24
Peak memory 201240 kb
Host smart-222704b1-896a-44a4-8cb4-6fa099ec8718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830455236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1830455236
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1148336375
Short name T616
Test name
Test status
Simulation time 4671116173 ps
CPU time 12.77 seconds
Started Aug 10 05:59:28 PM PDT 24
Finished Aug 10 05:59:41 PM PDT 24
Peak memory 201296 kb
Host smart-8698fd37-28e0-493a-a74f-a1f4712bc1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148336375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1148336375
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2372449468
Short name T565
Test name
Test status
Simulation time 5740711883 ps
CPU time 10.55 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 05:59:29 PM PDT 24
Peak memory 201380 kb
Host smart-621ed6a7-2c9f-47eb-a70a-d251f71e491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372449468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2372449468
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3836976260
Short name T214
Test name
Test status
Simulation time 251933281406 ps
CPU time 58.4 seconds
Started Aug 10 05:59:20 PM PDT 24
Finished Aug 10 06:00:18 PM PDT 24
Peak memory 210304 kb
Host smart-64448f52-ba5b-42ae-9fba-a4f55efdb42b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836976260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3836976260
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4177314743
Short name T517
Test name
Test status
Simulation time 387185291 ps
CPU time 1.61 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 05:59:22 PM PDT 24
Peak memory 201256 kb
Host smart-e884c7ee-249c-437c-a709-7918ea90d05b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177314743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4177314743
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.734084757
Short name T501
Test name
Test status
Simulation time 166871861994 ps
CPU time 99.73 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:01:10 PM PDT 24
Peak memory 201472 kb
Host smart-295176f1-99d5-45fe-b23c-3300812d2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734084757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.734084757
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.491785498
Short name T364
Test name
Test status
Simulation time 499598591926 ps
CPU time 416.9 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 06:06:20 PM PDT 24
Peak memory 201472 kb
Host smart-05cf33d5-4c1c-4338-8509-3868695fa918
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=491785498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.491785498
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3565684386
Short name T135
Test name
Test status
Simulation time 325317919661 ps
CPU time 165.31 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 06:02:08 PM PDT 24
Peak memory 201416 kb
Host smart-64ea6d69-156d-4ee4-bd10-ddf673444ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565684386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3565684386
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1701222934
Short name T470
Test name
Test status
Simulation time 496174533816 ps
CPU time 373.87 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:05:30 PM PDT 24
Peak memory 201464 kb
Host smart-d8384e70-76e0-4cbf-ac6c-ab75d4d57828
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701222934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1701222934
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3289998188
Short name T80
Test name
Test status
Simulation time 616033131112 ps
CPU time 1324.65 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:21:27 PM PDT 24
Peak memory 201480 kb
Host smart-07a4a1f9-9494-4b6b-9ba8-d2e3970c27fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289998188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3289998188
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1455123451
Short name T790
Test name
Test status
Simulation time 85477360595 ps
CPU time 462.38 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:07:22 PM PDT 24
Peak memory 201848 kb
Host smart-496fc8ad-53b0-4dfb-801e-d65b57bb88a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455123451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1455123451
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2961296923
Short name T792
Test name
Test status
Simulation time 32365153925 ps
CPU time 11.07 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 05:59:30 PM PDT 24
Peak memory 201356 kb
Host smart-a83868ff-ac48-48ef-915c-cac962b95680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961296923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2961296923
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4201943250
Short name T554
Test name
Test status
Simulation time 4949868018 ps
CPU time 13.55 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 05:59:31 PM PDT 24
Peak memory 201364 kb
Host smart-f36c597d-8481-49a7-a41c-f6cdfd774740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201943250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4201943250
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1201347149
Short name T703
Test name
Test status
Simulation time 5621168231 ps
CPU time 4.16 seconds
Started Aug 10 05:59:15 PM PDT 24
Finished Aug 10 05:59:20 PM PDT 24
Peak memory 201224 kb
Host smart-e0703ae0-6242-4ea1-9407-582f83dfbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201347149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1201347149
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.659681815
Short name T729
Test name
Test status
Simulation time 429124876993 ps
CPU time 1261.2 seconds
Started Aug 10 05:59:24 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 209976 kb
Host smart-4230c1ff-8ab4-4395-9800-7b4584273d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659681815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
659681815
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.811351181
Short name T559
Test name
Test status
Simulation time 569379614 ps
CPU time 0.89 seconds
Started Aug 10 05:59:40 PM PDT 24
Finished Aug 10 05:59:41 PM PDT 24
Peak memory 201148 kb
Host smart-c4ee9508-98fa-4dc9-8f49-406045c9215a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811351181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.811351181
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2204798396
Short name T585
Test name
Test status
Simulation time 329116507164 ps
CPU time 207.27 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 06:03:13 PM PDT 24
Peak memory 201460 kb
Host smart-aafe7374-0fb8-48ad-9a3f-9accf9f96821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204798396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2204798396
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3648948218
Short name T295
Test name
Test status
Simulation time 165829498749 ps
CPU time 103.62 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:01:14 PM PDT 24
Peak memory 201484 kb
Host smart-04a3e307-597f-42aa-af6d-6f9c12329347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648948218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3648948218
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.885507022
Short name T667
Test name
Test status
Simulation time 161650077731 ps
CPU time 182.79 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:02:33 PM PDT 24
Peak memory 201408 kb
Host smart-9a622cc1-d308-4f13-af39-2bbb852c93ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=885507022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.885507022
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.167733558
Short name T306
Test name
Test status
Simulation time 156996573356 ps
CPU time 359.24 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:05:31 PM PDT 24
Peak memory 201448 kb
Host smart-eb9a3ea1-33ae-417d-94f1-0657ad566101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167733558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.167733558
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2515304307
Short name T107
Test name
Test status
Simulation time 163261333148 ps
CPU time 191.91 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:02:43 PM PDT 24
Peak memory 201432 kb
Host smart-7170f910-646f-4cde-af46-0fd4ed97a210
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515304307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2515304307
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3141212133
Short name T151
Test name
Test status
Simulation time 380570811631 ps
CPU time 879.08 seconds
Started Aug 10 05:59:27 PM PDT 24
Finished Aug 10 06:14:06 PM PDT 24
Peak memory 201456 kb
Host smart-f5ca0f9b-31ce-4c4a-9602-6688e1c73248
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141212133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3141212133
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.952965978
Short name T515
Test name
Test status
Simulation time 73031778844 ps
CPU time 264.41 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:04:03 PM PDT 24
Peak memory 201784 kb
Host smart-3ceac55c-8359-41eb-832b-852119205d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952965978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.952965978
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4211124132
Short name T487
Test name
Test status
Simulation time 43959539141 ps
CPU time 103.58 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:01:16 PM PDT 24
Peak memory 201352 kb
Host smart-0b58db89-d2f6-4ac1-b353-c337ff79c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211124132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4211124132
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2150635607
Short name T540
Test name
Test status
Simulation time 4979201548 ps
CPU time 3.43 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 05:59:36 PM PDT 24
Peak memory 201240 kb
Host smart-5ed9054c-050f-4975-a686-9b542bb6a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150635607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2150635607
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2693335240
Short name T488
Test name
Test status
Simulation time 5616160813 ps
CPU time 4.03 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 05:59:22 PM PDT 24
Peak memory 201340 kb
Host smart-913a6faf-b568-4805-87a4-1dee59119377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693335240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2693335240
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2259348530
Short name T794
Test name
Test status
Simulation time 208117027961 ps
CPU time 731.57 seconds
Started Aug 10 05:59:26 PM PDT 24
Finished Aug 10 06:11:38 PM PDT 24
Peak memory 201900 kb
Host smart-bb7ef8db-ed5c-4479-8dbd-9204b013f945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259348530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2259348530
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1230379270
Short name T37
Test name
Test status
Simulation time 71256812283 ps
CPU time 34.02 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:00:13 PM PDT 24
Peak memory 201680 kb
Host smart-ab39c268-0d0a-439a-a63f-6f1df767421e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230379270 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1230379270
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2131062789
Short name T471
Test name
Test status
Simulation time 466101369 ps
CPU time 1.68 seconds
Started Aug 10 05:59:24 PM PDT 24
Finished Aug 10 05:59:26 PM PDT 24
Peak memory 201220 kb
Host smart-b0ef1c59-0ab3-40b4-b443-241f37c11c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131062789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2131062789
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.197906643
Short name T408
Test name
Test status
Simulation time 164975076668 ps
CPU time 390.58 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:06:02 PM PDT 24
Peak memory 201444 kb
Host smart-e14b8f9e-3c4f-44a2-8da9-5b29dc865ead
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197906643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.197906643
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3499993999
Short name T757
Test name
Test status
Simulation time 342919983059 ps
CPU time 849.86 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:13:40 PM PDT 24
Peak memory 201452 kb
Host smart-d3b7f726-2f0c-4b83-ae77-af2d149a580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499993999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3499993999
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3432011204
Short name T629
Test name
Test status
Simulation time 163393354205 ps
CPU time 197.57 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:02:56 PM PDT 24
Peak memory 201432 kb
Host smart-4e01be61-243f-4d4d-935d-9f52b64e0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432011204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3432011204
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.516768886
Short name T743
Test name
Test status
Simulation time 168520538498 ps
CPU time 91.3 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:00:53 PM PDT 24
Peak memory 201456 kb
Host smart-ec8bdc86-867b-4ae0-83ab-a2331c46cbd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=516768886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.516768886
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.392922249
Short name T152
Test name
Test status
Simulation time 321117271794 ps
CPU time 112.15 seconds
Started Aug 10 05:59:20 PM PDT 24
Finished Aug 10 06:01:12 PM PDT 24
Peak memory 201524 kb
Host smart-c6464c7d-5512-4515-a6d9-3c9b3920be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392922249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.392922249
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3595641374
Short name T525
Test name
Test status
Simulation time 499317272185 ps
CPU time 1171.25 seconds
Started Aug 10 05:59:29 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 201484 kb
Host smart-c612b725-59df-4e98-af82-bbc74560eee3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595641374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3595641374
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2228427231
Short name T77
Test name
Test status
Simulation time 372411460465 ps
CPU time 194.89 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:02:51 PM PDT 24
Peak memory 201504 kb
Host smart-df6e0f76-c06d-46ef-8c7a-ebd44d5d2b51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228427231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2228427231
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2055636261
Short name T109
Test name
Test status
Simulation time 210871795452 ps
CPU time 484.65 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:07:38 PM PDT 24
Peak memory 201428 kb
Host smart-5a1a8473-0b25-4e9b-887e-f69fec35e312
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055636261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2055636261
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1105642352
Short name T670
Test name
Test status
Simulation time 84752813078 ps
CPU time 299.98 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 06:04:42 PM PDT 24
Peak memory 201844 kb
Host smart-b997e6e4-e3d3-452b-bf70-894af217ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105642352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1105642352
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3825134138
Short name T416
Test name
Test status
Simulation time 40449996436 ps
CPU time 7.89 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 05:59:50 PM PDT 24
Peak memory 201296 kb
Host smart-11b3cead-c326-45aa-8661-2837040a82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825134138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3825134138
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2584391968
Short name T772
Test name
Test status
Simulation time 4163316360 ps
CPU time 10.13 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 05:59:49 PM PDT 24
Peak memory 201336 kb
Host smart-2ef24a3e-bf1a-43c6-b1c3-8070b06a1444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584391968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2584391968
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2739838157
Short name T401
Test name
Test status
Simulation time 5936097838 ps
CPU time 4.84 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 05:59:35 PM PDT 24
Peak memory 201356 kb
Host smart-f31d0240-127c-466a-a672-06a13860734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739838157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2739838157
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3226346755
Short name T459
Test name
Test status
Simulation time 163193619215 ps
CPU time 101.5 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:01:18 PM PDT 24
Peak memory 201432 kb
Host smart-a3e34894-7635-4185-bd47-1f33ce359532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226346755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3226346755
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1498623982
Short name T761
Test name
Test status
Simulation time 60855736355 ps
CPU time 108.1 seconds
Started Aug 10 05:59:28 PM PDT 24
Finished Aug 10 06:01:16 PM PDT 24
Peak memory 210232 kb
Host smart-cfee3032-5327-4c27-ab93-317d29a298a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498623982 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1498623982
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3353873360
Short name T106
Test name
Test status
Simulation time 471240177 ps
CPU time 1.67 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 05:59:34 PM PDT 24
Peak memory 201264 kb
Host smart-bad68382-52cc-48f0-85d1-24832fcc81b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353873360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3353873360
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.438653229
Short name T755
Test name
Test status
Simulation time 332330650132 ps
CPU time 409.26 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:06:23 PM PDT 24
Peak memory 201464 kb
Host smart-96ee6eff-5bf6-427b-9455-3ec99b10dda1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=438653229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.438653229
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2807863026
Short name T386
Test name
Test status
Simulation time 164323538224 ps
CPU time 330.57 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:05:09 PM PDT 24
Peak memory 201488 kb
Host smart-791fd435-0cc5-48c1-a906-9a54d18bc883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807863026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2807863026
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3514869040
Short name T98
Test name
Test status
Simulation time 323026721508 ps
CPU time 441.61 seconds
Started Aug 10 05:59:27 PM PDT 24
Finished Aug 10 06:06:49 PM PDT 24
Peak memory 201408 kb
Host smart-b0435d43-cab1-4dce-8be0-52ad0dc5d5b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514869040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3514869040
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4105945365
Short name T249
Test name
Test status
Simulation time 350346023063 ps
CPU time 820.95 seconds
Started Aug 10 05:59:28 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 201424 kb
Host smart-351cdfba-5abf-4240-a7d3-0ec082342503
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105945365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4105945365
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2340853947
Short name T94
Test name
Test status
Simulation time 402766560180 ps
CPU time 407.18 seconds
Started Aug 10 05:59:29 PM PDT 24
Finished Aug 10 06:06:16 PM PDT 24
Peak memory 201384 kb
Host smart-a1679844-401b-4b39-b82d-d0b35c87b6f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340853947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2340853947
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2266188813
Short name T712
Test name
Test status
Simulation time 84834785500 ps
CPU time 342.91 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:05:19 PM PDT 24
Peak memory 201848 kb
Host smart-7ae7e7fa-dcdd-4ca0-a636-182b8bf445e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266188813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2266188813
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4184430416
Short name T593
Test name
Test status
Simulation time 25807776451 ps
CPU time 59.14 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 06:00:41 PM PDT 24
Peak memory 201340 kb
Host smart-98dedd14-62f5-4d73-9207-33cb740eb16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184430416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4184430416
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2426842441
Short name T742
Test name
Test status
Simulation time 4005411265 ps
CPU time 4.98 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 05:59:37 PM PDT 24
Peak memory 201340 kb
Host smart-98f1a88b-fca7-458b-904b-42b105330651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426842441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2426842441
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.700446170
Short name T133
Test name
Test status
Simulation time 5807003403 ps
CPU time 4.33 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 05:59:42 PM PDT 24
Peak memory 201296 kb
Host smart-2a6978db-e5ba-4a8e-b8c0-c8040cec64c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700446170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.700446170
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3297818132
Short name T38
Test name
Test status
Simulation time 156994409293 ps
CPU time 134.88 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:01:47 PM PDT 24
Peak memory 210012 kb
Host smart-09bd133c-f8d2-4491-97bc-ce0f2e6247f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297818132 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3297818132
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1000892207
Short name T750
Test name
Test status
Simulation time 434084908 ps
CPU time 0.68 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 05:59:33 PM PDT 24
Peak memory 201240 kb
Host smart-bcefb638-93a8-4cdf-8fab-bc04841604b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000892207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1000892207
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2036257346
Short name T582
Test name
Test status
Simulation time 165711006708 ps
CPU time 205.5 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:02:59 PM PDT 24
Peak memory 201440 kb
Host smart-264ed627-be6a-4902-a446-90def0656ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036257346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2036257346
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3297955857
Short name T270
Test name
Test status
Simulation time 329984240275 ps
CPU time 211.29 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:03:10 PM PDT 24
Peak memory 201380 kb
Host smart-f40c8ecd-ab49-4b7a-a4ab-d79bd7812924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297955857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3297955857
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3023433398
Short name T632
Test name
Test status
Simulation time 327084422947 ps
CPU time 170.65 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:02:20 PM PDT 24
Peak memory 201376 kb
Host smart-86caa36e-5272-4bef-a6b0-277809c5e64f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023433398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3023433398
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2416065175
Short name T527
Test name
Test status
Simulation time 325106807180 ps
CPU time 364.35 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:05:38 PM PDT 24
Peak memory 201432 kb
Host smart-dc770e85-4d82-4422-99fc-459c93eedd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416065175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2416065175
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1876695709
Short name T600
Test name
Test status
Simulation time 494497938323 ps
CPU time 423.77 seconds
Started Aug 10 05:59:25 PM PDT 24
Finished Aug 10 06:06:29 PM PDT 24
Peak memory 201468 kb
Host smart-ccfdd669-f974-4a6a-90c9-165c3c88e62a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876695709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1876695709
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3842605375
Short name T590
Test name
Test status
Simulation time 612316506122 ps
CPU time 353.83 seconds
Started Aug 10 05:59:31 PM PDT 24
Finished Aug 10 06:05:25 PM PDT 24
Peak memory 201516 kb
Host smart-3868af7f-5e40-455e-9a34-89ad3f132c3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842605375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3842605375
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3738794395
Short name T441
Test name
Test status
Simulation time 613937540987 ps
CPU time 692.19 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 06:11:15 PM PDT 24
Peak memory 201432 kb
Host smart-f5305b70-6be6-4811-a6a2-cbf11d6da623
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738794395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3738794395
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3350882838
Short name T345
Test name
Test status
Simulation time 123118842979 ps
CPU time 524.9 seconds
Started Aug 10 05:59:37 PM PDT 24
Finished Aug 10 06:08:22 PM PDT 24
Peak memory 201828 kb
Host smart-64027689-acf8-40fb-9f09-c1ca4eb7055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350882838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3350882838
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.4004657699
Short name T780
Test name
Test status
Simulation time 25488524579 ps
CPU time 59.15 seconds
Started Aug 10 05:59:28 PM PDT 24
Finished Aug 10 06:00:27 PM PDT 24
Peak memory 201344 kb
Host smart-686540f0-992d-48bd-8102-68995429993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004657699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.4004657699
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4254919100
Short name T444
Test name
Test status
Simulation time 3812568776 ps
CPU time 9.37 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 05:59:43 PM PDT 24
Peak memory 201336 kb
Host smart-34908c33-ffc5-45d1-a3ac-5d9d029d00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254919100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4254919100
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3685105889
Short name T533
Test name
Test status
Simulation time 5839833310 ps
CPU time 15.21 seconds
Started Aug 10 05:59:37 PM PDT 24
Finished Aug 10 05:59:53 PM PDT 24
Peak memory 201340 kb
Host smart-6c9f7681-8acb-4915-8384-27394affd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685105889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3685105889
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3330713800
Short name T771
Test name
Test status
Simulation time 326188149269 ps
CPU time 733.66 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:11:49 PM PDT 24
Peak memory 201384 kb
Host smart-b2636e11-740a-4387-ab41-d0b3eecd103b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330713800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3330713800
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3893298305
Short name T34
Test name
Test status
Simulation time 99862444822 ps
CPU time 197.8 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:02:50 PM PDT 24
Peak memory 218328 kb
Host smart-6ad99baa-b69e-4c76-9c9c-7b770ae1f92f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893298305 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3893298305
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.974027883
Short name T439
Test name
Test status
Simulation time 352975236 ps
CPU time 1.35 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 05:59:37 PM PDT 24
Peak memory 201260 kb
Host smart-d1df8855-6823-4405-bdff-6df6043c3738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974027883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.974027883
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1585945879
Short name T319
Test name
Test status
Simulation time 370318778045 ps
CPU time 657.63 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:10:33 PM PDT 24
Peak memory 201416 kb
Host smart-6cc3ccad-7086-4970-a3f5-e5022fdbab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585945879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1585945879
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2209942094
Short name T665
Test name
Test status
Simulation time 332270032007 ps
CPU time 409.28 seconds
Started Aug 10 05:59:44 PM PDT 24
Finished Aug 10 06:06:34 PM PDT 24
Peak memory 201356 kb
Host smart-2644a897-30ad-445d-8008-1c9978030477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209942094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2209942094
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1809177568
Short name T529
Test name
Test status
Simulation time 491241921802 ps
CPU time 1117.81 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:18:17 PM PDT 24
Peak memory 201524 kb
Host smart-a9bc26c2-7dd8-4a25-8e82-4c1733657f21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809177568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1809177568
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1350760140
Short name T146
Test name
Test status
Simulation time 325712898087 ps
CPU time 738.57 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:11:51 PM PDT 24
Peak memory 201340 kb
Host smart-b61d3c88-df7e-43c8-9c00-dc3367b9bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350760140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1350760140
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1288142009
Short name T484
Test name
Test status
Simulation time 161572827227 ps
CPU time 340 seconds
Started Aug 10 05:59:39 PM PDT 24
Finished Aug 10 06:05:19 PM PDT 24
Peak memory 201424 kb
Host smart-55d55b30-edce-41a9-bd86-42354a450942
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288142009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1288142009
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.408525034
Short name T190
Test name
Test status
Simulation time 555386583262 ps
CPU time 285.6 seconds
Started Aug 10 05:59:47 PM PDT 24
Finished Aug 10 06:04:33 PM PDT 24
Peak memory 201448 kb
Host smart-f88613ff-2ea0-44fa-8826-ac734ed59b38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408525034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.408525034
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.796028277
Short name T531
Test name
Test status
Simulation time 193083924199 ps
CPU time 82.85 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:00:59 PM PDT 24
Peak memory 201272 kb
Host smart-8794be57-8a98-431d-82e3-8458ca86aeb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796028277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.796028277
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.288695867
Short name T217
Test name
Test status
Simulation time 141355208920 ps
CPU time 706.27 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:11:19 PM PDT 24
Peak memory 201864 kb
Host smart-5961e01b-2204-4637-8402-026e91080c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288695867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.288695867
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1264208187
Short name T418
Test name
Test status
Simulation time 32342809384 ps
CPU time 38.14 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:00:16 PM PDT 24
Peak memory 201380 kb
Host smart-212c485d-024a-466b-bb61-ca27b7ee8a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264208187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1264208187
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1346320792
Short name T782
Test name
Test status
Simulation time 5242155289 ps
CPU time 11.65 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 05:59:44 PM PDT 24
Peak memory 201364 kb
Host smart-0d613919-ab2c-45f5-a94d-62406ff3563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346320792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1346320792
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1192595451
Short name T578
Test name
Test status
Simulation time 5697683016 ps
CPU time 3.63 seconds
Started Aug 10 05:59:40 PM PDT 24
Finished Aug 10 05:59:44 PM PDT 24
Peak memory 201340 kb
Host smart-58ac7d5a-baa1-4eaa-b2cf-dcf50415fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192595451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1192595451
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1779620858
Short name T549
Test name
Test status
Simulation time 17369881982 ps
CPU time 29.3 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:00:17 PM PDT 24
Peak memory 201464 kb
Host smart-26b306fc-f927-42f9-aaf1-adc4a9e5dc54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779620858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1779620858
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.369020819
Short name T536
Test name
Test status
Simulation time 348376486 ps
CPU time 1.45 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 05:59:50 PM PDT 24
Peak memory 201220 kb
Host smart-48fb28bd-4f9d-411e-969d-5b914470305e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369020819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.369020819
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.516269327
Short name T775
Test name
Test status
Simulation time 166492346300 ps
CPU time 159.17 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 06:02:14 PM PDT 24
Peak memory 201420 kb
Host smart-42b641d7-4ad4-4881-ba24-6b551add4ac4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516269327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.516269327
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3471608029
Short name T635
Test name
Test status
Simulation time 174366168938 ps
CPU time 408.77 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:06:21 PM PDT 24
Peak memory 201300 kb
Host smart-d43b1447-53ea-44e0-af04-79437ac3bbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471608029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3471608029
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2386435801
Short name T181
Test name
Test status
Simulation time 330604983946 ps
CPU time 738.44 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:12:07 PM PDT 24
Peak memory 201432 kb
Host smart-36674aae-65fa-4f1b-a458-920655a6028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386435801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2386435801
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2100837007
Short name T659
Test name
Test status
Simulation time 325299920582 ps
CPU time 209.65 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:03:04 PM PDT 24
Peak memory 201520 kb
Host smart-aa2294c7-f4ea-49f3-a962-d58e147da6e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100837007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2100837007
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.89695321
Short name T153
Test name
Test status
Simulation time 328330096471 ps
CPU time 790.22 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:12:56 PM PDT 24
Peak memory 201416 kb
Host smart-8946cdd8-963a-42e2-b942-f4612e2852c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89695321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.89695321
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3359206261
Short name T766
Test name
Test status
Simulation time 497157257048 ps
CPU time 1089.93 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:17:47 PM PDT 24
Peak memory 201388 kb
Host smart-2ca0a221-8c78-4b5a-9234-650659bfd2cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359206261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3359206261
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1406631292
Short name T134
Test name
Test status
Simulation time 364093201713 ps
CPU time 816.45 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:13:13 PM PDT 24
Peak memory 201268 kb
Host smart-16f7730d-6ea4-4241-b686-03cdebd03330
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406631292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1406631292
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3621284859
Short name T507
Test name
Test status
Simulation time 410050533888 ps
CPU time 168.64 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 06:02:34 PM PDT 24
Peak memory 201440 kb
Host smart-0bffc2a5-bd12-4a2e-affc-78acec318632
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621284859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3621284859
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1743548664
Short name T95
Test name
Test status
Simulation time 96735149654 ps
CPU time 498.85 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:07:54 PM PDT 24
Peak memory 201836 kb
Host smart-cb662f50-cd79-4261-9b6f-19be8b64a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743548664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1743548664
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3737178848
Short name T696
Test name
Test status
Simulation time 26286243910 ps
CPU time 10.07 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 05:59:46 PM PDT 24
Peak memory 201348 kb
Host smart-9ec1edcb-0648-4953-9e8c-08fd8795ac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737178848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3737178848
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.136358982
Short name T434
Test name
Test status
Simulation time 3873564052 ps
CPU time 2.41 seconds
Started Aug 10 05:59:43 PM PDT 24
Finished Aug 10 05:59:45 PM PDT 24
Peak memory 201352 kb
Host smart-dca34e9f-7fd9-47ca-91e1-2d9a4e5fc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136358982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.136358982
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1610044054
Short name T498
Test name
Test status
Simulation time 5905035035 ps
CPU time 14.14 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 05:59:48 PM PDT 24
Peak memory 201456 kb
Host smart-d29df727-b5cf-4b07-9660-0f77456659fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610044054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1610044054
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3012077158
Short name T442
Test name
Test status
Simulation time 344255222345 ps
CPU time 401.36 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 06:06:15 PM PDT 24
Peak memory 201460 kb
Host smart-e9425466-97e4-4c9c-960a-45d5266514a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012077158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3012077158
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.108691533
Short name T482
Test name
Test status
Simulation time 384671820630 ps
CPU time 307.05 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 06:04:42 PM PDT 24
Peak memory 209948 kb
Host smart-251fa096-5ccb-4c7b-ac19-2b418ffde920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108691533 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.108691533
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1589793335
Short name T774
Test name
Test status
Simulation time 500759451 ps
CPU time 1.64 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 05:59:37 PM PDT 24
Peak memory 201200 kb
Host smart-637f5613-8f4d-4246-b232-2a51bd90435d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589793335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1589793335
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2620206567
Short name T201
Test name
Test status
Simulation time 336792712599 ps
CPU time 73.13 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:00:51 PM PDT 24
Peak memory 201540 kb
Host smart-8231eee9-dbca-453d-887a-9916d953f9fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620206567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2620206567
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.664998809
Short name T178
Test name
Test status
Simulation time 387352759301 ps
CPU time 60.26 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:00:49 PM PDT 24
Peak memory 201448 kb
Host smart-b41f94c8-c674-41ff-8f07-542f0b682753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664998809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.664998809
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3065457458
Short name T709
Test name
Test status
Simulation time 327069349567 ps
CPU time 198.09 seconds
Started Aug 10 05:59:47 PM PDT 24
Finished Aug 10 06:03:05 PM PDT 24
Peak memory 201516 kb
Host smart-b93acc44-c00e-44f3-b755-932085bdecac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065457458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3065457458
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3721371329
Short name T417
Test name
Test status
Simulation time 169696838463 ps
CPU time 399.75 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:06:30 PM PDT 24
Peak memory 201432 kb
Host smart-fc39d789-a4b1-4040-a560-a2214b4faad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721371329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3721371329
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3880812147
Short name T105
Test name
Test status
Simulation time 336077147980 ps
CPU time 129.55 seconds
Started Aug 10 05:59:47 PM PDT 24
Finished Aug 10 06:01:56 PM PDT 24
Peak memory 201312 kb
Host smart-d162449d-8ce1-4127-8c0b-bf9a2489dc17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880812147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3880812147
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3147518231
Short name T614
Test name
Test status
Simulation time 369493960390 ps
CPU time 804.01 seconds
Started Aug 10 05:59:30 PM PDT 24
Finished Aug 10 06:12:54 PM PDT 24
Peak memory 201416 kb
Host smart-bb1f6f9c-c458-484a-90c3-8a25eb9c29d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147518231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3147518231
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2367522088
Short name T693
Test name
Test status
Simulation time 586091438577 ps
CPU time 1363.52 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:22:16 PM PDT 24
Peak memory 201452 kb
Host smart-bb1c5563-188f-4b33-9fc2-6d273879a684
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367522088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2367522088
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2344773225
Short name T350
Test name
Test status
Simulation time 70370678997 ps
CPU time 238.85 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:03:45 PM PDT 24
Peak memory 201824 kb
Host smart-477868ee-4f27-4d2d-a60f-7cf69af19079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344773225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2344773225
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4067053547
Short name T556
Test name
Test status
Simulation time 32484032831 ps
CPU time 79.61 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:00:56 PM PDT 24
Peak memory 201316 kb
Host smart-f74fa3c7-5d1a-4807-b5b6-09c7a09cae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067053547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4067053547
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1076823111
Short name T726
Test name
Test status
Simulation time 3210606241 ps
CPU time 7.75 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 05:59:49 PM PDT 24
Peak memory 201324 kb
Host smart-b8a4ddeb-8b31-4819-b8a2-5e10cc743d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076823111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1076823111
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1365716712
Short name T587
Test name
Test status
Simulation time 5782474491 ps
CPU time 4.33 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 05:59:39 PM PDT 24
Peak memory 201272 kb
Host smart-3aa27da3-f2ae-4510-84ce-3ed6095a55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365716712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1365716712
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1302223041
Short name T631
Test name
Test status
Simulation time 1332048225739 ps
CPU time 1624.43 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:26:56 PM PDT 24
Peak memory 201788 kb
Host smart-a9b71915-ca4e-4c85-9587-819a3a09756e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302223041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1302223041
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2336694356
Short name T215
Test name
Test status
Simulation time 112200777293 ps
CPU time 284.26 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:04:17 PM PDT 24
Peak memory 210532 kb
Host smart-36eb7354-ccc1-41f5-bc41-7b42047269eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336694356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2336694356
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2604409003
Short name T575
Test name
Test status
Simulation time 450969308 ps
CPU time 0.87 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 05:59:34 PM PDT 24
Peak memory 201228 kb
Host smart-67569f55-a90f-4537-a77a-569c42b85ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604409003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2604409003
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.489008355
Short name T485
Test name
Test status
Simulation time 334548131997 ps
CPU time 419.08 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:06:32 PM PDT 24
Peak memory 201476 kb
Host smart-6776346a-f7fb-4926-ae1e-e9b3b4d16089
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489008355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.489008355
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1135831714
Short name T307
Test name
Test status
Simulation time 171676622598 ps
CPU time 106.49 seconds
Started Aug 10 05:59:33 PM PDT 24
Finished Aug 10 06:01:20 PM PDT 24
Peak memory 201472 kb
Host smart-82630c37-d571-4379-8803-e472b0ec4906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135831714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1135831714
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2784294162
Short name T243
Test name
Test status
Simulation time 167451997473 ps
CPU time 354.17 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:05:29 PM PDT 24
Peak memory 201464 kb
Host smart-8e2581d8-7929-4f88-b54c-67754ea4ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784294162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2784294162
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.728519635
Short name T736
Test name
Test status
Simulation time 496453591347 ps
CPU time 116.68 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:01:29 PM PDT 24
Peak memory 201424 kb
Host smart-5f0c9949-1e3f-4a05-9d8f-195a5c13adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728519635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.728519635
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2850011166
Short name T620
Test name
Test status
Simulation time 326286616392 ps
CPU time 352.75 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:05:39 PM PDT 24
Peak memory 201400 kb
Host smart-748ad4f8-8f22-4363-bb37-4d9f69336290
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850011166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2850011166
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2119719108
Short name T276
Test name
Test status
Simulation time 179417423679 ps
CPU time 356.1 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:05:46 PM PDT 24
Peak memory 201436 kb
Host smart-6387b95d-a135-41b2-8d86-c616669152df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119719108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2119719108
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3273118397
Short name T530
Test name
Test status
Simulation time 393514536260 ps
CPU time 220.72 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:03:16 PM PDT 24
Peak memory 201260 kb
Host smart-3adbd4e0-2d48-440b-9dc5-b6c11c21a7bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273118397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3273118397
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1567108865
Short name T716
Test name
Test status
Simulation time 31218123038 ps
CPU time 17.37 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 05:59:52 PM PDT 24
Peak memory 201372 kb
Host smart-8147a38c-8f6f-49d3-8817-2fb7b8555073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567108865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1567108865
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.683149220
Short name T398
Test name
Test status
Simulation time 3606140001 ps
CPU time 8.36 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 05:59:53 PM PDT 24
Peak memory 201300 kb
Host smart-18f22ccb-a7fb-4df6-b533-1f64df507f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683149220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.683149220
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2827586513
Short name T26
Test name
Test status
Simulation time 5963994566 ps
CPU time 15.05 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:00:06 PM PDT 24
Peak memory 201328 kb
Host smart-2f316072-4a28-49ba-9abc-fbf4542bc4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827586513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2827586513
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.545155619
Short name T285
Test name
Test status
Simulation time 206048646844 ps
CPU time 103.25 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:01:22 PM PDT 24
Peak memory 201420 kb
Host smart-a7b45f15-1b47-407b-ba1d-2800d784e568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545155619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
545155619
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1924363577
Short name T597
Test name
Test status
Simulation time 20172773568 ps
CPU time 69.69 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:00:45 PM PDT 24
Peak memory 209960 kb
Host smart-61710799-463a-4750-8248-792ee923de3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924363577 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1924363577
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1579794768
Short name T495
Test name
Test status
Simulation time 312737653 ps
CPU time 1.32 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 201256 kb
Host smart-ede1977e-f58f-47f8-bafb-f3526040a015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579794768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1579794768
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1497599846
Short name T570
Test name
Test status
Simulation time 167250471251 ps
CPU time 105.89 seconds
Started Aug 10 05:59:12 PM PDT 24
Finished Aug 10 06:00:58 PM PDT 24
Peak memory 201448 kb
Host smart-cc3ed4de-1ad7-46fd-ae3d-9503b590698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497599846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1497599846
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2196386321
Short name T596
Test name
Test status
Simulation time 495830628215 ps
CPU time 358.54 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:05:15 PM PDT 24
Peak memory 201472 kb
Host smart-d8693b0a-23e5-4bfd-a8ba-6de598393654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196386321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2196386321
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1639692269
Short name T591
Test name
Test status
Simulation time 164941984647 ps
CPU time 94.99 seconds
Started Aug 10 05:59:13 PM PDT 24
Finished Aug 10 06:00:48 PM PDT 24
Peak memory 201424 kb
Host smart-80d7821e-7613-4d10-9dfa-9f9562d56f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639692269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1639692269
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1683535596
Short name T289
Test name
Test status
Simulation time 169823803547 ps
CPU time 204.62 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:02:43 PM PDT 24
Peak memory 201496 kb
Host smart-2f1e27ec-7579-4612-9c88-d79ea187e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683535596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1683535596
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1475075470
Short name T788
Test name
Test status
Simulation time 487037299130 ps
CPU time 521.32 seconds
Started Aug 10 05:59:20 PM PDT 24
Finished Aug 10 06:08:02 PM PDT 24
Peak memory 201436 kb
Host smart-1a89b409-7b22-4285-9ea0-4824b3db95e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475075470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1475075470
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.258571021
Short name T636
Test name
Test status
Simulation time 196754144485 ps
CPU time 106.67 seconds
Started Aug 10 05:59:08 PM PDT 24
Finished Aug 10 06:00:54 PM PDT 24
Peak memory 201396 kb
Host smart-b154a1fc-1908-486b-b527-94d539d30c7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258571021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.258571021
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3940428787
Short name T639
Test name
Test status
Simulation time 109315197352 ps
CPU time 374.26 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 06:05:10 PM PDT 24
Peak memory 201792 kb
Host smart-b5ff335b-a967-4971-b5f8-fb3d980520ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940428787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3940428787
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.14417208
Short name T668
Test name
Test status
Simulation time 39767523981 ps
CPU time 25.14 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 05:59:23 PM PDT 24
Peak memory 201304 kb
Host smart-5a3a3fe0-3eb5-4702-9473-5d254692db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14417208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.14417208
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2815383783
Short name T691
Test name
Test status
Simulation time 5189581934 ps
CPU time 6.76 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 05:59:10 PM PDT 24
Peak memory 201368 kb
Host smart-20e3f643-b8fa-4850-823b-54723e9379a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815383783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2815383783
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3452395147
Short name T74
Test name
Test status
Simulation time 4220790650 ps
CPU time 10.29 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 05:59:09 PM PDT 24
Peak memory 217232 kb
Host smart-3f3a6dbb-9a1d-4858-830d-3e2d4c07a8a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452395147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3452395147
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3243586871
Short name T558
Test name
Test status
Simulation time 5871895354 ps
CPU time 8.14 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 05:59:06 PM PDT 24
Peak memory 201300 kb
Host smart-3f58e93e-68f0-496d-af43-046b04dfd73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243586871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3243586871
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.665111711
Short name T660
Test name
Test status
Simulation time 227272141225 ps
CPU time 520.59 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:07:43 PM PDT 24
Peak memory 201428 kb
Host smart-1f427cd9-65b8-4b4c-b531-35ce6b0b54ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665111711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.665111711
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4235928314
Short name T300
Test name
Test status
Simulation time 62738813457 ps
CPU time 75.02 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 06:00:11 PM PDT 24
Peak memory 217832 kb
Host smart-5665ddba-cff5-4dfd-a11e-ba6b748ed6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235928314 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4235928314
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1130543472
Short name T16
Test name
Test status
Simulation time 482610320 ps
CPU time 1.55 seconds
Started Aug 10 05:59:44 PM PDT 24
Finished Aug 10 05:59:45 PM PDT 24
Peak memory 201252 kb
Host smart-28f6315b-028d-447d-b464-dd50e02390d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130543472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1130543472
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1085942759
Short name T250
Test name
Test status
Simulation time 368725267711 ps
CPU time 805.8 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 201676 kb
Host smart-091861e2-53e1-4c0a-a212-f0df0f76accd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085942759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1085942759
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.938761635
Short name T514
Test name
Test status
Simulation time 490500685634 ps
CPU time 257.94 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:04:05 PM PDT 24
Peak memory 201432 kb
Host smart-35ef08f7-5dea-4869-a5c4-879e40102951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938761635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.938761635
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.24040133
Short name T674
Test name
Test status
Simulation time 488969180767 ps
CPU time 555.21 seconds
Started Aug 10 05:59:40 PM PDT 24
Finished Aug 10 06:08:55 PM PDT 24
Peak memory 201636 kb
Host smart-bcb3ce5b-aa67-4f88-bece-7e467d94f03f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=24040133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt
_fixed.24040133
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.718683834
Short name T734
Test name
Test status
Simulation time 162360449529 ps
CPU time 96.25 seconds
Started Aug 10 05:59:53 PM PDT 24
Finished Aug 10 06:01:29 PM PDT 24
Peak memory 201404 kb
Host smart-65341efc-b736-45a1-a204-a8c5156acc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718683834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.718683834
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.170219828
Short name T671
Test name
Test status
Simulation time 328605434756 ps
CPU time 180.13 seconds
Started Aug 10 05:59:35 PM PDT 24
Finished Aug 10 06:02:35 PM PDT 24
Peak memory 201436 kb
Host smart-3903da00-6ee6-47dc-8431-eb7c3707374a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=170219828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.170219828
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.828565789
Short name T405
Test name
Test status
Simulation time 206855130968 ps
CPU time 121.45 seconds
Started Aug 10 05:59:54 PM PDT 24
Finished Aug 10 06:01:56 PM PDT 24
Peak memory 201432 kb
Host smart-cbfa5e54-16a6-47c7-8871-b202a819519a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828565789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.828565789
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3664796634
Short name T349
Test name
Test status
Simulation time 108532621366 ps
CPU time 575.77 seconds
Started Aug 10 05:59:36 PM PDT 24
Finished Aug 10 06:09:12 PM PDT 24
Peak memory 201868 kb
Host smart-a41fb84f-80c3-4ff9-ad3d-5f3a62dad318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664796634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3664796634
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2731755286
Short name T378
Test name
Test status
Simulation time 28888555840 ps
CPU time 16.91 seconds
Started Aug 10 05:59:34 PM PDT 24
Finished Aug 10 05:59:51 PM PDT 24
Peak memory 201376 kb
Host smart-5da16da1-a6a8-48a0-b05b-5e7ade8c9a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731755286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2731755286
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.794844406
Short name T477
Test name
Test status
Simulation time 3566649375 ps
CPU time 1.77 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 05:59:52 PM PDT 24
Peak memory 201336 kb
Host smart-cbfdcf5e-b6d3-47eb-b1f7-45b49d94d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794844406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.794844406
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1423154413
Short name T760
Test name
Test status
Simulation time 6085111470 ps
CPU time 4.38 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 05:59:57 PM PDT 24
Peak memory 201340 kb
Host smart-4ddbec4e-0e04-476c-a852-b98328d9f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423154413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1423154413
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.696357493
Short name T311
Test name
Test status
Simulation time 380419245985 ps
CPU time 230.03 seconds
Started Aug 10 05:59:32 PM PDT 24
Finished Aug 10 06:03:22 PM PDT 24
Peak memory 201420 kb
Host smart-e46765ae-26bb-429d-81a3-d0a3a661579c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696357493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
696357493
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3913727360
Short name T508
Test name
Test status
Simulation time 473443236 ps
CPU time 1.8 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 05:59:54 PM PDT 24
Peak memory 201228 kb
Host smart-138eda94-80e9-4db6-afce-71f4f927d282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913727360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3913727360
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.365737612
Short name T787
Test name
Test status
Simulation time 399338390428 ps
CPU time 940.24 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:15:27 PM PDT 24
Peak memory 201560 kb
Host smart-c9f8d702-80bc-4d0b-b26e-8f6b55edab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365737612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.365737612
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1083331827
Short name T524
Test name
Test status
Simulation time 331271242309 ps
CPU time 276.07 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:04:24 PM PDT 24
Peak memory 201452 kb
Host smart-cd8068af-baff-480d-80a3-a572a42dfc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083331827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1083331827
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1341196368
Short name T167
Test name
Test status
Simulation time 486674132213 ps
CPU time 189.25 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:02:55 PM PDT 24
Peak memory 201456 kb
Host smart-bc10f3d7-7df0-40a4-90ed-be3426d4f8d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341196368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1341196368
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1368258280
Short name T679
Test name
Test status
Simulation time 163050912218 ps
CPU time 331.46 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:05:22 PM PDT 24
Peak memory 201428 kb
Host smart-46a52d85-b7a3-4dd6-88d1-91e23790df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368258280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1368258280
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.56700117
Short name T641
Test name
Test status
Simulation time 336071846295 ps
CPU time 488.87 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:08:00 PM PDT 24
Peak memory 201376 kb
Host smart-d74aba5a-d716-4104-a362-ad6cf0802ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=56700117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.56700117
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3370530409
Short name T320
Test name
Test status
Simulation time 443385794588 ps
CPU time 1056.15 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:17:26 PM PDT 24
Peak memory 201448 kb
Host smart-46d4e43b-c646-45e3-aead-d768883fdedd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370530409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3370530409
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2687151617
Short name T682
Test name
Test status
Simulation time 199477351932 ps
CPU time 240.92 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:03:49 PM PDT 24
Peak memory 201452 kb
Host smart-61529dee-3f16-4a08-9cb2-de99d3b65469
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687151617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2687151617
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1044522963
Short name T227
Test name
Test status
Simulation time 81428031049 ps
CPU time 337.36 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:05:28 PM PDT 24
Peak memory 201780 kb
Host smart-94d3d3b5-2b21-48ae-b724-00477059984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044522963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1044522963
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1166609542
Short name T628
Test name
Test status
Simulation time 24465797254 ps
CPU time 50.08 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:00:42 PM PDT 24
Peak memory 201332 kb
Host smart-21c91ac2-6e11-43c6-949d-af893f2f6920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166609542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1166609542
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3525925762
Short name T361
Test name
Test status
Simulation time 4163048906 ps
CPU time 9.95 seconds
Started Aug 10 05:59:44 PM PDT 24
Finished Aug 10 05:59:54 PM PDT 24
Peak memory 201328 kb
Host smart-12c98035-dbac-4d8d-bcf3-9822be11fe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525925762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3525925762
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.10880324
Short name T156
Test name
Test status
Simulation time 5804229068 ps
CPU time 2.65 seconds
Started Aug 10 05:59:43 PM PDT 24
Finished Aug 10 05:59:45 PM PDT 24
Peak memory 201392 kb
Host smart-497e641f-eea2-4063-b8e9-c8bde1759441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10880324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.10880324
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2598844747
Short name T326
Test name
Test status
Simulation time 161484696439 ps
CPU time 64.63 seconds
Started Aug 10 05:59:53 PM PDT 24
Finished Aug 10 06:00:58 PM PDT 24
Peak memory 209872 kb
Host smart-93651782-ed1e-4c1b-93ad-7295b18a0f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598844747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2598844747
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.705148169
Short name T385
Test name
Test status
Simulation time 413175685 ps
CPU time 0.98 seconds
Started Aug 10 05:59:43 PM PDT 24
Finished Aug 10 05:59:44 PM PDT 24
Peak memory 201248 kb
Host smart-1e398ef5-581c-4a90-bd95-2a821cf23b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705148169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.705148169
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1165966009
Short name T715
Test name
Test status
Simulation time 328689535291 ps
CPU time 817.36 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:13:27 PM PDT 24
Peak memory 201460 kb
Host smart-398f0701-76e4-40c6-81d1-9effcb2b5171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165966009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1165966009
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.226618827
Short name T561
Test name
Test status
Simulation time 325158433991 ps
CPU time 708.22 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:11:37 PM PDT 24
Peak memory 201516 kb
Host smart-144ce29f-56ce-41ec-8f51-f1da64cd4c21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=226618827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.226618827
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1970370454
Short name T337
Test name
Test status
Simulation time 162108862359 ps
CPU time 86.52 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:01:16 PM PDT 24
Peak memory 201464 kb
Host smart-09ff1f4c-c1e5-41b0-9e08-468d3e1f49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970370454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1970370454
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3690118152
Short name T403
Test name
Test status
Simulation time 490349513039 ps
CPU time 288.22 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:04:37 PM PDT 24
Peak memory 201412 kb
Host smart-66900935-3e82-406b-881f-e8b8ce1ebf0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690118152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3690118152
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2699035185
Short name T183
Test name
Test status
Simulation time 543769676224 ps
CPU time 105.78 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:01:34 PM PDT 24
Peak memory 201444 kb
Host smart-28aecf93-6a22-47ba-80b0-6193c64f1709
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699035185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2699035185
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.883794571
Short name T437
Test name
Test status
Simulation time 414456187490 ps
CPU time 143.06 seconds
Started Aug 10 05:59:53 PM PDT 24
Finished Aug 10 06:02:16 PM PDT 24
Peak memory 201440 kb
Host smart-1af18f01-a6f4-4e92-83ca-0dba2ec04307
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883794571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.883794571
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1403889268
Short name T608
Test name
Test status
Simulation time 125102010477 ps
CPU time 418.55 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:06:51 PM PDT 24
Peak memory 201800 kb
Host smart-36c43f33-c4f3-4789-b760-a8d1929aec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403889268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1403889268
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3994077611
Short name T779
Test name
Test status
Simulation time 47014018551 ps
CPU time 105.02 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:01:37 PM PDT 24
Peak memory 201304 kb
Host smart-6959ef57-ab55-438c-ae1e-e9c224cfa730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994077611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3994077611
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3929159702
Short name T643
Test name
Test status
Simulation time 4873846746 ps
CPU time 3.42 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 05:59:49 PM PDT 24
Peak memory 201364 kb
Host smart-552c58b1-45f6-45cd-9cca-33b840453333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929159702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3929159702
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3710478658
Short name T425
Test name
Test status
Simulation time 5907456561 ps
CPU time 14.44 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:00:07 PM PDT 24
Peak memory 201340 kb
Host smart-03adf41e-4513-46f1-bda8-e9c2d4469e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710478658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3710478658
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1590012360
Short name T323
Test name
Test status
Simulation time 354053394899 ps
CPU time 208.54 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 201464 kb
Host smart-e921e519-9565-455a-a9ac-da20cb35d60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590012360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1590012360
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3253117235
Short name T292
Test name
Test status
Simulation time 71819076681 ps
CPU time 160.7 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:02:32 PM PDT 24
Peak memory 209764 kb
Host smart-bdbee905-a37f-422b-b33b-fb36097e3dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253117235 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3253117235
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2443976974
Short name T537
Test name
Test status
Simulation time 366424812 ps
CPU time 0.81 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 05:59:46 PM PDT 24
Peak memory 201264 kb
Host smart-62a608aa-d6ba-446f-b061-dd209362108c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443976974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2443976974
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.876258261
Short name T769
Test name
Test status
Simulation time 343244020216 ps
CPU time 642.29 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:10:35 PM PDT 24
Peak memory 201444 kb
Host smart-75a746d9-b555-4433-a249-c75e6c47cec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876258261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.876258261
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2316365091
Short name T332
Test name
Test status
Simulation time 533598140666 ps
CPU time 214.56 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:03:25 PM PDT 24
Peak memory 201488 kb
Host smart-795fa2b3-6f20-4a9b-9a48-87e0b7f0726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316365091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2316365091
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3920233220
Short name T402
Test name
Test status
Simulation time 491062686819 ps
CPU time 96.32 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:01:27 PM PDT 24
Peak memory 201444 kb
Host smart-4ed40746-4ac8-41bb-9ad4-ea42a1281b9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920233220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3920233220
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2454987467
Short name T353
Test name
Test status
Simulation time 495190807845 ps
CPU time 1153.38 seconds
Started Aug 10 05:59:45 PM PDT 24
Finished Aug 10 06:18:59 PM PDT 24
Peak memory 201468 kb
Host smart-aa0ab8cb-200d-4c8b-b62e-53e14b51cf19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454987467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2454987467
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3451282013
Short name T770
Test name
Test status
Simulation time 190855850209 ps
CPU time 78.77 seconds
Started Aug 10 05:59:43 PM PDT 24
Finished Aug 10 06:01:02 PM PDT 24
Peak memory 201388 kb
Host smart-4c91048f-c85a-459e-b9c4-27e70d4d38e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451282013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3451282013
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3115692227
Short name T159
Test name
Test status
Simulation time 605172827273 ps
CPU time 348.32 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:05:37 PM PDT 24
Peak memory 201452 kb
Host smart-7f81eb04-86d1-4feb-bd88-3a83b06c6042
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115692227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3115692227
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4136916330
Short name T505
Test name
Test status
Simulation time 84273000754 ps
CPU time 427.06 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:06:58 PM PDT 24
Peak memory 201792 kb
Host smart-c5eea22f-0d16-4487-8d6a-b3214a8d7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136916330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4136916330
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1900793597
Short name T727
Test name
Test status
Simulation time 27465733069 ps
CPU time 68.26 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:01:00 PM PDT 24
Peak memory 201308 kb
Host smart-e14efa33-c47e-4327-b976-1b4080bfcdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900793597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1900793597
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2071499279
Short name T75
Test name
Test status
Simulation time 3859404129 ps
CPU time 8.41 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 05:59:58 PM PDT 24
Peak memory 201364 kb
Host smart-ce49d67c-467a-47f5-af26-88ed23fae8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071499279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2071499279
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.34267971
Short name T689
Test name
Test status
Simulation time 6064468222 ps
CPU time 7.81 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 05:59:50 PM PDT 24
Peak memory 201340 kb
Host smart-546e1c4e-7e14-4f80-bc95-0bdf6db8aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34267971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.34267971
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2070704280
Short name T269
Test name
Test status
Simulation time 454940998942 ps
CPU time 592.55 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:09:45 PM PDT 24
Peak memory 201792 kb
Host smart-48985b46-8cac-4235-9c5c-7304355872cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070704280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2070704280
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2450367877
Short name T342
Test name
Test status
Simulation time 160524611112 ps
CPU time 176.62 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 06:02:45 PM PDT 24
Peak memory 212180 kb
Host smart-26da815f-fe7c-4689-8c10-08c5344dc0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450367877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2450367877
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1656901018
Short name T721
Test name
Test status
Simulation time 294447822 ps
CPU time 0.8 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 05:59:52 PM PDT 24
Peak memory 201148 kb
Host smart-88a87d63-f786-462d-8535-0c779b43b0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656901018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1656901018
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1513904270
Short name T581
Test name
Test status
Simulation time 168270180964 ps
CPU time 195.71 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:03:05 PM PDT 24
Peak memory 201460 kb
Host smart-cf051540-4878-439c-9788-c569f9ae2699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513904270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1513904270
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.21148563
Short name T685
Test name
Test status
Simulation time 496209901415 ps
CPU time 196.52 seconds
Started Aug 10 05:59:49 PM PDT 24
Finished Aug 10 06:03:06 PM PDT 24
Peak memory 201528 kb
Host smart-8a3c7ca8-c221-410a-98c5-dbec84fa166f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt
_fixed.21148563
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3515419828
Short name T304
Test name
Test status
Simulation time 500869449926 ps
CPU time 1060.98 seconds
Started Aug 10 05:59:42 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 201452 kb
Host smart-3dd17d4f-fbc6-4408-8d76-64a73c7c12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515419828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3515419828
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4183438805
Short name T9
Test name
Test status
Simulation time 165236457769 ps
CPU time 374.59 seconds
Started Aug 10 05:59:46 PM PDT 24
Finished Aug 10 06:06:00 PM PDT 24
Peak memory 201328 kb
Host smart-3b51a888-7f6a-48fd-b572-50fdc9effede
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183438805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4183438805
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.628987496
Short name T443
Test name
Test status
Simulation time 603207031074 ps
CPU time 347.46 seconds
Started Aug 10 05:59:56 PM PDT 24
Finished Aug 10 06:05:44 PM PDT 24
Peak memory 201448 kb
Host smart-def20fa6-f87e-4783-8df3-c6267ada2eea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628987496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.628987496
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2255852141
Short name T47
Test name
Test status
Simulation time 90995831760 ps
CPU time 375.45 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:06:07 PM PDT 24
Peak memory 201772 kb
Host smart-9b34692c-98e3-4054-8820-00b44fdaa742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255852141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2255852141
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1094605998
Short name T392
Test name
Test status
Simulation time 41442348624 ps
CPU time 20.21 seconds
Started Aug 10 05:59:54 PM PDT 24
Finished Aug 10 06:00:15 PM PDT 24
Peak memory 201324 kb
Host smart-4fac0614-c054-4ff4-8496-225c5ad8ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094605998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1094605998
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.621181447
Short name T453
Test name
Test status
Simulation time 4245133534 ps
CPU time 9.19 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:00:01 PM PDT 24
Peak memory 201532 kb
Host smart-005c0469-5b58-4657-affb-8cd1c0ff9f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621181447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.621181447
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3369965600
Short name T576
Test name
Test status
Simulation time 5958252622 ps
CPU time 7.04 seconds
Started Aug 10 05:59:48 PM PDT 24
Finished Aug 10 05:59:55 PM PDT 24
Peak memory 201300 kb
Host smart-52742fd6-69cf-4aa4-9296-41cf11cdc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369965600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3369965600
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1310371678
Short name T144
Test name
Test status
Simulation time 167980392633 ps
CPU time 381.75 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:06:13 PM PDT 24
Peak memory 201448 kb
Host smart-bf309ee7-eca7-4e12-abc1-231a03dfcbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310371678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1310371678
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2874609422
Short name T22
Test name
Test status
Simulation time 44911260963 ps
CPU time 99.23 seconds
Started Aug 10 05:59:53 PM PDT 24
Finished Aug 10 06:01:32 PM PDT 24
Peak memory 210128 kb
Host smart-67620a0e-a232-44e8-8d50-eb9e5ceece73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874609422 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2874609422
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2122113797
Short name T630
Test name
Test status
Simulation time 375156313 ps
CPU time 1.43 seconds
Started Aug 10 05:59:55 PM PDT 24
Finished Aug 10 05:59:56 PM PDT 24
Peak memory 201212 kb
Host smart-be106526-1c62-40b5-b9d8-f7d6aadadac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122113797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2122113797
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3630534881
Short name T199
Test name
Test status
Simulation time 333890496071 ps
CPU time 196.76 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:03:08 PM PDT 24
Peak memory 201512 kb
Host smart-63fdb639-f7a8-423a-977d-3718ee0571f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630534881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3630534881
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1445677554
Short name T187
Test name
Test status
Simulation time 491383425412 ps
CPU time 116.29 seconds
Started Aug 10 05:59:56 PM PDT 24
Finished Aug 10 06:01:53 PM PDT 24
Peak memory 201492 kb
Host smart-9dbb13a6-66d2-4b35-8564-359052b75b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445677554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1445677554
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3121125233
Short name T483
Test name
Test status
Simulation time 164550808383 ps
CPU time 375.88 seconds
Started Aug 10 05:59:55 PM PDT 24
Finished Aug 10 06:06:11 PM PDT 24
Peak memory 201352 kb
Host smart-f6d7f3f7-a8e8-4d08-9ccc-96d6c11d4874
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121125233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3121125233
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3944711301
Short name T161
Test name
Test status
Simulation time 163475410120 ps
CPU time 325.81 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:05:18 PM PDT 24
Peak memory 201392 kb
Host smart-abb848a5-ce85-4078-bec8-3c6ee158b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944711301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3944711301
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3817676710
Short name T399
Test name
Test status
Simulation time 330085640394 ps
CPU time 69.76 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:01:10 PM PDT 24
Peak memory 201368 kb
Host smart-bdb2374a-2928-4065-9b2a-7d0cc625fab7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817676710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3817676710
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.260729364
Short name T100
Test name
Test status
Simulation time 184122900793 ps
CPU time 41.78 seconds
Started Aug 10 05:59:52 PM PDT 24
Finished Aug 10 06:00:34 PM PDT 24
Peak memory 201456 kb
Host smart-5710df00-0cdc-45dc-85fb-a8a3487e278e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260729364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.260729364
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.387868189
Short name T567
Test name
Test status
Simulation time 190251477587 ps
CPU time 206.78 seconds
Started Aug 10 05:59:51 PM PDT 24
Finished Aug 10 06:03:18 PM PDT 24
Peak memory 201464 kb
Host smart-c78f62a9-f000-4789-8d91-4793f9dd8d12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387868189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.387868189
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2660600737
Short name T223
Test name
Test status
Simulation time 70167327699 ps
CPU time 236.5 seconds
Started Aug 10 05:59:56 PM PDT 24
Finished Aug 10 06:03:53 PM PDT 24
Peak memory 201792 kb
Host smart-2da4a890-9166-4997-97d1-1659c5231f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660600737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2660600737
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3745511053
Short name T504
Test name
Test status
Simulation time 23101228011 ps
CPU time 13.35 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:00:03 PM PDT 24
Peak memory 201240 kb
Host smart-d953b5d5-741d-4df0-8021-1522fa3e711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745511053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3745511053
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3568268528
Short name T573
Test name
Test status
Simulation time 4810248015 ps
CPU time 5.92 seconds
Started Aug 10 05:59:56 PM PDT 24
Finished Aug 10 06:00:02 PM PDT 24
Peak memory 201344 kb
Host smart-61f66ae4-0ad8-48b5-a37c-979ad3ef8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568268528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3568268528
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3906596382
Short name T486
Test name
Test status
Simulation time 5991753706 ps
CPU time 1.5 seconds
Started Aug 10 05:59:53 PM PDT 24
Finished Aug 10 05:59:54 PM PDT 24
Peak memory 201304 kb
Host smart-ae8bf9f1-594a-45f9-94e7-313c01f57587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906596382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3906596382
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2867035588
Short name T752
Test name
Test status
Simulation time 696834734293 ps
CPU time 458.54 seconds
Started Aug 10 05:59:54 PM PDT 24
Finished Aug 10 06:07:32 PM PDT 24
Peak memory 201396 kb
Host smart-6f34c370-f29d-4227-b5fd-8811c1e60f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867035588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2867035588
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1868643073
Short name T20
Test name
Test status
Simulation time 62784898953 ps
CPU time 54.27 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:00:45 PM PDT 24
Peak memory 210164 kb
Host smart-92b26d44-2637-4dea-bcc4-081073ad7620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868643073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1868643073
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3021502684
Short name T767
Test name
Test status
Simulation time 482904383 ps
CPU time 1.17 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:00:07 PM PDT 24
Peak memory 201208 kb
Host smart-594331c3-fb53-4f15-959b-cb766278bbaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021502684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3021502684
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1231029320
Short name T240
Test name
Test status
Simulation time 537439575885 ps
CPU time 912.22 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:15:12 PM PDT 24
Peak memory 201568 kb
Host smart-eec23e44-b9eb-4e96-aa72-ce99b06f35a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231029320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1231029320
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1697896557
Short name T168
Test name
Test status
Simulation time 346629512594 ps
CPU time 729.67 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:12:16 PM PDT 24
Peak memory 201380 kb
Host smart-b6b322f6-b00b-497d-b1df-e7bff2d333f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697896557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1697896557
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3623826606
Short name T456
Test name
Test status
Simulation time 322869115253 ps
CPU time 322.51 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:05:29 PM PDT 24
Peak memory 201516 kb
Host smart-6f3ba801-24d4-462b-8f89-d729453b99a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623826606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3623826606
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3670660884
Short name T666
Test name
Test status
Simulation time 327143912935 ps
CPU time 401.2 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:06:42 PM PDT 24
Peak memory 201464 kb
Host smart-4ba23c03-90a1-40e1-a87a-341ef64ebc3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670660884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3670660884
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2708853901
Short name T322
Test name
Test status
Simulation time 607472512299 ps
CPU time 371.01 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:06:17 PM PDT 24
Peak memory 201436 kb
Host smart-cfb069c9-b201-4607-872f-89cefcba0f25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708853901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2708853901
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.687287821
Short name T358
Test name
Test status
Simulation time 219810846151 ps
CPU time 291.89 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:04:52 PM PDT 24
Peak memory 201444 kb
Host smart-5340117e-c891-4a91-85c5-8fa58b8c34ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687287821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.687287821
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.280327110
Short name T520
Test name
Test status
Simulation time 131142296272 ps
CPU time 683.16 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:11:24 PM PDT 24
Peak memory 201884 kb
Host smart-1b23b09a-6924-46a5-90d8-ef2cee07a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280327110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.280327110
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2126262168
Short name T492
Test name
Test status
Simulation time 46012441645 ps
CPU time 24.72 seconds
Started Aug 10 06:00:03 PM PDT 24
Finished Aug 10 06:00:31 PM PDT 24
Peak memory 201356 kb
Host smart-3327a761-e373-4442-8877-957c124f9b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126262168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2126262168
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3449913220
Short name T371
Test name
Test status
Simulation time 3635880366 ps
CPU time 9.54 seconds
Started Aug 10 06:00:03 PM PDT 24
Finished Aug 10 06:00:16 PM PDT 24
Peak memory 201372 kb
Host smart-6f824700-42f8-41fe-b889-d4ec7f699167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449913220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3449913220
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3074538335
Short name T430
Test name
Test status
Simulation time 6037302583 ps
CPU time 15.86 seconds
Started Aug 10 05:59:50 PM PDT 24
Finished Aug 10 06:00:06 PM PDT 24
Peak memory 201364 kb
Host smart-f559a864-d7d9-4db9-97b4-3eee2d8a6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074538335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3074538335
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.760287468
Short name T786
Test name
Test status
Simulation time 265546137286 ps
CPU time 354.17 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:06:00 PM PDT 24
Peak memory 210028 kb
Host smart-f461bcab-30de-44d9-acc0-13878a6c7893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760287468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
760287468
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.511658257
Short name T493
Test name
Test status
Simulation time 419185803 ps
CPU time 1.07 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:00:12 PM PDT 24
Peak memory 201264 kb
Host smart-ab1bd0ab-32de-4fdd-930b-3759358dc83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511658257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.511658257
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2857438473
Short name T330
Test name
Test status
Simulation time 506249172809 ps
CPU time 136.16 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:02:22 PM PDT 24
Peak memory 201424 kb
Host smart-d4bae3f6-e539-4747-835b-0501a4be4cba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857438473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2857438473
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1674543390
Short name T251
Test name
Test status
Simulation time 396126875631 ps
CPU time 171.05 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:02:57 PM PDT 24
Peak memory 201412 kb
Host smart-b65ea869-cb21-4a47-94e6-a36dff182ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674543390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1674543390
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.464285440
Short name T188
Test name
Test status
Simulation time 488376935569 ps
CPU time 126.59 seconds
Started Aug 10 06:00:04 PM PDT 24
Finished Aug 10 06:02:13 PM PDT 24
Peak memory 201472 kb
Host smart-edaee611-db16-4135-9552-16bbfe8b716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464285440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.464285440
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.979127443
Short name T640
Test name
Test status
Simulation time 494766765201 ps
CPU time 1177.25 seconds
Started Aug 10 06:00:02 PM PDT 24
Finished Aug 10 06:19:43 PM PDT 24
Peak memory 201324 kb
Host smart-c6401c30-7c3a-45d8-8711-0ea3b59b5c96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=979127443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.979127443
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.901086287
Short name T475
Test name
Test status
Simulation time 166723107523 ps
CPU time 406.38 seconds
Started Aug 10 06:00:03 PM PDT 24
Finished Aug 10 06:06:52 PM PDT 24
Peak memory 201428 kb
Host smart-daec3764-8f6d-4154-8ba1-c88cf94d9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901086287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.901086287
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1648400832
Short name T173
Test name
Test status
Simulation time 160265774929 ps
CPU time 343.58 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:05:44 PM PDT 24
Peak memory 201416 kb
Host smart-1d2a8bd4-ce67-4ab5-9524-47586aa134b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648400832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1648400832
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.56807902
Short name T193
Test name
Test status
Simulation time 530850350895 ps
CPU time 190.52 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:03:11 PM PDT 24
Peak memory 201448 kb
Host smart-1e10aa2b-d215-4d76-97c9-a47450fbc7a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56807902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_w
akeup.56807902
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1404298729
Short name T548
Test name
Test status
Simulation time 192834244592 ps
CPU time 449.45 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:07:30 PM PDT 24
Peak memory 201468 kb
Host smart-14f15344-0c93-4579-9182-5bebdb2bde9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404298729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1404298729
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.56563412
Short name T604
Test name
Test status
Simulation time 76983441154 ps
CPU time 324.43 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:05:25 PM PDT 24
Peak memory 201824 kb
Host smart-e7254a20-a443-42c0-ae25-130bd50adf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56563412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.56563412
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.671769524
Short name T662
Test name
Test status
Simulation time 22109374490 ps
CPU time 13.16 seconds
Started Aug 10 06:00:01 PM PDT 24
Finished Aug 10 06:00:19 PM PDT 24
Peak memory 201372 kb
Host smart-76e014d3-1a37-4755-b142-5113cd738923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671769524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.671769524
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4057659442
Short name T751
Test name
Test status
Simulation time 3811839847 ps
CPU time 9.95 seconds
Started Aug 10 06:00:05 PM PDT 24
Finished Aug 10 06:00:16 PM PDT 24
Peak memory 201336 kb
Host smart-fa0ebbb7-a689-43c8-9ed0-8b6bf505a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057659442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4057659442
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1632916807
Short name T2
Test name
Test status
Simulation time 5666651997 ps
CPU time 4.48 seconds
Started Aug 10 06:00:00 PM PDT 24
Finished Aug 10 06:00:04 PM PDT 24
Peak memory 201356 kb
Host smart-53625ebe-4c45-4228-bac1-78584034d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632916807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1632916807
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.576608827
Short name T282
Test name
Test status
Simulation time 230430574591 ps
CPU time 433.32 seconds
Started Aug 10 06:00:15 PM PDT 24
Finished Aug 10 06:07:29 PM PDT 24
Peak memory 217728 kb
Host smart-d8a17a3a-39c8-4e47-a6e6-20efc875cd5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576608827 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.576608827
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.792663797
Short name T355
Test name
Test status
Simulation time 370185965 ps
CPU time 0.98 seconds
Started Aug 10 06:00:13 PM PDT 24
Finished Aug 10 06:00:14 PM PDT 24
Peak memory 201204 kb
Host smart-23f9f21a-8a8a-47b1-96f1-ab7b77b00cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792663797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.792663797
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.811486760
Short name T634
Test name
Test status
Simulation time 166367452681 ps
CPU time 84.61 seconds
Started Aug 10 06:00:14 PM PDT 24
Finished Aug 10 06:01:39 PM PDT 24
Peak memory 201460 kb
Host smart-232ba667-309b-4909-8d17-cde8fc2859d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811486760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.811486760
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1328280534
Short name T328
Test name
Test status
Simulation time 330535915885 ps
CPU time 410.06 seconds
Started Aug 10 06:00:15 PM PDT 24
Finished Aug 10 06:07:05 PM PDT 24
Peak memory 201476 kb
Host smart-793445ad-2504-448e-b247-2822f6c7ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328280534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1328280534
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2625571013
Short name T741
Test name
Test status
Simulation time 486324571644 ps
CPU time 565.57 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:09:38 PM PDT 24
Peak memory 201476 kb
Host smart-4dcd7bc1-8cf9-46b3-aab7-325ff97838fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625571013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2625571013
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2138247110
Short name T185
Test name
Test status
Simulation time 490408724271 ps
CPU time 290.22 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:05:02 PM PDT 24
Peak memory 201464 kb
Host smart-298fb7c3-c19d-479a-ae6c-f6edf785478f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138247110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2138247110
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4275519559
Short name T148
Test name
Test status
Simulation time 491595222109 ps
CPU time 1155.79 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 201540 kb
Host smart-6951e699-0f24-4c5b-a268-362b7ab025f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275519559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4275519559
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3458781155
Short name T706
Test name
Test status
Simulation time 495543250594 ps
CPU time 1088.49 seconds
Started Aug 10 06:00:16 PM PDT 24
Finished Aug 10 06:18:25 PM PDT 24
Peak memory 201364 kb
Host smart-b4d1e05c-8cfa-4c8a-879d-240f649f4110
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458781155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3458781155
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2822628110
Short name T294
Test name
Test status
Simulation time 561222164747 ps
CPU time 1276.7 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:21:29 PM PDT 24
Peak memory 201496 kb
Host smart-6a8cc282-57db-4a94-9706-f2fb41625242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822628110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2822628110
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2034972135
Short name T390
Test name
Test status
Simulation time 403519435221 ps
CPU time 219.18 seconds
Started Aug 10 06:00:14 PM PDT 24
Finished Aug 10 06:03:54 PM PDT 24
Peak memory 201396 kb
Host smart-f3f538e5-1fb4-4d6a-bd30-795f0da3ed8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034972135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2034972135
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1550305736
Short name T438
Test name
Test status
Simulation time 34628167999 ps
CPU time 41.3 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:00:52 PM PDT 24
Peak memory 201244 kb
Host smart-534003d5-187b-469b-8407-c1dbb4adffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550305736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1550305736
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2207114219
Short name T389
Test name
Test status
Simulation time 5088492729 ps
CPU time 3.84 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:00:15 PM PDT 24
Peak memory 201360 kb
Host smart-b760ea05-beb9-488e-a9da-69ac00b3f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207114219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2207114219
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2236139814
Short name T421
Test name
Test status
Simulation time 6113590954 ps
CPU time 12.7 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:00:24 PM PDT 24
Peak memory 201252 kb
Host smart-9a162323-843a-437c-bb5f-95cfa557578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236139814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2236139814
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.45004616
Short name T705
Test name
Test status
Simulation time 26554098660 ps
CPU time 12.62 seconds
Started Aug 10 06:00:15 PM PDT 24
Finished Aug 10 06:00:28 PM PDT 24
Peak memory 201272 kb
Host smart-0c119928-fc3c-40b2-bcfc-6c40daf383f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45004616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.45004616
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2315546534
Short name T262
Test name
Test status
Simulation time 36169629300 ps
CPU time 113.6 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:02:06 PM PDT 24
Peak memory 210248 kb
Host smart-ee160e07-8818-4617-9c76-2f72f5018c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315546534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2315546534
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3986465640
Short name T580
Test name
Test status
Simulation time 461656882 ps
CPU time 0.84 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:00:23 PM PDT 24
Peak memory 201248 kb
Host smart-631a70d2-67d1-45e5-8ea3-62bd1ca339de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986465640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3986465640
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2081103056
Short name T211
Test name
Test status
Simulation time 324941933426 ps
CPU time 183.77 seconds
Started Aug 10 06:00:14 PM PDT 24
Finished Aug 10 06:03:18 PM PDT 24
Peak memory 201432 kb
Host smart-2f6682ed-56e1-4ebf-9a94-9b10bb037878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081103056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2081103056
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.268398389
Short name T657
Test name
Test status
Simulation time 493243853157 ps
CPU time 822.23 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:13:55 PM PDT 24
Peak memory 201404 kb
Host smart-cfe27a17-ab36-4df2-8214-4f901620e38e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=268398389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.268398389
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2110657713
Short name T617
Test name
Test status
Simulation time 489283261103 ps
CPU time 270.59 seconds
Started Aug 10 06:00:11 PM PDT 24
Finished Aug 10 06:04:42 PM PDT 24
Peak memory 201480 kb
Host smart-b56542a4-c46a-402e-b44c-e4830079b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110657713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2110657713
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.782370811
Short name T410
Test name
Test status
Simulation time 492316501117 ps
CPU time 427.52 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:07:20 PM PDT 24
Peak memory 201440 kb
Host smart-26c7b9b9-73dd-473d-9e66-aac266875c47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=782370811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.782370811
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2777183523
Short name T163
Test name
Test status
Simulation time 174101238399 ps
CPU time 377.22 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:06:29 PM PDT 24
Peak memory 201440 kb
Host smart-31dd7c7d-ad04-4e8f-a172-6f97a722cab7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777183523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2777183523
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2268242310
Short name T747
Test name
Test status
Simulation time 205281221710 ps
CPU time 118.52 seconds
Started Aug 10 06:00:10 PM PDT 24
Finished Aug 10 06:02:09 PM PDT 24
Peak memory 201424 kb
Host smart-8d4135a7-b70c-47c0-9c5b-ffa32880390f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268242310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2268242310
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3128779316
Short name T414
Test name
Test status
Simulation time 70832224894 ps
CPU time 274.45 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:04:58 PM PDT 24
Peak memory 201728 kb
Host smart-5f5a12e4-8f26-4795-adf5-52c8df6f3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128779316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3128779316
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2711510787
Short name T407
Test name
Test status
Simulation time 30580828800 ps
CPU time 66.47 seconds
Started Aug 10 06:00:26 PM PDT 24
Finished Aug 10 06:01:32 PM PDT 24
Peak memory 201320 kb
Host smart-3ba4e4ae-cca6-44e0-8263-c14ad53c71ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711510787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2711510787
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.342898196
Short name T603
Test name
Test status
Simulation time 4279698917 ps
CPU time 11.08 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:00:33 PM PDT 24
Peak memory 201300 kb
Host smart-0bb3cd53-b9c9-4f8d-9f2c-31b015312667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342898196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.342898196
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1967298135
Short name T676
Test name
Test status
Simulation time 6078739367 ps
CPU time 3.6 seconds
Started Aug 10 06:00:12 PM PDT 24
Finished Aug 10 06:00:15 PM PDT 24
Peak memory 201308 kb
Host smart-0432dc9d-bca4-492b-8ddf-5ae6d0f5902b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967298135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1967298135
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2482104414
Short name T627
Test name
Test status
Simulation time 603302617956 ps
CPU time 600.15 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:10:23 PM PDT 24
Peak memory 210104 kb
Host smart-c2531a7b-95e6-4214-a6dc-4dfeef621c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482104414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2482104414
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2867999747
Short name T25
Test name
Test status
Simulation time 314735734807 ps
CPU time 281.29 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:05:04 PM PDT 24
Peak memory 210176 kb
Host smart-f17cb724-5c2b-4099-9684-59014a863f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867999747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2867999747
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1904057140
Short name T532
Test name
Test status
Simulation time 486275729 ps
CPU time 1.68 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 201200 kb
Host smart-9cea3f96-c5c4-4412-8899-392c859452c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904057140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1904057140
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2155527584
Short name T534
Test name
Test status
Simulation time 171145170235 ps
CPU time 193.72 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 06:02:10 PM PDT 24
Peak memory 201696 kb
Host smart-e96aaa69-2b55-42c9-985c-b2508d1e1743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155527584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2155527584
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2072728255
Short name T480
Test name
Test status
Simulation time 168777554965 ps
CPU time 207.57 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 06:02:26 PM PDT 24
Peak memory 201480 kb
Host smart-c0ca60dc-c2b3-493a-af78-6231afae8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072728255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2072728255
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2949926368
Short name T5
Test name
Test status
Simulation time 488730881044 ps
CPU time 1145.32 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:18:25 PM PDT 24
Peak memory 201412 kb
Host smart-94aea396-77a8-4272-aeff-1358bd003914
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949926368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2949926368
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4208387293
Short name T735
Test name
Test status
Simulation time 331833180075 ps
CPU time 183.71 seconds
Started Aug 10 05:59:01 PM PDT 24
Finished Aug 10 06:02:05 PM PDT 24
Peak memory 201464 kb
Host smart-a8dbafbd-b4f1-42e6-9408-a4aa7b64b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208387293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4208387293
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2220994403
Short name T196
Test name
Test status
Simulation time 326404779928 ps
CPU time 178.32 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:02:17 PM PDT 24
Peak memory 201436 kb
Host smart-85b12531-1247-4fd7-8ec6-5296d2ab71b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220994403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2220994403
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.647538964
Short name T467
Test name
Test status
Simulation time 392466789260 ps
CPU time 233.35 seconds
Started Aug 10 05:59:10 PM PDT 24
Finished Aug 10 06:03:04 PM PDT 24
Peak memory 201420 kb
Host smart-8a4ea530-37cd-4ca2-9adc-242d986c0046
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647538964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.647538964
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.239106012
Short name T701
Test name
Test status
Simulation time 120943569526 ps
CPU time 451.41 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 06:06:25 PM PDT 24
Peak memory 201772 kb
Host smart-2452e3d9-ce44-4d5c-8e9c-307dfe41dc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239106012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.239106012
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4162861843
Short name T594
Test name
Test status
Simulation time 32019217550 ps
CPU time 22.69 seconds
Started Aug 10 05:59:11 PM PDT 24
Finished Aug 10 05:59:34 PM PDT 24
Peak memory 201344 kb
Host smart-cce3c82a-9aa6-456b-8b7d-79c38802ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162861843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4162861843
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1722537386
Short name T791
Test name
Test status
Simulation time 4646228970 ps
CPU time 6.16 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:59:00 PM PDT 24
Peak memory 201228 kb
Host smart-f0ac60ba-933b-4de0-a249-473ad18b3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722537386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1722537386
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3929010121
Short name T59
Test name
Test status
Simulation time 7860772443 ps
CPU time 18 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 05:59:20 PM PDT 24
Peak memory 218256 kb
Host smart-76398215-21e7-4253-a540-27761cf334de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929010121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3929010121
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2529388929
Short name T476
Test name
Test status
Simulation time 5968325723 ps
CPU time 6.06 seconds
Started Aug 10 05:58:59 PM PDT 24
Finished Aug 10 05:59:05 PM PDT 24
Peak memory 201392 kb
Host smart-f73100b3-4b73-41d3-a018-f7b9c8b246c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529388929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2529388929
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.17680428
Short name T28
Test name
Test status
Simulation time 82334864148 ps
CPU time 31.18 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 05:59:39 PM PDT 24
Peak memory 209788 kb
Host smart-b3730a65-d8d9-49e5-98af-35bad9d26760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680428 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.17680428
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2965869223
Short name T698
Test name
Test status
Simulation time 498781913 ps
CPU time 1.2 seconds
Started Aug 10 06:00:21 PM PDT 24
Finished Aug 10 06:00:23 PM PDT 24
Peak memory 201248 kb
Host smart-2d3b829a-e5df-4a41-8bf0-b24b846a93ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965869223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2965869223
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.258656615
Short name T589
Test name
Test status
Simulation time 181926971169 ps
CPU time 105.84 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:02:09 PM PDT 24
Peak memory 201468 kb
Host smart-906c4d65-eb5f-4a5b-a4c3-4f7b9aac0b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258656615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.258656615
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.536714929
Short name T231
Test name
Test status
Simulation time 320827298482 ps
CPU time 637.56 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 201436 kb
Host smart-ecc06832-82bb-49eb-832d-64a24e24a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536714929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.536714929
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2397910252
Short name T391
Test name
Test status
Simulation time 176721833819 ps
CPU time 425.81 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:07:29 PM PDT 24
Peak memory 201412 kb
Host smart-12963544-3f82-4bf7-9007-501a2260898b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397910252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2397910252
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3455016128
Short name T609
Test name
Test status
Simulation time 157889983363 ps
CPU time 79.72 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:01:43 PM PDT 24
Peak memory 201464 kb
Host smart-add61ce7-16b4-4920-b4c5-af6b88dcadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455016128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3455016128
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.209927310
Short name T102
Test name
Test status
Simulation time 166363129635 ps
CPU time 393.04 seconds
Started Aug 10 06:00:20 PM PDT 24
Finished Aug 10 06:06:53 PM PDT 24
Peak memory 201432 kb
Host smart-d7dd2272-816c-4929-9554-2a6c73358977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=209927310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.209927310
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1132159803
Short name T647
Test name
Test status
Simulation time 604044757266 ps
CPU time 773.52 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:13:16 PM PDT 24
Peak memory 201516 kb
Host smart-4563e066-2a7a-4a2f-aa6f-7c9075116707
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132159803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1132159803
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2795266444
Short name T3
Test name
Test status
Simulation time 94508274941 ps
CPU time 407.57 seconds
Started Aug 10 06:00:24 PM PDT 24
Finished Aug 10 06:07:12 PM PDT 24
Peak memory 201804 kb
Host smart-98bc7974-ded4-47a3-92ad-f1445583c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795266444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2795266444
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1638487133
Short name T720
Test name
Test status
Simulation time 39571014360 ps
CPU time 86.53 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:01:48 PM PDT 24
Peak memory 201356 kb
Host smart-48b9542f-e992-4429-b487-d08eb4351531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638487133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1638487133
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4210002587
Short name T622
Test name
Test status
Simulation time 5394823966 ps
CPU time 7.23 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:00:30 PM PDT 24
Peak memory 201316 kb
Host smart-a5bf2fcc-508b-442c-92e7-1f31b57bfd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210002587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4210002587
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4171955625
Short name T512
Test name
Test status
Simulation time 5742117122 ps
CPU time 4.26 seconds
Started Aug 10 06:00:22 PM PDT 24
Finished Aug 10 06:00:27 PM PDT 24
Peak memory 201348 kb
Host smart-ed6db2d4-3107-4a0c-b1a9-154045170784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171955625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4171955625
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3555371800
Short name T406
Test name
Test status
Simulation time 326460629 ps
CPU time 1.33 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:00:32 PM PDT 24
Peak memory 201264 kb
Host smart-4c1fa833-943a-42cd-b0ef-008fff8ebb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555371800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3555371800
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4024774477
Short name T579
Test name
Test status
Simulation time 162515424741 ps
CPU time 45.2 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:01:17 PM PDT 24
Peak memory 201396 kb
Host smart-0b24ee5a-b0f2-4acb-89e9-3a24d81aa9ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024774477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4024774477
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1171004372
Short name T313
Test name
Test status
Simulation time 347074858234 ps
CPU time 761.83 seconds
Started Aug 10 06:00:41 PM PDT 24
Finished Aug 10 06:13:23 PM PDT 24
Peak memory 201452 kb
Host smart-456d684b-cac1-47c3-a130-2caa96c203ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171004372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1171004372
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.702506007
Short name T669
Test name
Test status
Simulation time 506841300499 ps
CPU time 1268.16 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:21:39 PM PDT 24
Peak memory 201408 kb
Host smart-754fa457-7509-4d39-818a-c5c65fc184cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702506007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.702506007
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.577473566
Short name T449
Test name
Test status
Simulation time 330439049350 ps
CPU time 794.82 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:13:46 PM PDT 24
Peak memory 201424 kb
Host smart-5b0a3179-18c3-41e4-a416-21105593171f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=577473566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.577473566
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.449990283
Short name T233
Test name
Test status
Simulation time 490108329890 ps
CPU time 998.54 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 201428 kb
Host smart-326a5526-03da-4c72-a5f9-df048b95f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449990283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.449990283
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2906795038
Short name T717
Test name
Test status
Simulation time 164274091508 ps
CPU time 387.82 seconds
Started Aug 10 06:00:21 PM PDT 24
Finished Aug 10 06:06:49 PM PDT 24
Peak memory 201384 kb
Host smart-11e5aeeb-f90e-46c9-a926-b1278bba28f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906795038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2906795038
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2317424511
Short name T553
Test name
Test status
Simulation time 179510341004 ps
CPU time 437.04 seconds
Started Aug 10 06:00:41 PM PDT 24
Finished Aug 10 06:07:58 PM PDT 24
Peak memory 201440 kb
Host smart-fe7669ac-5830-4b70-a056-a18c1833eb8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317424511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2317424511
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1103373639
Short name T384
Test name
Test status
Simulation time 204842194514 ps
CPU time 127.71 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:02:39 PM PDT 24
Peak memory 201448 kb
Host smart-43af01ee-9ae7-4cfd-adfc-af76b14a9458
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103373639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1103373639
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2182839742
Short name T753
Test name
Test status
Simulation time 35966638184 ps
CPU time 20.31 seconds
Started Aug 10 06:00:32 PM PDT 24
Finished Aug 10 06:00:53 PM PDT 24
Peak memory 201364 kb
Host smart-74ba7c12-ee4b-4330-8863-3434fe348751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182839742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2182839742
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3684682008
Short name T351
Test name
Test status
Simulation time 3384778729 ps
CPU time 7.79 seconds
Started Aug 10 06:00:34 PM PDT 24
Finished Aug 10 06:00:41 PM PDT 24
Peak memory 201352 kb
Host smart-b79ddcad-9ccc-4554-9717-5ed03843c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684682008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3684682008
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.891566225
Short name T522
Test name
Test status
Simulation time 5973144463 ps
CPU time 13.96 seconds
Started Aug 10 06:00:23 PM PDT 24
Finished Aug 10 06:00:37 PM PDT 24
Peak memory 201396 kb
Host smart-1d461ed7-c992-4011-8961-6c1b5950aa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891566225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.891566225
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.369275583
Short name T763
Test name
Test status
Simulation time 229794647988 ps
CPU time 345.51 seconds
Started Aug 10 06:00:32 PM PDT 24
Finished Aug 10 06:06:18 PM PDT 24
Peak memory 201820 kb
Host smart-aaa35d81-6b52-44e2-a21c-e8f129722c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369275583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
369275583
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2056081350
Short name T652
Test name
Test status
Simulation time 21690719587 ps
CPU time 16.38 seconds
Started Aug 10 06:00:30 PM PDT 24
Finished Aug 10 06:00:47 PM PDT 24
Peak memory 201548 kb
Host smart-84f3a060-7a63-48c7-b8c3-ec92b7e13714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056081350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2056081350
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2432560281
Short name T382
Test name
Test status
Simulation time 462553085 ps
CPU time 1.41 seconds
Started Aug 10 06:00:39 PM PDT 24
Finished Aug 10 06:00:40 PM PDT 24
Peak memory 201408 kb
Host smart-07dd5b4f-d793-41c8-8940-aa79d103e986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432560281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2432560281
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4093214800
Short name T302
Test name
Test status
Simulation time 167240409853 ps
CPU time 370.22 seconds
Started Aug 10 06:00:41 PM PDT 24
Finished Aug 10 06:06:52 PM PDT 24
Peak memory 201460 kb
Host smart-799747bf-fe45-4845-912a-7443c6ae695a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093214800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4093214800
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.712004979
Short name T765
Test name
Test status
Simulation time 482684254886 ps
CPU time 132.45 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:02:44 PM PDT 24
Peak memory 201464 kb
Host smart-714f3830-d743-461d-995e-c56f8e89b4a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=712004979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.712004979
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2872622134
Short name T171
Test name
Test status
Simulation time 321388895980 ps
CPU time 269.57 seconds
Started Aug 10 06:00:45 PM PDT 24
Finished Aug 10 06:05:15 PM PDT 24
Peak memory 201476 kb
Host smart-fa5f18ae-2ad0-49eb-a588-57e66d486fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872622134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2872622134
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3165143233
Short name T165
Test name
Test status
Simulation time 481789469333 ps
CPU time 278.36 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:05:10 PM PDT 24
Peak memory 201428 kb
Host smart-a872bb00-c9ff-448e-9df8-cb0d1d6113e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165143233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3165143233
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2651425352
Short name T317
Test name
Test status
Simulation time 348540296337 ps
CPU time 360.34 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:06:31 PM PDT 24
Peak memory 201340 kb
Host smart-897885e7-e371-4bcc-ab52-d68b51d9dc3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651425352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2651425352
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2054327267
Short name T740
Test name
Test status
Simulation time 616047212766 ps
CPU time 1387.84 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:23:39 PM PDT 24
Peak memory 201432 kb
Host smart-f7e7caa7-f8fc-4f06-8e9c-45967943cb11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054327267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2054327267
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2068253064
Short name T695
Test name
Test status
Simulation time 111531995582 ps
CPU time 424.18 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:07:36 PM PDT 24
Peak memory 201868 kb
Host smart-a57f3aae-fd2b-4366-ae50-0d96064f8767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068253064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2068253064
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3174792323
Short name T785
Test name
Test status
Simulation time 24658289437 ps
CPU time 10.94 seconds
Started Aug 10 06:00:40 PM PDT 24
Finished Aug 10 06:00:51 PM PDT 24
Peak memory 201360 kb
Host smart-db976149-4da1-46f7-a88f-17acc5c27313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174792323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3174792323
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1578074576
Short name T777
Test name
Test status
Simulation time 4399373541 ps
CPU time 11.08 seconds
Started Aug 10 06:00:33 PM PDT 24
Finished Aug 10 06:00:44 PM PDT 24
Peak memory 201448 kb
Host smart-62c6c810-4cde-4ab6-ab22-ca8891219eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578074576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1578074576
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3911062795
Short name T513
Test name
Test status
Simulation time 6032567202 ps
CPU time 4.18 seconds
Started Aug 10 06:00:41 PM PDT 24
Finished Aug 10 06:00:45 PM PDT 24
Peak memory 201368 kb
Host smart-c660fc80-7e40-45ad-b0ee-59640f652ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911062795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3911062795
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1028693141
Short name T29
Test name
Test status
Simulation time 11146829979 ps
CPU time 27.21 seconds
Started Aug 10 06:00:39 PM PDT 24
Finished Aug 10 06:01:07 PM PDT 24
Peak memory 201360 kb
Host smart-b8946be0-2028-4a62-9f12-da7fdc8f4867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028693141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1028693141
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3871854047
Short name T448
Test name
Test status
Simulation time 272641791192 ps
CPU time 132.57 seconds
Started Aug 10 06:00:31 PM PDT 24
Finished Aug 10 06:02:44 PM PDT 24
Peak memory 209780 kb
Host smart-bb130e4f-09ca-4b5f-aee0-aa5919fcb2ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871854047 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3871854047
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2688495689
Short name T569
Test name
Test status
Simulation time 474982879 ps
CPU time 0.89 seconds
Started Aug 10 06:00:54 PM PDT 24
Finished Aug 10 06:00:55 PM PDT 24
Peak memory 201264 kb
Host smart-65e3c384-e758-4f5b-ac5f-4ebb2d15513e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688495689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2688495689
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.859560732
Short name T256
Test name
Test status
Simulation time 499215464923 ps
CPU time 933.92 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:16:28 PM PDT 24
Peak memory 201532 kb
Host smart-71fae56b-2bee-4684-a73e-3afbd527e58b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859560732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.859560732
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1990696754
Short name T445
Test name
Test status
Simulation time 161177883539 ps
CPU time 91.87 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:02:25 PM PDT 24
Peak memory 201456 kb
Host smart-13a0f9d4-6f37-4d75-8d6f-59345c9c15cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990696754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1990696754
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1792378103
Short name T110
Test name
Test status
Simulation time 486833953986 ps
CPU time 1192.14 seconds
Started Aug 10 06:00:40 PM PDT 24
Finished Aug 10 06:20:32 PM PDT 24
Peak memory 201420 kb
Host smart-d74e49e7-29d2-4cbe-9ef7-f54f22e55d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792378103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1792378103
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1332167165
Short name T377
Test name
Test status
Simulation time 335743941329 ps
CPU time 117.69 seconds
Started Aug 10 06:00:40 PM PDT 24
Finished Aug 10 06:02:38 PM PDT 24
Peak memory 201416 kb
Host smart-c46cb24b-2b01-45c2-b3d4-06587b1cfaa4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332167165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1332167165
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3924595638
Short name T509
Test name
Test status
Simulation time 158125426888 ps
CPU time 90.86 seconds
Started Aug 10 06:00:39 PM PDT 24
Finished Aug 10 06:02:10 PM PDT 24
Peak memory 201456 kb
Host smart-1b190574-d724-45af-84c4-df48762a8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924595638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3924595638
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1607097580
Short name T466
Test name
Test status
Simulation time 488650327011 ps
CPU time 288.74 seconds
Started Aug 10 06:00:39 PM PDT 24
Finished Aug 10 06:05:28 PM PDT 24
Peak memory 201424 kb
Host smart-e1b32c03-050e-403e-b5d2-94c4bfb3416b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607097580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1607097580
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3354067637
Short name T206
Test name
Test status
Simulation time 644544478310 ps
CPU time 105.79 seconds
Started Aug 10 06:00:40 PM PDT 24
Finished Aug 10 06:02:26 PM PDT 24
Peak memory 201428 kb
Host smart-9f0f9b0b-a28f-4320-b38f-42f0858bae21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354067637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3354067637
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3458368727
Short name T387
Test name
Test status
Simulation time 587136868655 ps
CPU time 657.31 seconds
Started Aug 10 06:00:40 PM PDT 24
Finished Aug 10 06:11:37 PM PDT 24
Peak memory 201464 kb
Host smart-de29d5c3-ab00-4a07-9cfe-4a7ea15da0a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458368727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3458368727
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.415148694
Short name T229
Test name
Test status
Simulation time 119957843375 ps
CPU time 444.3 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:08:18 PM PDT 24
Peak memory 201916 kb
Host smart-bd25fc7d-a4cf-4550-98b3-64c70f6379b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415148694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.415148694
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.353786634
Short name T793
Test name
Test status
Simulation time 32699154248 ps
CPU time 59.65 seconds
Started Aug 10 06:00:52 PM PDT 24
Finished Aug 10 06:01:52 PM PDT 24
Peak memory 201300 kb
Host smart-053725c2-7a3b-458f-bc41-c75bce3e7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353786634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.353786634
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2708425055
Short name T412
Test name
Test status
Simulation time 5008181716 ps
CPU time 11.58 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:01:05 PM PDT 24
Peak memory 201364 kb
Host smart-a171fa84-eed8-43d9-97c7-fe62e28ed423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708425055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2708425055
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1059888324
Short name T393
Test name
Test status
Simulation time 5882919654 ps
CPU time 2.33 seconds
Started Aug 10 06:00:39 PM PDT 24
Finished Aug 10 06:00:42 PM PDT 24
Peak memory 201316 kb
Host smart-6740749a-f7cd-47ef-a780-964983efbe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059888324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1059888324
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2111834978
Short name T465
Test name
Test status
Simulation time 203350416633 ps
CPU time 360.66 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:06:54 PM PDT 24
Peak memory 201516 kb
Host smart-cd579936-0e3c-4483-a719-e58ef276b406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111834978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2111834978
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.329567811
Short name T36
Test name
Test status
Simulation time 63478191047 ps
CPU time 126.2 seconds
Started Aug 10 06:00:55 PM PDT 24
Finished Aug 10 06:03:01 PM PDT 24
Peak memory 217448 kb
Host smart-2ddfc5df-f1bf-4751-8353-110ca7d49526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329567811 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.329567811
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.540808192
Short name T451
Test name
Test status
Simulation time 313326701 ps
CPU time 1.31 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:01:02 PM PDT 24
Peak memory 201240 kb
Host smart-b71b5a9e-a432-4e72-acf4-0fefc06ec5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540808192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.540808192
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2967857454
Short name T245
Test name
Test status
Simulation time 178699745600 ps
CPU time 203.74 seconds
Started Aug 10 06:01:03 PM PDT 24
Finished Aug 10 06:04:27 PM PDT 24
Peak memory 201420 kb
Host smart-259adcf4-6b4b-4bcb-b833-70133f519f11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967857454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2967857454
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3880778499
Short name T202
Test name
Test status
Simulation time 328735659722 ps
CPU time 206.57 seconds
Started Aug 10 06:01:03 PM PDT 24
Finished Aug 10 06:04:30 PM PDT 24
Peak memory 201460 kb
Host smart-69ab1f0e-1fdc-4576-bfd2-206936b157d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880778499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3880778499
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1799239235
Short name T176
Test name
Test status
Simulation time 331166375168 ps
CPU time 215.57 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:04:29 PM PDT 24
Peak memory 201400 kb
Host smart-c4d1d3a8-c35a-4b44-a0ad-b3c25dfdbace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799239235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1799239235
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1355022060
Short name T472
Test name
Test status
Simulation time 484816891728 ps
CPU time 1021.29 seconds
Started Aug 10 06:00:54 PM PDT 24
Finished Aug 10 06:17:55 PM PDT 24
Peak memory 201528 kb
Host smart-98cac8e4-6c25-4fc1-8a06-7887c3caf6ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355022060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1355022060
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.279072745
Short name T293
Test name
Test status
Simulation time 331209861494 ps
CPU time 733.25 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 201456 kb
Host smart-66442b0f-6b99-45c2-9851-11d2165abade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279072745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.279072745
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2468397036
Short name T454
Test name
Test status
Simulation time 327254807458 ps
CPU time 77.47 seconds
Started Aug 10 06:00:53 PM PDT 24
Finished Aug 10 06:02:10 PM PDT 24
Peak memory 201404 kb
Host smart-5ac71d7f-cbe9-46ae-84a0-b4eb6d2d53a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468397036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2468397036
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.553463891
Short name T286
Test name
Test status
Simulation time 380757759626 ps
CPU time 105.52 seconds
Started Aug 10 06:00:52 PM PDT 24
Finished Aug 10 06:02:38 PM PDT 24
Peak memory 201320 kb
Host smart-1da72994-93d9-4a66-a43a-bce276d7f4a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553463891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.553463891
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2121083018
Short name T518
Test name
Test status
Simulation time 590632842210 ps
CPU time 212.05 seconds
Started Aug 10 06:00:54 PM PDT 24
Finished Aug 10 06:04:26 PM PDT 24
Peak memory 201316 kb
Host smart-bbbfdd8e-d825-4509-a88e-765b4346bade
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121083018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2121083018
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1130608706
Short name T651
Test name
Test status
Simulation time 100176757392 ps
CPU time 316.15 seconds
Started Aug 10 06:01:03 PM PDT 24
Finished Aug 10 06:06:19 PM PDT 24
Peak memory 201840 kb
Host smart-e661aebf-7e0c-43aa-a15d-19e237d3343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130608706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1130608706
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.44543672
Short name T625
Test name
Test status
Simulation time 26633004565 ps
CPU time 57.35 seconds
Started Aug 10 06:00:59 PM PDT 24
Finished Aug 10 06:01:57 PM PDT 24
Peak memory 201356 kb
Host smart-40da6300-b009-4589-bbc3-eef41e359fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44543672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.44543672
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1195252523
Short name T413
Test name
Test status
Simulation time 4832270608 ps
CPU time 3.34 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:01:05 PM PDT 24
Peak memory 201340 kb
Host smart-80e99d4f-7181-4fa0-a8f9-6a1ab2deb58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195252523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1195252523
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2487425939
Short name T789
Test name
Test status
Simulation time 5986158185 ps
CPU time 14.46 seconds
Started Aug 10 06:00:51 PM PDT 24
Finished Aug 10 06:01:06 PM PDT 24
Peak memory 201336 kb
Host smart-0e5ba677-b5d5-4988-8e2d-8df00038c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487425939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2487425939
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1377244314
Short name T339
Test name
Test status
Simulation time 337125496192 ps
CPU time 785.45 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:14:06 PM PDT 24
Peak memory 201488 kb
Host smart-5802bb14-6254-40ca-8ead-6000b710d671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377244314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1377244314
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4292653075
Short name T23
Test name
Test status
Simulation time 19663003805 ps
CPU time 41.04 seconds
Started Aug 10 06:00:59 PM PDT 24
Finished Aug 10 06:01:41 PM PDT 24
Peak memory 209864 kb
Host smart-94299735-e2d9-42f3-9e16-70c3fa38d9ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292653075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4292653075
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3807924838
Short name T365
Test name
Test status
Simulation time 385002877 ps
CPU time 0.87 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:01:11 PM PDT 24
Peak memory 201212 kb
Host smart-f1dd07f3-fdae-4229-9df1-9d2031380291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807924838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3807924838
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.435857570
Short name T687
Test name
Test status
Simulation time 157853912181 ps
CPU time 327.96 seconds
Started Aug 10 06:01:00 PM PDT 24
Finished Aug 10 06:06:29 PM PDT 24
Peak memory 201424 kb
Host smart-990a7a42-d7d1-4789-8c3c-b5b32f7107cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435857570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.435857570
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1128352372
Short name T272
Test name
Test status
Simulation time 163269047645 ps
CPU time 333.19 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:06:35 PM PDT 24
Peak memory 201392 kb
Host smart-c0373b84-9be9-4286-940c-d043d68c7d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128352372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1128352372
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1161638032
Short name T172
Test name
Test status
Simulation time 162095300844 ps
CPU time 228.15 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:04:50 PM PDT 24
Peak memory 201476 kb
Host smart-54d6d37d-8af6-443f-8206-035a28cbca55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161638032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1161638032
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1532719518
Short name T189
Test name
Test status
Simulation time 496589903342 ps
CPU time 837.04 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:15:00 PM PDT 24
Peak memory 201484 kb
Host smart-fa2273b1-c658-4118-bba4-da550c1ef5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532719518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1532719518
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1385635052
Short name T162
Test name
Test status
Simulation time 497641326200 ps
CPU time 1102.71 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:19:24 PM PDT 24
Peak memory 201324 kb
Host smart-f848c167-6936-43ce-bd80-2a08d1661bc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385635052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1385635052
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1634027346
Short name T545
Test name
Test status
Simulation time 168277533864 ps
CPU time 72.86 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:02:14 PM PDT 24
Peak memory 201436 kb
Host smart-d07511c4-9400-4a33-8ba3-4e614b70b6ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634027346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1634027346
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.480791436
Short name T90
Test name
Test status
Simulation time 198999540198 ps
CPU time 425.28 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:08:07 PM PDT 24
Peak memory 201364 kb
Host smart-3212f6f5-1664-4b0e-bd27-796e71907ea1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480791436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.480791436
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4135540135
Short name T618
Test name
Test status
Simulation time 96351522886 ps
CPU time 403.01 seconds
Started Aug 10 06:01:01 PM PDT 24
Finished Aug 10 06:07:44 PM PDT 24
Peak memory 201836 kb
Host smart-e8376fd0-8206-417f-b952-068c88525770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135540135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4135540135
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2264558078
Short name T713
Test name
Test status
Simulation time 20797136416 ps
CPU time 10.16 seconds
Started Aug 10 06:01:03 PM PDT 24
Finished Aug 10 06:01:13 PM PDT 24
Peak memory 201328 kb
Host smart-5f2e275a-8ce3-4d7a-800d-f7af7812803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264558078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2264558078
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3250717662
Short name T621
Test name
Test status
Simulation time 4225037898 ps
CPU time 9.76 seconds
Started Aug 10 06:01:05 PM PDT 24
Finished Aug 10 06:01:15 PM PDT 24
Peak memory 201336 kb
Host smart-a6cb7c2e-41ea-4b14-a5fc-fd7277f74684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250717662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3250717662
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3280372821
Short name T409
Test name
Test status
Simulation time 5943582869 ps
CPU time 14.8 seconds
Started Aug 10 06:01:02 PM PDT 24
Finished Aug 10 06:01:17 PM PDT 24
Peak memory 201388 kb
Host smart-feda4269-79d8-40d5-a247-546e3dab1095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280372821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3280372821
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3499634715
Short name T86
Test name
Test status
Simulation time 556446570 ps
CPU time 0.81 seconds
Started Aug 10 06:01:17 PM PDT 24
Finished Aug 10 06:01:18 PM PDT 24
Peak memory 201264 kb
Host smart-f56dad9c-121b-413a-876b-15ad2e34def2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499634715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3499634715
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2984269128
Short name T528
Test name
Test status
Simulation time 508872463435 ps
CPU time 225.35 seconds
Started Aug 10 06:01:11 PM PDT 24
Finished Aug 10 06:04:56 PM PDT 24
Peak memory 201452 kb
Host smart-98cdb910-a02f-4cad-bfe9-4ab44c819981
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984269128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2984269128
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2917956327
Short name T562
Test name
Test status
Simulation time 162132533014 ps
CPU time 343.85 seconds
Started Aug 10 06:01:09 PM PDT 24
Finished Aug 10 06:06:53 PM PDT 24
Peak memory 201476 kb
Host smart-1977d20f-c018-4d49-a781-e6b4afc0c4f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917956327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2917956327
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1770114120
Short name T158
Test name
Test status
Simulation time 165481294996 ps
CPU time 383.53 seconds
Started Aug 10 06:01:09 PM PDT 24
Finished Aug 10 06:07:33 PM PDT 24
Peak memory 201400 kb
Host smart-1a7b9f9b-33f4-4a7e-8a6c-04909f7bba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770114120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1770114120
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3702948542
Short name T708
Test name
Test status
Simulation time 487026289339 ps
CPU time 567.46 seconds
Started Aug 10 06:01:09 PM PDT 24
Finished Aug 10 06:10:36 PM PDT 24
Peak memory 201428 kb
Host smart-d71ef584-c00f-4da8-8263-c183a68b43af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702948542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3702948542
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1733936495
Short name T265
Test name
Test status
Simulation time 202882232343 ps
CPU time 496.84 seconds
Started Aug 10 06:01:09 PM PDT 24
Finished Aug 10 06:09:26 PM PDT 24
Peak memory 201356 kb
Host smart-5f4d6a83-04b0-477a-b41b-9d8ba0485c55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733936495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1733936495
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1570630745
Short name T700
Test name
Test status
Simulation time 398466006869 ps
CPU time 241.49 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:05:11 PM PDT 24
Peak memory 201436 kb
Host smart-ceecc91e-f762-4af9-9c4d-3ea8792eb627
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570630745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1570630745
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2272474266
Short name T496
Test name
Test status
Simulation time 126880617650 ps
CPU time 456.67 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:08:46 PM PDT 24
Peak memory 201836 kb
Host smart-6e921204-1c87-4143-b6dd-115290857d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272474266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2272474266
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1028592174
Short name T677
Test name
Test status
Simulation time 36645424483 ps
CPU time 79.56 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:02:29 PM PDT 24
Peak memory 201356 kb
Host smart-efb2671f-0023-4706-b932-d4eeed9da2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028592174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1028592174
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3095841338
Short name T431
Test name
Test status
Simulation time 3884444520 ps
CPU time 4.35 seconds
Started Aug 10 06:01:10 PM PDT 24
Finished Aug 10 06:01:14 PM PDT 24
Peak memory 201336 kb
Host smart-3dca52a3-33c1-473e-81e5-cf4febe7113c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095841338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3095841338
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1520414518
Short name T663
Test name
Test status
Simulation time 5901873180 ps
CPU time 14.28 seconds
Started Aug 10 06:01:08 PM PDT 24
Finished Aug 10 06:01:23 PM PDT 24
Peak memory 201368 kb
Host smart-a01723bf-a129-4500-9637-f169078bcec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520414518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1520414518
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1597606205
Short name T174
Test name
Test status
Simulation time 548147657565 ps
CPU time 1226.03 seconds
Started Aug 10 06:01:20 PM PDT 24
Finished Aug 10 06:21:46 PM PDT 24
Peak memory 201428 kb
Host smart-65d0df3b-9e5e-40ef-b6c3-7dd694ae2f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597606205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1597606205
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1327811431
Short name T338
Test name
Test status
Simulation time 55075563807 ps
CPU time 136.4 seconds
Started Aug 10 06:01:17 PM PDT 24
Finished Aug 10 06:03:33 PM PDT 24
Peak memory 209844 kb
Host smart-258f1461-aa4f-4b5b-871f-be31048273ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327811431 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1327811431
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4093399805
Short name T756
Test name
Test status
Simulation time 430621979 ps
CPU time 0.75 seconds
Started Aug 10 06:01:28 PM PDT 24
Finished Aug 10 06:01:29 PM PDT 24
Peak memory 201208 kb
Host smart-32826660-4813-43f7-a724-bc0f9c1b533f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093399805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4093399805
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2306888891
Short name T275
Test name
Test status
Simulation time 158308564103 ps
CPU time 360.22 seconds
Started Aug 10 06:01:19 PM PDT 24
Finished Aug 10 06:07:19 PM PDT 24
Peak memory 201420 kb
Host smart-9f87b36c-80ec-461b-945a-a99a68a3f870
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306888891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2306888891
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2553019297
Short name T552
Test name
Test status
Simulation time 326846879530 ps
CPU time 407.38 seconds
Started Aug 10 06:01:20 PM PDT 24
Finished Aug 10 06:08:07 PM PDT 24
Peak memory 201500 kb
Host smart-d8710458-5381-485b-8096-10c9e9e557b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553019297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2553019297
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.201964882
Short name T544
Test name
Test status
Simulation time 321378313315 ps
CPU time 161.52 seconds
Started Aug 10 06:01:20 PM PDT 24
Finished Aug 10 06:04:01 PM PDT 24
Peak memory 201420 kb
Host smart-bc7ba764-cdf3-4c68-8f56-ba65ab0a1fd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=201964882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.201964882
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1642628996
Short name T739
Test name
Test status
Simulation time 160395366332 ps
CPU time 378.62 seconds
Started Aug 10 06:01:18 PM PDT 24
Finished Aug 10 06:07:36 PM PDT 24
Peak memory 201628 kb
Host smart-bac65e37-1ad8-42d9-9465-6bc068de860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642628996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1642628996
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.834219836
Short name T455
Test name
Test status
Simulation time 163946568063 ps
CPU time 375.67 seconds
Started Aug 10 06:01:20 PM PDT 24
Finished Aug 10 06:07:36 PM PDT 24
Peak memory 201428 kb
Host smart-845582f4-315a-4e95-8dfc-8b9c42061d13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=834219836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.834219836
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1056596122
Short name T368
Test name
Test status
Simulation time 601754751075 ps
CPU time 1338.12 seconds
Started Aug 10 06:01:19 PM PDT 24
Finished Aug 10 06:23:37 PM PDT 24
Peak memory 201428 kb
Host smart-ac5d6020-1827-4a1e-bcd6-6afeaad3962f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056596122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1056596122
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2512053225
Short name T538
Test name
Test status
Simulation time 63488508681 ps
CPU time 334.01 seconds
Started Aug 10 06:01:27 PM PDT 24
Finished Aug 10 06:07:01 PM PDT 24
Peak memory 202012 kb
Host smart-c3bda52c-8457-4c0a-8e11-37fc366fff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512053225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2512053225
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2759453563
Short name T506
Test name
Test status
Simulation time 28412923615 ps
CPU time 15.54 seconds
Started Aug 10 06:01:26 PM PDT 24
Finished Aug 10 06:01:41 PM PDT 24
Peak memory 201328 kb
Host smart-40113f90-1eb0-4bc7-8110-5466911bb3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759453563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2759453563
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3096967359
Short name T555
Test name
Test status
Simulation time 3913602755 ps
CPU time 2.87 seconds
Started Aug 10 06:01:27 PM PDT 24
Finished Aug 10 06:01:30 PM PDT 24
Peak memory 201296 kb
Host smart-021297c8-cc15-44c6-89be-5b9b3d528931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096967359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3096967359
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1894043878
Short name T795
Test name
Test status
Simulation time 5935882547 ps
CPU time 12.89 seconds
Started Aug 10 06:01:17 PM PDT 24
Finished Aug 10 06:01:30 PM PDT 24
Peak memory 201324 kb
Host smart-1c5448b3-0f13-4233-90f8-a680738deeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894043878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1894043878
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3830127797
Short name T264
Test name
Test status
Simulation time 350868638833 ps
CPU time 823.89 seconds
Started Aug 10 06:01:29 PM PDT 24
Finished Aug 10 06:15:13 PM PDT 24
Peak memory 201456 kb
Host smart-68cb7be4-511b-4c0e-9cd1-2f948d54ce86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830127797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3830127797
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1842308816
Short name T664
Test name
Test status
Simulation time 310904264 ps
CPU time 0.81 seconds
Started Aug 10 06:01:35 PM PDT 24
Finished Aug 10 06:01:37 PM PDT 24
Peak memory 201208 kb
Host smart-05477578-10c8-4552-8098-34c2f0f9d59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842308816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1842308816
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2659463811
Short name T154
Test name
Test status
Simulation time 494709483262 ps
CPU time 1131.37 seconds
Started Aug 10 06:01:27 PM PDT 24
Finished Aug 10 06:20:19 PM PDT 24
Peak memory 201628 kb
Host smart-d0f2547b-5d77-40ed-a6be-2863e6928d1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659463811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2659463811
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3752237073
Short name T236
Test name
Test status
Simulation time 418504047057 ps
CPU time 497.22 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:09:51 PM PDT 24
Peak memory 201488 kb
Host smart-fe66131f-f7e8-4c3e-bf81-934de3f2dbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752237073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3752237073
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.290666036
Short name T97
Test name
Test status
Simulation time 485966549324 ps
CPU time 1104.51 seconds
Started Aug 10 06:01:29 PM PDT 24
Finished Aug 10 06:19:53 PM PDT 24
Peak memory 201476 kb
Host smart-28a65852-a18c-4ab0-9b99-520382f2d25d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=290666036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.290666036
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1456431947
Short name T519
Test name
Test status
Simulation time 323511095496 ps
CPU time 700.79 seconds
Started Aug 10 06:01:25 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 201340 kb
Host smart-ec73c8d5-5451-42d4-bc8f-67ecdbebadad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456431947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1456431947
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.609562358
Short name T523
Test name
Test status
Simulation time 163158468499 ps
CPU time 391.75 seconds
Started Aug 10 06:01:26 PM PDT 24
Finished Aug 10 06:07:58 PM PDT 24
Peak memory 201436 kb
Host smart-75269d2f-34cd-42f1-acf3-a5f083814c72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=609562358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.609562358
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2019441392
Short name T584
Test name
Test status
Simulation time 405765311950 ps
CPU time 246.97 seconds
Started Aug 10 06:01:25 PM PDT 24
Finished Aug 10 06:05:32 PM PDT 24
Peak memory 201452 kb
Host smart-c3e8db51-8a71-4bae-b894-6238c31e157f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019441392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2019441392
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.94226800
Short name T228
Test name
Test status
Simulation time 90357738046 ps
CPU time 304.46 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:06:38 PM PDT 24
Peak memory 201824 kb
Host smart-fa18fbd2-6981-4611-bcfc-cdd07201e0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94226800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.94226800
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2084553767
Short name T543
Test name
Test status
Simulation time 24733355324 ps
CPU time 30.25 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:02:04 PM PDT 24
Peak memory 201244 kb
Host smart-9afef4bd-f23b-480a-8064-f907eb61decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084553767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2084553767
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.489173128
Short name T754
Test name
Test status
Simulation time 3554418937 ps
CPU time 4.76 seconds
Started Aug 10 06:01:33 PM PDT 24
Finished Aug 10 06:01:38 PM PDT 24
Peak memory 201344 kb
Host smart-0a4dc55f-ada1-4ce4-a0f3-439eac3e1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489173128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.489173128
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4059714276
Short name T132
Test name
Test status
Simulation time 6000855480 ps
CPU time 13.32 seconds
Started Aug 10 06:01:26 PM PDT 24
Finished Aug 10 06:01:40 PM PDT 24
Peak memory 201368 kb
Host smart-48d6db73-5cad-4b05-b39f-ead3dc407216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059714276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4059714276
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1053103486
Short name T225
Test name
Test status
Simulation time 305203733176 ps
CPU time 655.39 seconds
Started Aug 10 06:01:33 PM PDT 24
Finished Aug 10 06:12:29 PM PDT 24
Peak memory 211672 kb
Host smart-635ec48d-14a4-41fd-83c3-269626964370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053103486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1053103486
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.925615967
Short name T778
Test name
Test status
Simulation time 77862335836 ps
CPU time 168.15 seconds
Started Aug 10 06:01:35 PM PDT 24
Finished Aug 10 06:04:23 PM PDT 24
Peak memory 210084 kb
Host smart-28083bac-bfd2-4154-956f-b7c5bbf4f356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925615967 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.925615967
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2024922752
Short name T447
Test name
Test status
Simulation time 427438019 ps
CPU time 0.71 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:01:41 PM PDT 24
Peak memory 201264 kb
Host smart-5cdea802-6460-4b2c-9041-3f064d8199ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024922752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2024922752
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.700705340
Short name T605
Test name
Test status
Simulation time 180875635360 ps
CPU time 434.71 seconds
Started Aug 10 06:01:40 PM PDT 24
Finished Aug 10 06:08:55 PM PDT 24
Peak memory 201456 kb
Host smart-23c18283-bb7f-492f-bbd9-2ec3c9b616f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700705340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.700705340
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.564087419
Short name T748
Test name
Test status
Simulation time 164856073745 ps
CPU time 42.25 seconds
Started Aug 10 06:01:40 PM PDT 24
Finished Aug 10 06:02:22 PM PDT 24
Peak memory 201368 kb
Host smart-1e0dd9ba-c37b-4ff7-84a8-b79944490b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564087419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.564087419
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2015816321
Short name T764
Test name
Test status
Simulation time 162618656213 ps
CPU time 364.37 seconds
Started Aug 10 06:01:33 PM PDT 24
Finished Aug 10 06:07:38 PM PDT 24
Peak memory 201432 kb
Host smart-4b524720-c714-411b-bac4-df40029b4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015816321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2015816321
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2291944464
Short name T502
Test name
Test status
Simulation time 492581111117 ps
CPU time 72.12 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:02:47 PM PDT 24
Peak memory 201444 kb
Host smart-170a4eb7-510d-44a6-b3b3-be92bb535071
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291944464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2291944464
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3855579478
Short name T546
Test name
Test status
Simulation time 333581332368 ps
CPU time 197.78 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:04:52 PM PDT 24
Peak memory 201424 kb
Host smart-c999ba56-33a3-4d54-8468-eea9caaf95cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855579478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3855579478
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3021765438
Short name T383
Test name
Test status
Simulation time 332086673409 ps
CPU time 714.72 seconds
Started Aug 10 06:01:34 PM PDT 24
Finished Aug 10 06:13:29 PM PDT 24
Peak memory 201344 kb
Host smart-11a05c0e-b3ee-46f9-8b77-e89d68a4b1cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021765438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3021765438
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2143788671
Short name T759
Test name
Test status
Simulation time 254096162392 ps
CPU time 305.01 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:06:46 PM PDT 24
Peak memory 201412 kb
Host smart-a3e5e95c-1071-41db-8701-3b3267fa5492
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143788671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2143788671
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.550224247
Short name T633
Test name
Test status
Simulation time 392434363904 ps
CPU time 952.3 seconds
Started Aug 10 06:01:43 PM PDT 24
Finished Aug 10 06:17:36 PM PDT 24
Peak memory 201400 kb
Host smart-e2bed348-bda9-4c66-ad11-e99d4b2eacc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550224247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.550224247
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1606123823
Short name T638
Test name
Test status
Simulation time 112879893003 ps
CPU time 397.23 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:08:19 PM PDT 24
Peak memory 201804 kb
Host smart-d22cce63-38cf-45e1-a611-5b666e43104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606123823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1606123823
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.855881911
Short name T142
Test name
Test status
Simulation time 36763027539 ps
CPU time 9.96 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:01:51 PM PDT 24
Peak memory 201340 kb
Host smart-43c78d66-276e-453d-b9ef-99e7a076bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855881911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.855881911
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2550203718
Short name T602
Test name
Test status
Simulation time 3952811920 ps
CPU time 8.46 seconds
Started Aug 10 06:01:43 PM PDT 24
Finished Aug 10 06:01:51 PM PDT 24
Peak memory 201312 kb
Host smart-b8e7db3a-4791-4c55-9858-960cf8fee535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550203718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2550203718
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.377368957
Short name T474
Test name
Test status
Simulation time 5938744703 ps
CPU time 4.27 seconds
Started Aug 10 06:01:33 PM PDT 24
Finished Aug 10 06:01:38 PM PDT 24
Peak memory 201316 kb
Host smart-ba9cb511-b02e-4371-b76b-4cf136cf8ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377368957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.377368957
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.480634798
Short name T315
Test name
Test status
Simulation time 594708673302 ps
CPU time 1400.78 seconds
Started Aug 10 06:01:42 PM PDT 24
Finished Aug 10 06:25:03 PM PDT 24
Peak memory 201448 kb
Host smart-619295e9-268a-42b3-95c7-03bf54adadd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480634798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
480634798
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.597170121
Short name T335
Test name
Test status
Simulation time 37479203765 ps
CPU time 79.85 seconds
Started Aug 10 06:01:42 PM PDT 24
Finished Aug 10 06:03:02 PM PDT 24
Peak memory 209748 kb
Host smart-6eb13545-2554-48ed-b647-e4d76c7bf005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597170121 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.597170121
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1300154558
Short name T730
Test name
Test status
Simulation time 454619044 ps
CPU time 1.1 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 05:59:09 PM PDT 24
Peak memory 201260 kb
Host smart-9279be15-e417-4548-aabb-4fab2ced5ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300154558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1300154558
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.578956703
Short name T207
Test name
Test status
Simulation time 334393467972 ps
CPU time 198.41 seconds
Started Aug 10 05:59:15 PM PDT 24
Finished Aug 10 06:02:34 PM PDT 24
Peak memory 201436 kb
Host smart-01133ac4-94b9-402c-955c-c2d475d84161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578956703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.578956703
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1435196050
Short name T157
Test name
Test status
Simulation time 205232354290 ps
CPU time 453.85 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 06:06:34 PM PDT 24
Peak memory 201376 kb
Host smart-28086052-b684-4090-9e9a-3b1a42e157a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435196050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1435196050
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1085565658
Short name T273
Test name
Test status
Simulation time 164621659657 ps
CPU time 360.2 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 06:05:14 PM PDT 24
Peak memory 201336 kb
Host smart-060eed5b-105c-403b-b6df-d3dab34a3c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085565658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1085565658
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.943981413
Short name T440
Test name
Test status
Simulation time 331125009763 ps
CPU time 781.59 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 201516 kb
Host smart-18f71466-1a52-4f2d-a45a-cac420590891
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943981413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.943981413
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2688096565
Short name T192
Test name
Test status
Simulation time 486527645978 ps
CPU time 1031.09 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:16:27 PM PDT 24
Peak memory 201388 kb
Host smart-e923d83e-ff43-44f0-a95e-81abe44765da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688096565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2688096565
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3465611781
Short name T419
Test name
Test status
Simulation time 489732914604 ps
CPU time 1050.35 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 201436 kb
Host smart-4659cfbd-b0cf-4370-9a07-9d7a6b9ea371
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465611781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3465611781
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.541854113
Short name T200
Test name
Test status
Simulation time 538377123067 ps
CPU time 143.26 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:01:27 PM PDT 24
Peak memory 201448 kb
Host smart-443f3ad0-0524-4599-b0dd-9cd364a92184
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541854113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.541854113
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.709823381
Short name T563
Test name
Test status
Simulation time 417838020790 ps
CPU time 234.45 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:02:57 PM PDT 24
Peak memory 201528 kb
Host smart-62ef46be-a4f6-44fa-b7e7-464f4fe30766
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709823381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.709823381
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1580331376
Short name T46
Test name
Test status
Simulation time 85712195049 ps
CPU time 323.07 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:04:40 PM PDT 24
Peak memory 201804 kb
Host smart-9c1dad0a-4bda-4678-adb9-79f18f04ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580331376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1580331376
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1937488426
Short name T490
Test name
Test status
Simulation time 29427471686 ps
CPU time 68.89 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:00:25 PM PDT 24
Peak memory 201368 kb
Host smart-e3018f15-22eb-4f03-9919-fbb9f31a7792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937488426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1937488426
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2262653386
Short name T731
Test name
Test status
Simulation time 4229173716 ps
CPU time 11.36 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 05:59:13 PM PDT 24
Peak memory 201528 kb
Host smart-5917ff00-b96d-4f8c-ab9c-a1f85b97d144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262653386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2262653386
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1980166969
Short name T73
Test name
Test status
Simulation time 7886229744 ps
CPU time 5.33 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 05:59:20 PM PDT 24
Peak memory 218228 kb
Host smart-52cc8e73-310e-45a2-bede-453b590cce88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980166969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1980166969
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1268180623
Short name T88
Test name
Test status
Simulation time 5697832643 ps
CPU time 8.4 seconds
Started Aug 10 05:58:59 PM PDT 24
Finished Aug 10 05:59:08 PM PDT 24
Peak memory 201384 kb
Host smart-e4145e1c-698a-42e5-a35d-49909aa1c5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268180623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1268180623
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.492528178
Short name T577
Test name
Test status
Simulation time 152780043741 ps
CPU time 776.73 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 201828 kb
Host smart-510b003d-9cc2-4902-90ba-bd2f27e4514e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492528178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.492528178
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3936440305
Short name T489
Test name
Test status
Simulation time 207663714867 ps
CPU time 152.79 seconds
Started Aug 10 05:59:06 PM PDT 24
Finished Aug 10 06:01:39 PM PDT 24
Peak memory 210536 kb
Host smart-6fede3f3-df4b-4348-ae27-8a2e2adb0667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936440305 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3936440305
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3662047323
Short name T15
Test name
Test status
Simulation time 427003857 ps
CPU time 0.83 seconds
Started Aug 10 06:01:52 PM PDT 24
Finished Aug 10 06:01:53 PM PDT 24
Peak memory 201212 kb
Host smart-b84e4827-68ec-41d2-b30e-856b77351979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662047323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3662047323
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1302282019
Short name T51
Test name
Test status
Simulation time 170365245901 ps
CPU time 80.26 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:03:11 PM PDT 24
Peak memory 201452 kb
Host smart-040231fb-c295-4876-a4c7-eceb724891a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302282019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1302282019
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2355963348
Short name T327
Test name
Test status
Simulation time 334565925528 ps
CPU time 419.37 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:08:49 PM PDT 24
Peak memory 201452 kb
Host smart-c601f32e-a359-44a2-b01c-1cf570a20042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355963348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2355963348
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.879078415
Short name T248
Test name
Test status
Simulation time 158437398555 ps
CPU time 194.09 seconds
Started Aug 10 06:01:42 PM PDT 24
Finished Aug 10 06:04:56 PM PDT 24
Peak memory 201452 kb
Host smart-562e1452-1d8b-4355-a9b9-d1722ef2ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879078415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.879078415
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1007885684
Short name T658
Test name
Test status
Simulation time 323824844559 ps
CPU time 794.75 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:15:05 PM PDT 24
Peak memory 201616 kb
Host smart-e5aafeb4-f1dd-4aca-8fda-c6b111b399fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007885684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1007885684
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1847710309
Short name T423
Test name
Test status
Simulation time 330907257198 ps
CPU time 97.58 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:03:18 PM PDT 24
Peak memory 201356 kb
Host smart-72aae3ba-0cc0-4b25-9c96-31d48c66c666
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847710309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1847710309
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3094626395
Short name T280
Test name
Test status
Simulation time 365188333592 ps
CPU time 199.87 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:05:10 PM PDT 24
Peak memory 201460 kb
Host smart-11c8b89a-1c24-430a-a197-63e8529857b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094626395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3094626395
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.656677116
Short name T111
Test name
Test status
Simulation time 390879718854 ps
CPU time 78.95 seconds
Started Aug 10 06:01:57 PM PDT 24
Finished Aug 10 06:03:16 PM PDT 24
Peak memory 201432 kb
Host smart-6d966de3-5a45-4a77-90b7-df7a9bf1fc43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656677116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.656677116
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3237640825
Short name T588
Test name
Test status
Simulation time 114254006747 ps
CPU time 607.7 seconds
Started Aug 10 06:01:52 PM PDT 24
Finished Aug 10 06:12:00 PM PDT 24
Peak memory 201824 kb
Host smart-ad897cd3-f9d1-4048-8125-2c753025fb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237640825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3237640825
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2100691619
Short name T613
Test name
Test status
Simulation time 27411415271 ps
CPU time 58.29 seconds
Started Aug 10 06:01:49 PM PDT 24
Finished Aug 10 06:02:47 PM PDT 24
Peak memory 201384 kb
Host smart-5e301990-218d-4290-aec8-d3c4e62c17c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100691619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2100691619
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3941298437
Short name T400
Test name
Test status
Simulation time 3625197392 ps
CPU time 2 seconds
Started Aug 10 06:01:59 PM PDT 24
Finished Aug 10 06:02:01 PM PDT 24
Peak memory 201360 kb
Host smart-1710597f-f145-463e-b943-10f5a1724841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941298437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3941298437
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2933334447
Short name T363
Test name
Test status
Simulation time 5802697994 ps
CPU time 4.34 seconds
Started Aug 10 06:01:41 PM PDT 24
Finished Aug 10 06:01:46 PM PDT 24
Peak memory 201336 kb
Host smart-03fed83b-d102-4bb2-9c86-6a3a31a99c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933334447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2933334447
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1451567512
Short name T224
Test name
Test status
Simulation time 466419530849 ps
CPU time 627.85 seconds
Started Aug 10 06:01:51 PM PDT 24
Finished Aug 10 06:12:19 PM PDT 24
Peak memory 210016 kb
Host smart-dd4de842-ecf1-4f4a-9583-8869685cb87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451567512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1451567512
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2882058094
Short name T653
Test name
Test status
Simulation time 387010917883 ps
CPU time 365.43 seconds
Started Aug 10 06:01:51 PM PDT 24
Finished Aug 10 06:07:56 PM PDT 24
Peak memory 217656 kb
Host smart-a7505fe1-471a-43f6-9a80-227525567a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882058094 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2882058094
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3081518256
Short name T564
Test name
Test status
Simulation time 406958331 ps
CPU time 0.81 seconds
Started Aug 10 06:01:58 PM PDT 24
Finished Aug 10 06:01:58 PM PDT 24
Peak memory 201244 kb
Host smart-24859a39-1d00-40de-9e84-1d46cc81d7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081518256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3081518256
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1713225463
Short name T278
Test name
Test status
Simulation time 164457034676 ps
CPU time 367.26 seconds
Started Aug 10 06:02:02 PM PDT 24
Finished Aug 10 06:08:09 PM PDT 24
Peak memory 201548 kb
Host smart-8562e89d-2edf-4bfc-9f1f-8f899871a6fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713225463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1713225463
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2928205606
Short name T749
Test name
Test status
Simulation time 173374804648 ps
CPU time 43.76 seconds
Started Aug 10 06:01:58 PM PDT 24
Finished Aug 10 06:02:42 PM PDT 24
Peak memory 201452 kb
Host smart-8562dffe-7ffb-482c-b2b7-d59b9494820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928205606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2928205606
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2686578503
Short name T87
Test name
Test status
Simulation time 322214482077 ps
CPU time 776.36 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:14:47 PM PDT 24
Peak memory 201412 kb
Host smart-ffe93025-2ab7-4c95-b066-fc1125409a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686578503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2686578503
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1279545555
Short name T768
Test name
Test status
Simulation time 332856073626 ps
CPU time 413.94 seconds
Started Aug 10 06:02:00 PM PDT 24
Finished Aug 10 06:08:54 PM PDT 24
Peak memory 201508 kb
Host smart-982705f6-b4d9-4d00-ae26-b6c09b6f65c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279545555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1279545555
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2071196994
Short name T710
Test name
Test status
Simulation time 324761708350 ps
CPU time 371.36 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:08:01 PM PDT 24
Peak memory 201440 kb
Host smart-d3be3ffb-f63b-4e94-8cfb-c6d8a839872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071196994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2071196994
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3873852024
Short name T357
Test name
Test status
Simulation time 333770907783 ps
CPU time 736.65 seconds
Started Aug 10 06:01:50 PM PDT 24
Finished Aug 10 06:14:07 PM PDT 24
Peak memory 201436 kb
Host smart-bdcc852e-bd52-479a-b0ea-61bb46ae231b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873852024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3873852024
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1679594081
Short name T79
Test name
Test status
Simulation time 551955268690 ps
CPU time 1264.67 seconds
Started Aug 10 06:02:00 PM PDT 24
Finished Aug 10 06:23:05 PM PDT 24
Peak memory 201416 kb
Host smart-b713613c-6930-4983-9751-d51d06f93716
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679594081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1679594081
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3190514913
Short name T381
Test name
Test status
Simulation time 198342528084 ps
CPU time 76.28 seconds
Started Aug 10 06:01:59 PM PDT 24
Finished Aug 10 06:03:16 PM PDT 24
Peak memory 201616 kb
Host smart-d0eac685-ca15-4ddc-817d-0e82287cd137
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190514913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3190514913
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3576568860
Short name T218
Test name
Test status
Simulation time 88600906342 ps
CPU time 229.94 seconds
Started Aug 10 06:01:58 PM PDT 24
Finished Aug 10 06:05:48 PM PDT 24
Peak memory 201796 kb
Host smart-8b7a8358-a037-4c3e-a5e6-edf8d8d4d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576568860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3576568860
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3988743999
Short name T557
Test name
Test status
Simulation time 29198333699 ps
CPU time 68.02 seconds
Started Aug 10 06:01:59 PM PDT 24
Finished Aug 10 06:03:07 PM PDT 24
Peak memory 201328 kb
Host smart-eba75134-0acd-49e2-9264-4e13299db0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988743999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3988743999
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3317618851
Short name T8
Test name
Test status
Simulation time 3988739168 ps
CPU time 5.7 seconds
Started Aug 10 06:02:03 PM PDT 24
Finished Aug 10 06:02:08 PM PDT 24
Peak memory 201308 kb
Host smart-606721ae-3918-4b50-b4e0-9a27bc577d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317618851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3317618851
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2646873811
Short name T370
Test name
Test status
Simulation time 5573925669 ps
CPU time 2.35 seconds
Started Aug 10 06:01:52 PM PDT 24
Finished Aug 10 06:01:55 PM PDT 24
Peak memory 201324 kb
Host smart-a4a55669-d575-4f9a-93f7-5eb15ad881ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646873811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2646873811
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1939266361
Short name T85
Test name
Test status
Simulation time 337385411725 ps
CPU time 496.6 seconds
Started Aug 10 06:01:57 PM PDT 24
Finished Aug 10 06:10:14 PM PDT 24
Peak memory 209964 kb
Host smart-46b67505-c20e-441c-a287-4b410f74a424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939266361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1939266361
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1024332440
Short name T516
Test name
Test status
Simulation time 395834409 ps
CPU time 1.26 seconds
Started Aug 10 06:02:05 PM PDT 24
Finished Aug 10 06:02:07 PM PDT 24
Peak memory 201220 kb
Host smart-b5011988-eaaa-483a-9a43-7cb3674b0ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024332440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1024332440
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.46601150
Short name T169
Test name
Test status
Simulation time 173086848281 ps
CPU time 187.88 seconds
Started Aug 10 06:02:00 PM PDT 24
Finished Aug 10 06:05:08 PM PDT 24
Peak memory 201488 kb
Host smart-76126b63-9fb8-4ce1-87b0-e9438afecb71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46601150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gatin
g.46601150
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1740366392
Short name T277
Test name
Test status
Simulation time 341593776367 ps
CPU time 743.77 seconds
Started Aug 10 06:02:07 PM PDT 24
Finished Aug 10 06:14:31 PM PDT 24
Peak memory 201512 kb
Host smart-a38df5f8-7513-41b3-94e3-6bf6ead7efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740366392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1740366392
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2142211254
Short name T145
Test name
Test status
Simulation time 162527896560 ps
CPU time 96.49 seconds
Started Aug 10 06:02:02 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 201520 kb
Host smart-066f8c30-dbff-4009-818c-25029b813426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142211254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2142211254
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2084676276
Short name T683
Test name
Test status
Simulation time 162911792126 ps
CPU time 40.67 seconds
Started Aug 10 06:02:00 PM PDT 24
Finished Aug 10 06:02:40 PM PDT 24
Peak memory 201468 kb
Host smart-8ad9dc5a-d838-4d07-8ca4-891c4ba3c7c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084676276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2084676276
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1392639314
Short name T27
Test name
Test status
Simulation time 325847270237 ps
CPU time 370 seconds
Started Aug 10 06:02:02 PM PDT 24
Finished Aug 10 06:08:12 PM PDT 24
Peak memory 201460 kb
Host smart-46b2faf5-c3e5-4c9f-92e6-76ade2fc3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392639314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1392639314
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2870891227
Short name T436
Test name
Test status
Simulation time 497966585426 ps
CPU time 1090.55 seconds
Started Aug 10 06:01:58 PM PDT 24
Finished Aug 10 06:20:09 PM PDT 24
Peak memory 201428 kb
Host smart-36d001ec-4c4f-46a9-bab1-e0a0a800ce38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870891227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2870891227
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1087428387
Short name T491
Test name
Test status
Simulation time 204388897268 ps
CPU time 113.41 seconds
Started Aug 10 06:01:59 PM PDT 24
Finished Aug 10 06:03:52 PM PDT 24
Peak memory 201436 kb
Host smart-3106668c-fe3a-49d1-8707-db429d74d178
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087428387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1087428387
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.926580940
Short name T369
Test name
Test status
Simulation time 200350036196 ps
CPU time 236.8 seconds
Started Aug 10 06:02:02 PM PDT 24
Finished Aug 10 06:05:58 PM PDT 24
Peak memory 201464 kb
Host smart-99309b0e-ab6f-41a8-87b1-b5a4afc1f552
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926580940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.926580940
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1800061913
Short name T396
Test name
Test status
Simulation time 100455457434 ps
CPU time 279.5 seconds
Started Aug 10 06:02:04 PM PDT 24
Finished Aug 10 06:06:43 PM PDT 24
Peak memory 201792 kb
Host smart-d503c8aa-740d-452d-af63-8cc2b0123539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800061913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1800061913
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1537244903
Short name T623
Test name
Test status
Simulation time 24018800809 ps
CPU time 25.78 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:02:32 PM PDT 24
Peak memory 201352 kb
Host smart-28ad29aa-fcf1-4d98-a7fa-be9e98459135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537244903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1537244903
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.657182857
Short name T568
Test name
Test status
Simulation time 3119084923 ps
CPU time 2.1 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:02:08 PM PDT 24
Peak memory 201364 kb
Host smart-761a84b6-106f-4cfc-8b18-ec369e1ebbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657182857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.657182857
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.348129123
Short name T646
Test name
Test status
Simulation time 6019890665 ps
CPU time 14.34 seconds
Started Aug 10 06:02:00 PM PDT 24
Finished Aug 10 06:02:15 PM PDT 24
Peak memory 201332 kb
Host smart-01e7d48c-462d-45e6-8c12-6d720cdac0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348129123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.348129123
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1762391537
Short name T719
Test name
Test status
Simulation time 162330492065 ps
CPU time 136.28 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:04:22 PM PDT 24
Peak memory 201396 kb
Host smart-d50a056f-73fb-45ba-9b9f-e6612f833a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762391537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1762391537
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3849123231
Short name T301
Test name
Test status
Simulation time 1177738976512 ps
CPU time 268.86 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:06:35 PM PDT 24
Peak memory 210188 kb
Host smart-1197f9d7-b18d-45c2-aad3-7e3637e5932a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849123231 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3849123231
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3250370005
Short name T4
Test name
Test status
Simulation time 318092824 ps
CPU time 0.79 seconds
Started Aug 10 06:02:13 PM PDT 24
Finished Aug 10 06:02:14 PM PDT 24
Peak memory 201260 kb
Host smart-4cfa6a32-2a15-458e-afeb-7010f2e591a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250370005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3250370005
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1697231966
Short name T746
Test name
Test status
Simulation time 191691695340 ps
CPU time 69.78 seconds
Started Aug 10 06:02:15 PM PDT 24
Finished Aug 10 06:03:24 PM PDT 24
Peak memory 201460 kb
Host smart-c980e5a6-7c28-4b3c-8ea4-39b8b3d9400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697231966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1697231966
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.440695947
Short name T426
Test name
Test status
Simulation time 168561320218 ps
CPU time 59.35 seconds
Started Aug 10 06:02:05 PM PDT 24
Finished Aug 10 06:03:05 PM PDT 24
Peak memory 201492 kb
Host smart-c2f6df57-0800-4f35-99fb-f2a1d7bf13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440695947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.440695947
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2437068011
Short name T464
Test name
Test status
Simulation time 327987540349 ps
CPU time 771.2 seconds
Started Aug 10 06:02:05 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 201464 kb
Host smart-352cac92-16c3-40ce-85e1-999667007a14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437068011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2437068011
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1456990024
Short name T697
Test name
Test status
Simulation time 165409140056 ps
CPU time 355.65 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:08:02 PM PDT 24
Peak memory 201484 kb
Host smart-2fa60ff7-82b6-45d1-bad9-ff74642ad98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456990024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1456990024
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1727089620
Short name T586
Test name
Test status
Simulation time 334262756814 ps
CPU time 174.13 seconds
Started Aug 10 06:02:08 PM PDT 24
Finished Aug 10 06:05:02 PM PDT 24
Peak memory 201440 kb
Host smart-cf5b9445-31ce-4985-826d-85322645822f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727089620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1727089620
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2002190583
Short name T571
Test name
Test status
Simulation time 181386281795 ps
CPU time 39.29 seconds
Started Aug 10 06:02:06 PM PDT 24
Finished Aug 10 06:02:45 PM PDT 24
Peak memory 201396 kb
Host smart-cb5f8fc7-12e3-4f60-90f2-012213a71248
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002190583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2002190583
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1113165817
Short name T388
Test name
Test status
Simulation time 602236844589 ps
CPU time 1367.37 seconds
Started Aug 10 06:02:15 PM PDT 24
Finished Aug 10 06:25:03 PM PDT 24
Peak memory 201400 kb
Host smart-c7871352-fea1-4125-bcbd-df3398e6d0a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113165817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1113165817
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2893719776
Short name T221
Test name
Test status
Simulation time 105097892830 ps
CPU time 454.25 seconds
Started Aug 10 06:02:16 PM PDT 24
Finished Aug 10 06:09:51 PM PDT 24
Peak memory 201812 kb
Host smart-8c11969d-ad89-4e10-95ef-9946952a7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893719776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2893719776
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3314502416
Short name T648
Test name
Test status
Simulation time 28874348095 ps
CPU time 42.66 seconds
Started Aug 10 06:02:15 PM PDT 24
Finished Aug 10 06:02:57 PM PDT 24
Peak memory 201348 kb
Host smart-133f22b8-a5a8-4836-90dd-3de56d4d401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314502416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3314502416
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2106229984
Short name T463
Test name
Test status
Simulation time 4329266425 ps
CPU time 5.63 seconds
Started Aug 10 06:02:15 PM PDT 24
Finished Aug 10 06:02:21 PM PDT 24
Peak memory 201304 kb
Host smart-ae32aa58-2435-400c-b8ef-33f24e7c5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106229984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2106229984
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.214477866
Short name T428
Test name
Test status
Simulation time 5572508253 ps
CPU time 12.39 seconds
Started Aug 10 06:02:07 PM PDT 24
Finished Aug 10 06:02:19 PM PDT 24
Peak memory 201380 kb
Host smart-29897ae5-ef6d-4613-9f77-0c1f4f53035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214477866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.214477866
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2388788877
Short name T462
Test name
Test status
Simulation time 200721870910 ps
CPU time 439.54 seconds
Started Aug 10 06:02:16 PM PDT 24
Finished Aug 10 06:09:35 PM PDT 24
Peak memory 201408 kb
Host smart-772feb74-f3df-4713-ae18-f22d0cc98823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388788877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2388788877
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1577511840
Short name T312
Test name
Test status
Simulation time 38929775610 ps
CPU time 17.55 seconds
Started Aug 10 06:02:16 PM PDT 24
Finished Aug 10 06:02:34 PM PDT 24
Peak memory 209824 kb
Host smart-69b5002c-b214-41a2-858c-b23a2e2512a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577511840 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1577511840
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.399291567
Short name T672
Test name
Test status
Simulation time 525844371 ps
CPU time 0.75 seconds
Started Aug 10 06:02:30 PM PDT 24
Finished Aug 10 06:02:31 PM PDT 24
Peak memory 201200 kb
Host smart-212bcf4f-d8e0-4366-9fc7-dee93ff63a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399291567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.399291567
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3538936697
Short name T244
Test name
Test status
Simulation time 189902976617 ps
CPU time 107.6 seconds
Started Aug 10 06:02:22 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 201448 kb
Host smart-85af4d8b-ac0f-488f-a5df-81c7c32b3c5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538936697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3538936697
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3577177491
Short name T284
Test name
Test status
Simulation time 523424555966 ps
CPU time 585.35 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:12:08 PM PDT 24
Peak memory 201520 kb
Host smart-04da733d-fcf0-4cba-9c69-7e19d2a72fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577177491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3577177491
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1913870981
Short name T711
Test name
Test status
Simulation time 326691306775 ps
CPU time 385.8 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:08:49 PM PDT 24
Peak memory 201480 kb
Host smart-8e0d59bb-8c5e-4dff-ac2a-bccef10b2a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913870981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1913870981
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.408148518
Short name T642
Test name
Test status
Simulation time 483451870553 ps
CPU time 1070.34 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 201468 kb
Host smart-56dbf973-0bb5-40c2-843d-455c4a677d4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408148518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.408148518
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1288653385
Short name T290
Test name
Test status
Simulation time 331921207571 ps
CPU time 179.31 seconds
Started Aug 10 06:02:14 PM PDT 24
Finished Aug 10 06:05:14 PM PDT 24
Peak memory 201448 kb
Host smart-f5a71b85-c567-4066-ad27-e1eb912a4ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288653385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1288653385
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3137445703
Short name T394
Test name
Test status
Simulation time 161488217316 ps
CPU time 93.23 seconds
Started Aug 10 06:02:15 PM PDT 24
Finished Aug 10 06:03:48 PM PDT 24
Peak memory 201460 kb
Host smart-3e3e76af-316c-4ebb-a86e-67ed1f0a8a74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137445703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3137445703
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3802786373
Short name T375
Test name
Test status
Simulation time 612493194569 ps
CPU time 668.91 seconds
Started Aug 10 06:02:25 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 201460 kb
Host smart-44c149ca-8f74-4269-bed1-d77e512946c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802786373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3802786373
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2561565431
Short name T526
Test name
Test status
Simulation time 113707068091 ps
CPU time 384.95 seconds
Started Aug 10 06:02:22 PM PDT 24
Finished Aug 10 06:08:47 PM PDT 24
Peak memory 201800 kb
Host smart-51778870-d7d5-4ec1-a9a7-43c7de43773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561565431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2561565431
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3452837726
Short name T460
Test name
Test status
Simulation time 37465885648 ps
CPU time 41.13 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:03:04 PM PDT 24
Peak memory 201316 kb
Host smart-1e41c15d-ae30-4734-8658-e196849ce185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452837726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3452837726
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.906296541
Short name T745
Test name
Test status
Simulation time 3064635044 ps
CPU time 2.52 seconds
Started Aug 10 06:02:23 PM PDT 24
Finished Aug 10 06:02:25 PM PDT 24
Peak memory 201328 kb
Host smart-7a4dc1d2-3f10-4e8a-b009-8e1dccce08de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906296541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.906296541
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2808485689
Short name T686
Test name
Test status
Simulation time 6139548765 ps
CPU time 4.96 seconds
Started Aug 10 06:02:16 PM PDT 24
Finished Aug 10 06:02:21 PM PDT 24
Peak memory 201380 kb
Host smart-136d0fbe-63ca-47ea-9f7a-686fb152e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808485689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2808485689
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2792125054
Short name T31
Test name
Test status
Simulation time 186634603170 ps
CPU time 952.52 seconds
Started Aug 10 06:02:22 PM PDT 24
Finished Aug 10 06:18:15 PM PDT 24
Peak memory 201872 kb
Host smart-cb762391-9ce7-48f5-ac06-e609f126e971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792125054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2792125054
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3834417816
Short name T598
Test name
Test status
Simulation time 96617931905 ps
CPU time 56.21 seconds
Started Aug 10 06:02:24 PM PDT 24
Finished Aug 10 06:03:21 PM PDT 24
Peak memory 201560 kb
Host smart-0736ff9b-0617-4e37-8e02-d43f474f7ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834417816 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3834417816
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3665388992
Short name T422
Test name
Test status
Simulation time 300193493 ps
CPU time 1.3 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:02:41 PM PDT 24
Peak memory 201252 kb
Host smart-cfa69e35-082b-405b-ab79-77b35da8649f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665388992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3665388992
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1929178434
Short name T194
Test name
Test status
Simulation time 510643394199 ps
CPU time 114.3 seconds
Started Aug 10 06:02:30 PM PDT 24
Finished Aug 10 06:04:25 PM PDT 24
Peak memory 201448 kb
Host smart-6f27800f-f574-4652-bf3b-b0bc2bd31d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929178434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1929178434
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.192114788
Short name T500
Test name
Test status
Simulation time 172371181619 ps
CPU time 99.98 seconds
Started Aug 10 06:02:31 PM PDT 24
Finished Aug 10 06:04:11 PM PDT 24
Peak memory 201440 kb
Host smart-c6a09acd-6a1e-44a3-a035-57f7e38b60a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192114788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.192114788
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.991816321
Short name T83
Test name
Test status
Simulation time 320273230641 ps
CPU time 759.62 seconds
Started Aug 10 06:02:31 PM PDT 24
Finished Aug 10 06:15:11 PM PDT 24
Peak memory 201316 kb
Host smart-84d6ee9c-7346-4684-aa57-76dea751b6ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=991816321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.991816321
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3366630999
Short name T259
Test name
Test status
Simulation time 163979300419 ps
CPU time 191.25 seconds
Started Aug 10 06:02:32 PM PDT 24
Finished Aug 10 06:05:43 PM PDT 24
Peak memory 201444 kb
Host smart-1c66640e-3a9d-494a-b68a-9538e9555253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366630999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3366630999
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1137998993
Short name T784
Test name
Test status
Simulation time 496456337739 ps
CPU time 1004.48 seconds
Started Aug 10 06:02:32 PM PDT 24
Finished Aug 10 06:19:17 PM PDT 24
Peak memory 201396 kb
Host smart-b0aa493c-e5e2-448a-8219-99559076df75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137998993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1137998993
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.777804250
Short name T239
Test name
Test status
Simulation time 393321037616 ps
CPU time 648.81 seconds
Started Aug 10 06:02:32 PM PDT 24
Finished Aug 10 06:13:21 PM PDT 24
Peak memory 201460 kb
Host smart-954a16c7-605a-43b6-ab01-ca585c6de9bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777804250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.777804250
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2727738883
Short name T362
Test name
Test status
Simulation time 394943085254 ps
CPU time 866.58 seconds
Started Aug 10 06:02:31 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 201432 kb
Host smart-63747569-4cf6-419b-928a-16f001e6fcf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727738883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2727738883
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3505225763
Short name T222
Test name
Test status
Simulation time 123483458887 ps
CPU time 441.22 seconds
Started Aug 10 06:02:34 PM PDT 24
Finished Aug 10 06:09:55 PM PDT 24
Peak memory 201720 kb
Host smart-2c5c3407-247e-43c3-a037-a25e4c930f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505225763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3505225763
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.660843806
Short name T366
Test name
Test status
Simulation time 46448661465 ps
CPU time 10.13 seconds
Started Aug 10 06:02:31 PM PDT 24
Finished Aug 10 06:02:42 PM PDT 24
Peak memory 201308 kb
Host smart-4f56b568-c61b-49bd-86a4-2c3c70677cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660843806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.660843806
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2291842425
Short name T550
Test name
Test status
Simulation time 3450698502 ps
CPU time 5.44 seconds
Started Aug 10 06:02:34 PM PDT 24
Finished Aug 10 06:02:40 PM PDT 24
Peak memory 201228 kb
Host smart-4b6676c6-e71e-4c48-a8a6-9716b27a79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291842425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2291842425
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1787540340
Short name T433
Test name
Test status
Simulation time 6136481957 ps
CPU time 4.55 seconds
Started Aug 10 06:02:30 PM PDT 24
Finished Aug 10 06:02:35 PM PDT 24
Peak memory 201300 kb
Host smart-7c87dd35-f65b-4ba1-b03a-365dcae9cf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787540340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1787540340
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1195620065
Short name T281
Test name
Test status
Simulation time 280098816195 ps
CPU time 686.82 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:14:06 PM PDT 24
Peak memory 201848 kb
Host smart-b5615666-cc34-4ee6-b07f-70f771b70015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195620065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1195620065
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1693190471
Short name T521
Test name
Test status
Simulation time 95963028390 ps
CPU time 202.23 seconds
Started Aug 10 06:02:34 PM PDT 24
Finished Aug 10 06:05:56 PM PDT 24
Peak memory 213040 kb
Host smart-bf2f4b93-a1b7-482c-b9ea-0456017b0745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693190471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1693190471
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2012780322
Short name T104
Test name
Test status
Simulation time 338314457 ps
CPU time 0.81 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:02:52 PM PDT 24
Peak memory 201256 kb
Host smart-a91dbd22-7bff-4d01-9348-43fc031f91e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012780322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2012780322
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1633240539
Short name T343
Test name
Test status
Simulation time 163274854027 ps
CPU time 361.27 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:08:41 PM PDT 24
Peak memory 201348 kb
Host smart-6ae2ff17-ef35-49d9-a77d-ef3c51b4fc9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633240539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1633240539
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4035849343
Short name T39
Test name
Test status
Simulation time 190717844982 ps
CPU time 105.58 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:04:25 PM PDT 24
Peak memory 201456 kb
Host smart-6286d044-6b2d-4d60-96f4-7e41e814b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035849343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4035849343
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3614344849
Short name T101
Test name
Test status
Simulation time 495433816137 ps
CPU time 440.94 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:10:00 PM PDT 24
Peak memory 201408 kb
Host smart-c41c97b1-4335-4d95-aae1-eeca66493756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614344849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3614344849
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1879763941
Short name T367
Test name
Test status
Simulation time 321145373382 ps
CPU time 785.6 seconds
Started Aug 10 06:02:38 PM PDT 24
Finished Aug 10 06:15:44 PM PDT 24
Peak memory 201472 kb
Host smart-e085f4cd-6ec8-4244-b840-8a181e3471de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879763941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1879763941
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3173939898
Short name T341
Test name
Test status
Simulation time 491955001360 ps
CPU time 582.77 seconds
Started Aug 10 06:02:41 PM PDT 24
Finished Aug 10 06:12:24 PM PDT 24
Peak memory 201392 kb
Host smart-3ed757e6-2752-46c4-8f4f-5f1552fbe62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173939898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3173939898
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3942085762
Short name T724
Test name
Test status
Simulation time 337951608222 ps
CPU time 204.63 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:06:04 PM PDT 24
Peak memory 201432 kb
Host smart-9d67992c-92b6-403d-964c-fc27f608867c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942085762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3942085762
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3974619435
Short name T340
Test name
Test status
Simulation time 557078819232 ps
CPU time 1298.54 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:24:18 PM PDT 24
Peak memory 201460 kb
Host smart-5060e8fa-0c89-4e4c-a735-5db6bc7bfd5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974619435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3974619435
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3067635623
Short name T607
Test name
Test status
Simulation time 197709523390 ps
CPU time 119.98 seconds
Started Aug 10 06:02:38 PM PDT 24
Finished Aug 10 06:04:38 PM PDT 24
Peak memory 201476 kb
Host smart-70288dfd-7ffe-450f-9cbf-3ad3869383c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067635623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3067635623
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.976993042
Short name T655
Test name
Test status
Simulation time 72240075008 ps
CPU time 264.88 seconds
Started Aug 10 06:02:40 PM PDT 24
Finished Aug 10 06:07:05 PM PDT 24
Peak memory 201792 kb
Host smart-cd288706-2dac-42ef-9b15-af989efc921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976993042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.976993042
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4213503093
Short name T637
Test name
Test status
Simulation time 42183392631 ps
CPU time 23.85 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:03:03 PM PDT 24
Peak memory 201356 kb
Host smart-cb4763c6-35b8-4e67-8434-ab41655e47ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213503093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4213503093
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1044633110
Short name T78
Test name
Test status
Simulation time 3751225345 ps
CPU time 5.37 seconds
Started Aug 10 06:02:39 PM PDT 24
Finished Aug 10 06:02:45 PM PDT 24
Peak memory 201368 kb
Host smart-78b4fdce-c457-41e3-b516-f151075e2ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044633110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1044633110
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2152012079
Short name T478
Test name
Test status
Simulation time 5864015772 ps
CPU time 14.39 seconds
Started Aug 10 06:02:38 PM PDT 24
Finished Aug 10 06:02:52 PM PDT 24
Peak memory 201344 kb
Host smart-c0cdf18c-17ae-409a-b018-1ee8dcc5732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152012079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2152012079
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.94121197
Short name T334
Test name
Test status
Simulation time 341265548307 ps
CPU time 778.64 seconds
Started Aug 10 06:02:50 PM PDT 24
Finished Aug 10 06:15:49 PM PDT 24
Peak memory 201432 kb
Host smart-3720438d-1958-4869-815c-2ccc73041df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94121197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.94121197
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1034793776
Short name T318
Test name
Test status
Simulation time 16905163311 ps
CPU time 37.13 seconds
Started Aug 10 06:02:37 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 210624 kb
Host smart-23d66f1d-fed4-4ade-87a0-651c430926b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034793776 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1034793776
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2895701005
Short name T615
Test name
Test status
Simulation time 462527886 ps
CPU time 1.41 seconds
Started Aug 10 06:02:55 PM PDT 24
Finished Aug 10 06:02:56 PM PDT 24
Peak memory 201408 kb
Host smart-fdec8e29-de46-4eb5-bef4-ea7152b2a406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895701005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2895701005
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.40525955
Short name T209
Test name
Test status
Simulation time 324800853636 ps
CPU time 115.55 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:04:47 PM PDT 24
Peak memory 201472 kb
Host smart-d756798a-e688-4879-9a76-c74efda027f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gatin
g.40525955
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2650158668
Short name T699
Test name
Test status
Simulation time 492854900211 ps
CPU time 1060.27 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 201612 kb
Host smart-7baa5375-975b-433d-aca0-264fc643c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650158668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2650158668
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3475079395
Short name T420
Test name
Test status
Simulation time 492457765625 ps
CPU time 1145.93 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:21:57 PM PDT 24
Peak memory 201540 kb
Host smart-422e75b8-f104-429f-b3eb-9d2c7d2953a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475079395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3475079395
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1631495065
Short name T253
Test name
Test status
Simulation time 327687107948 ps
CPU time 738.86 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:15:10 PM PDT 24
Peak memory 201424 kb
Host smart-f9e0620b-8ad2-495b-bca1-be412f2f80ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631495065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1631495065
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4234031018
Short name T397
Test name
Test status
Simulation time 495939467259 ps
CPU time 716.81 seconds
Started Aug 10 06:02:52 PM PDT 24
Finished Aug 10 06:14:49 PM PDT 24
Peak memory 201408 kb
Host smart-798ab8d6-c92b-47b2-bca4-f242982d2f1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234031018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4234031018
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3313169575
Short name T725
Test name
Test status
Simulation time 660072865758 ps
CPU time 687.49 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:14:18 PM PDT 24
Peak memory 201452 kb
Host smart-247905d3-c671-4af6-8d08-99e41b97926a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313169575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3313169575
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.117943374
Short name T461
Test name
Test status
Simulation time 609555992338 ps
CPU time 702.13 seconds
Started Aug 10 06:02:50 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 201480 kb
Host smart-8472c547-55ce-4b96-b4f0-901b4405c85e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117943374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.117943374
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4290289046
Short name T542
Test name
Test status
Simulation time 88929402785 ps
CPU time 299.22 seconds
Started Aug 10 06:02:49 PM PDT 24
Finished Aug 10 06:07:49 PM PDT 24
Peak memory 201944 kb
Host smart-6451903e-fe23-401d-a4f2-da9ee12a839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290289046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4290289046
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3863917283
Short name T776
Test name
Test status
Simulation time 28497881997 ps
CPU time 16.14 seconds
Started Aug 10 06:02:50 PM PDT 24
Finished Aug 10 06:03:07 PM PDT 24
Peak memory 201336 kb
Host smart-e3938727-d240-4b6f-8b16-5dea48938c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863917283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3863917283
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2467253745
Short name T112
Test name
Test status
Simulation time 2995502709 ps
CPU time 1.29 seconds
Started Aug 10 06:02:49 PM PDT 24
Finished Aug 10 06:02:50 PM PDT 24
Peak memory 201348 kb
Host smart-6510af8d-67a8-4dfb-8734-4e634ba18de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467253745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2467253745
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1171062899
Short name T773
Test name
Test status
Simulation time 5655314491 ps
CPU time 12.56 seconds
Started Aug 10 06:02:51 PM PDT 24
Finished Aug 10 06:03:03 PM PDT 24
Peak memory 201316 kb
Host smart-69324b64-a972-48b3-a6f3-9b51976e09db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171062899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1171062899
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.459556904
Short name T479
Test name
Test status
Simulation time 6909068452 ps
CPU time 5.12 seconds
Started Aug 10 06:02:50 PM PDT 24
Finished Aug 10 06:02:55 PM PDT 24
Peak memory 201348 kb
Host smart-ce1a8be0-66da-4cbf-b786-d6dc399f5542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459556904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
459556904
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3743025440
Short name T457
Test name
Test status
Simulation time 480879673 ps
CPU time 1.58 seconds
Started Aug 10 06:03:04 PM PDT 24
Finished Aug 10 06:03:06 PM PDT 24
Peak memory 201228 kb
Host smart-fda8c2fe-fb22-4022-96a5-f59a40a70f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743025440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3743025440
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.728386968
Short name T14
Test name
Test status
Simulation time 168066495276 ps
CPU time 183.84 seconds
Started Aug 10 06:02:57 PM PDT 24
Finished Aug 10 06:06:01 PM PDT 24
Peak memory 201536 kb
Host smart-076b45a4-3e28-4bc1-b817-5755d9965bcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728386968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.728386968
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1770943041
Short name T714
Test name
Test status
Simulation time 495216867463 ps
CPU time 552.34 seconds
Started Aug 10 06:02:55 PM PDT 24
Finished Aug 10 06:12:08 PM PDT 24
Peak memory 201456 kb
Host smart-aa0998e9-9633-41b3-924a-9bf158567b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770943041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1770943041
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3724697034
Short name T645
Test name
Test status
Simulation time 489777332781 ps
CPU time 95.65 seconds
Started Aug 10 06:02:56 PM PDT 24
Finished Aug 10 06:04:32 PM PDT 24
Peak memory 201416 kb
Host smart-7c5af038-5dca-49b3-920c-49e6ef854344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724697034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3724697034
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3063057734
Short name T688
Test name
Test status
Simulation time 327276313457 ps
CPU time 743.64 seconds
Started Aug 10 06:02:56 PM PDT 24
Finished Aug 10 06:15:20 PM PDT 24
Peak memory 201460 kb
Host smart-8e4c1263-a497-49ea-87fc-456910afa517
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063057734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3063057734
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3118331165
Short name T333
Test name
Test status
Simulation time 163068810567 ps
CPU time 326.64 seconds
Started Aug 10 06:02:55 PM PDT 24
Finished Aug 10 06:08:22 PM PDT 24
Peak memory 201364 kb
Host smart-d330a82f-8767-467e-b739-9d50fa786f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118331165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3118331165
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.223314527
Short name T601
Test name
Test status
Simulation time 501307535154 ps
CPU time 1059.82 seconds
Started Aug 10 06:02:57 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 201440 kb
Host smart-8bcd1551-ccf3-4ff6-85f0-83a6f2bd5b08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=223314527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.223314527
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2435263845
Short name T298
Test name
Test status
Simulation time 385932626153 ps
CPU time 428.39 seconds
Started Aug 10 06:02:55 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 201444 kb
Host smart-0866af6a-39e5-4684-8007-fef0c7183256
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435263845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2435263845
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2804810760
Short name T395
Test name
Test status
Simulation time 213937542353 ps
CPU time 128 seconds
Started Aug 10 06:02:57 PM PDT 24
Finished Aug 10 06:05:05 PM PDT 24
Peak memory 201392 kb
Host smart-3139dfc6-aa63-4b4f-86c8-eb027a2efbc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804810760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2804810760
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.212589949
Short name T424
Test name
Test status
Simulation time 85197884239 ps
CPU time 443.36 seconds
Started Aug 10 06:02:53 PM PDT 24
Finished Aug 10 06:10:17 PM PDT 24
Peak memory 201828 kb
Host smart-d2e5c83d-b9c3-4696-9cb4-8ae5ff3dbc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212589949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.212589949
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3429812645
Short name T758
Test name
Test status
Simulation time 35490860087 ps
CPU time 80.87 seconds
Started Aug 10 06:02:57 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 201320 kb
Host smart-cc5aee7b-5297-48e9-88c3-5ef4918f27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429812645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3429812645
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.757019143
Short name T728
Test name
Test status
Simulation time 3659877073 ps
CPU time 2.47 seconds
Started Aug 10 06:02:57 PM PDT 24
Finished Aug 10 06:03:00 PM PDT 24
Peak memory 201316 kb
Host smart-3f88b766-68fb-4fdc-8fd0-946e2aafd9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757019143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.757019143
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1903750749
Short name T404
Test name
Test status
Simulation time 5826164083 ps
CPU time 4.19 seconds
Started Aug 10 06:02:55 PM PDT 24
Finished Aug 10 06:02:59 PM PDT 24
Peak memory 201348 kb
Host smart-41da34b3-51a5-4bd8-a114-0d45b241329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903750749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1903750749
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.749161025
Short name T18
Test name
Test status
Simulation time 122327200729 ps
CPU time 69.34 seconds
Started Aug 10 06:02:56 PM PDT 24
Finished Aug 10 06:04:06 PM PDT 24
Peak memory 209728 kb
Host smart-b22123c1-1128-4e0b-9235-fdcd2ff3280a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749161025 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.749161025
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3579178268
Short name T359
Test name
Test status
Simulation time 292715753 ps
CPU time 1.25 seconds
Started Aug 10 06:03:13 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 201248 kb
Host smart-eeb39d43-0eb7-4386-9008-30f286bf498b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579178268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3579178268
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3880393892
Short name T186
Test name
Test status
Simulation time 330418240933 ps
CPU time 793.32 seconds
Started Aug 10 06:03:03 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 201468 kb
Host smart-e30066f0-367a-4f83-967a-734c2b5db3c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880393892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3880393892
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4265917195
Short name T182
Test name
Test status
Simulation time 350685241212 ps
CPU time 424.7 seconds
Started Aug 10 06:03:04 PM PDT 24
Finished Aug 10 06:10:09 PM PDT 24
Peak memory 201388 kb
Host smart-9ab72bc2-a2a3-4361-afc6-e4a35149bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265917195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4265917195
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.93709953
Short name T180
Test name
Test status
Simulation time 167987506483 ps
CPU time 76.34 seconds
Started Aug 10 06:03:03 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 201468 kb
Host smart-0a595b5e-7286-46da-b53d-d1377f2db6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93709953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.93709953
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1046069584
Short name T560
Test name
Test status
Simulation time 167615043219 ps
CPU time 102.18 seconds
Started Aug 10 06:03:02 PM PDT 24
Finished Aug 10 06:04:44 PM PDT 24
Peak memory 201296 kb
Host smart-482f717d-8c68-481e-8a27-3cad7ac4d965
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046069584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1046069584
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2643771736
Short name T197
Test name
Test status
Simulation time 333757275937 ps
CPU time 192.39 seconds
Started Aug 10 06:03:09 PM PDT 24
Finished Aug 10 06:06:21 PM PDT 24
Peak memory 201468 kb
Host smart-b20565bd-de28-4a44-80c1-9aca27f92d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643771736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2643771736
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2166137948
Short name T737
Test name
Test status
Simulation time 333712776628 ps
CPU time 177.41 seconds
Started Aug 10 06:03:03 PM PDT 24
Finished Aug 10 06:06:00 PM PDT 24
Peak memory 201440 kb
Host smart-355a6ffe-cb83-4745-92bd-bf23ab995d6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166137948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2166137948
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.873918815
Short name T344
Test name
Test status
Simulation time 385173267219 ps
CPU time 895.66 seconds
Started Aug 10 06:03:03 PM PDT 24
Finished Aug 10 06:17:59 PM PDT 24
Peak memory 201428 kb
Host smart-5267a185-748c-4038-ab81-14b890903630
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873918815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.873918815
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.209661227
Short name T539
Test name
Test status
Simulation time 198910894694 ps
CPU time 210.92 seconds
Started Aug 10 06:03:19 PM PDT 24
Finished Aug 10 06:06:50 PM PDT 24
Peak memory 201464 kb
Host smart-a261af35-d611-44f2-b387-374f281b6e54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209661227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.209661227
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.403830013
Short name T723
Test name
Test status
Simulation time 103199644440 ps
CPU time 414.47 seconds
Started Aug 10 06:03:09 PM PDT 24
Finished Aug 10 06:10:03 PM PDT 24
Peak memory 201864 kb
Host smart-eb264641-100b-4909-9f5b-53834fd953ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403830013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.403830013
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.351802562
Short name T649
Test name
Test status
Simulation time 37910668991 ps
CPU time 5.14 seconds
Started Aug 10 06:03:09 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 201320 kb
Host smart-b07ca0d3-167c-49d2-8b03-956d8e95029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351802562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.351802562
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2439200249
Short name T606
Test name
Test status
Simulation time 3953290494 ps
CPU time 1.34 seconds
Started Aug 10 06:03:04 PM PDT 24
Finished Aug 10 06:03:05 PM PDT 24
Peak memory 201352 kb
Host smart-0d9fa3a1-49cc-420d-89d4-b8da5ad067d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439200249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2439200249
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2237320362
Short name T744
Test name
Test status
Simulation time 5521517124 ps
CPU time 13.51 seconds
Started Aug 10 06:03:03 PM PDT 24
Finished Aug 10 06:03:17 PM PDT 24
Peak memory 201344 kb
Host smart-c31e5bfb-4d9d-4247-b8b7-832cdb86296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237320362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2237320362
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1694894041
Short name T33
Test name
Test status
Simulation time 51409622829 ps
CPU time 80.49 seconds
Started Aug 10 06:03:10 PM PDT 24
Finished Aug 10 06:04:30 PM PDT 24
Peak memory 209804 kb
Host smart-a94633e0-a714-4fda-bd73-59837e984cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694894041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1694894041
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2519500119
Short name T783
Test name
Test status
Simulation time 323071518 ps
CPU time 1.02 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 05:59:15 PM PDT 24
Peak memory 201248 kb
Host smart-bf099990-8d6c-40f6-b168-d9b18b06a991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519500119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2519500119
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.92670533
Short name T702
Test name
Test status
Simulation time 190982974565 ps
CPU time 209.37 seconds
Started Aug 10 05:59:13 PM PDT 24
Finished Aug 10 06:02:43 PM PDT 24
Peak memory 201436 kb
Host smart-ac0b4bed-478a-463b-8d32-2c21fee5ce1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92670533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating
.92670533
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2280080356
Short name T170
Test name
Test status
Simulation time 493128521663 ps
CPU time 998.69 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:15:55 PM PDT 24
Peak memory 201432 kb
Host smart-7b0d18fb-d7c3-4407-929f-234f115943b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280080356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2280080356
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.319009457
Short name T432
Test name
Test status
Simulation time 494278778322 ps
CPU time 505.99 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:07:28 PM PDT 24
Peak memory 201640 kb
Host smart-2b09fa74-3620-4df2-882d-d554e581c3d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=319009457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.319009457
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2954616580
Short name T704
Test name
Test status
Simulation time 164824499192 ps
CPU time 125.49 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:01:23 PM PDT 24
Peak memory 201436 kb
Host smart-50657863-ad62-4c9c-af85-d06e4a633e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954616580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2954616580
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.969440680
Short name T503
Test name
Test status
Simulation time 332974635137 ps
CPU time 323.22 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:04:39 PM PDT 24
Peak memory 201436 kb
Host smart-69a3417b-bbd3-4023-af79-bc4af3ad13fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=969440680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.969440680
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3471663243
Short name T733
Test name
Test status
Simulation time 336554580792 ps
CPU time 195.13 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:02:33 PM PDT 24
Peak memory 201472 kb
Host smart-5084194b-378b-487c-9d2c-e2a265afd349
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471663243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3471663243
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.828824147
Short name T762
Test name
Test status
Simulation time 408046312856 ps
CPU time 926.73 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:14:29 PM PDT 24
Peak memory 201456 kb
Host smart-46532ebb-6a1f-4150-aec2-767d187e44bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828824147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.828824147
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3398372232
Short name T626
Test name
Test status
Simulation time 117373365374 ps
CPU time 423.43 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:06:20 PM PDT 24
Peak memory 201844 kb
Host smart-f49e2c39-5f16-4773-b9df-670058ffe907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398372232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3398372232
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1084796773
Short name T675
Test name
Test status
Simulation time 35405597990 ps
CPU time 37.22 seconds
Started Aug 10 05:59:05 PM PDT 24
Finished Aug 10 05:59:42 PM PDT 24
Peak memory 201316 kb
Host smart-b94b4904-a5e5-4856-83d4-bef670100dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084796773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1084796773
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3453769134
Short name T595
Test name
Test status
Simulation time 4412031764 ps
CPU time 3.23 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 05:59:19 PM PDT 24
Peak memory 201348 kb
Host smart-9b320238-9b63-4589-820c-e5a72a90283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453769134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3453769134
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1803470388
Short name T678
Test name
Test status
Simulation time 6020906065 ps
CPU time 15.26 seconds
Started Aug 10 05:59:13 PM PDT 24
Finished Aug 10 05:59:28 PM PDT 24
Peak memory 201372 kb
Host smart-e16fe5a8-9e81-4974-92d9-aa5b9aa9b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803470388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1803470388
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3472172581
Short name T11
Test name
Test status
Simulation time 53421461419 ps
CPU time 131.38 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:01:28 PM PDT 24
Peak memory 201352 kb
Host smart-d1a1e537-0a7b-46a2-bc69-7ab9e9c6f2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472172581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3472172581
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1672476520
Short name T681
Test name
Test status
Simulation time 29979489049 ps
CPU time 62.99 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:00:21 PM PDT 24
Peak memory 209840 kb
Host smart-582c6894-5876-481d-bf35-664aca6bb3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672476520 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1672476520
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.379654463
Short name T551
Test name
Test status
Simulation time 332356201 ps
CPU time 1.35 seconds
Started Aug 10 05:59:12 PM PDT 24
Finished Aug 10 05:59:14 PM PDT 24
Peak memory 201240 kb
Host smart-bc648488-ba94-4eaa-b841-23454e949a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379654463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.379654463
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3196924656
Short name T583
Test name
Test status
Simulation time 187353082815 ps
CPU time 317.66 seconds
Started Aug 10 05:59:01 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 201404 kb
Host smart-f44946c5-6509-4134-a3a3-1bfc0d29d47c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196924656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3196924656
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2792804966
Short name T510
Test name
Test status
Simulation time 171284798613 ps
CPU time 97.24 seconds
Started Aug 10 05:59:05 PM PDT 24
Finished Aug 10 06:00:42 PM PDT 24
Peak memory 201396 kb
Host smart-1bab863a-dd02-4c53-a2e4-6013f1d4923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792804966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2792804966
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3593143101
Short name T458
Test name
Test status
Simulation time 500500964164 ps
CPU time 1157.32 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 201332 kb
Host smart-ca1fc428-819d-40e5-b018-d81d2bf5bebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593143101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3593143101
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3119951296
Short name T732
Test name
Test status
Simulation time 487630493772 ps
CPU time 295.3 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 201504 kb
Host smart-bd94b5d7-2e2a-496a-9a29-719adda3594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119951296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3119951296
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3926532521
Short name T673
Test name
Test status
Simulation time 162454382394 ps
CPU time 172.93 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 06:01:56 PM PDT 24
Peak memory 201404 kb
Host smart-d90ab26a-05ce-484b-ac58-12239185973d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926532521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3926532521
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.984882349
Short name T184
Test name
Test status
Simulation time 358428685386 ps
CPU time 422.39 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:06:24 PM PDT 24
Peak memory 201384 kb
Host smart-434a9b9c-3eff-466b-8142-8251f1ebe486
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984882349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.984882349
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1061477468
Short name T96
Test name
Test status
Simulation time 386765410294 ps
CPU time 243.04 seconds
Started Aug 10 05:59:05 PM PDT 24
Finished Aug 10 06:03:09 PM PDT 24
Peak memory 201364 kb
Host smart-a09a4d89-3855-4940-96f3-845abdc42c93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061477468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1061477468
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.158719862
Short name T219
Test name
Test status
Simulation time 128912171165 ps
CPU time 690.33 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 06:10:54 PM PDT 24
Peak memory 201816 kb
Host smart-5453cb76-81c4-420c-bfbf-67e5f71b4474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158719862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.158719862
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3984306746
Short name T499
Test name
Test status
Simulation time 45426526970 ps
CPU time 109.24 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:00:51 PM PDT 24
Peak memory 201352 kb
Host smart-e6e2a799-7d4c-41ef-8e9e-14b7c1523f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984306746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3984306746
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.403609916
Short name T707
Test name
Test status
Simulation time 4254512068 ps
CPU time 5.55 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 05:59:12 PM PDT 24
Peak memory 201304 kb
Host smart-b2fa4b27-979e-4a34-8f9d-3fe4d54a6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403609916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.403609916
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2463389978
Short name T108
Test name
Test status
Simulation time 5685457689 ps
CPU time 14.3 seconds
Started Aug 10 05:59:15 PM PDT 24
Finished Aug 10 05:59:29 PM PDT 24
Peak memory 201308 kb
Host smart-8a81a85a-404d-4fbe-a666-43e2135d5c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463389978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2463389978
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3849042681
Short name T644
Test name
Test status
Simulation time 17254586368 ps
CPU time 20.77 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 05:59:28 PM PDT 24
Peak memory 201420 kb
Host smart-4a33db70-230a-4280-af8f-c1e5fbfc40fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849042681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3849042681
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1321784162
Short name T297
Test name
Test status
Simulation time 232255022523 ps
CPU time 269.79 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:03:49 PM PDT 24
Peak memory 218296 kb
Host smart-3a84c3d4-d37f-4ba4-8ff1-65f27cb2dc4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321784162 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1321784162
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2600262550
Short name T91
Test name
Test status
Simulation time 518245783 ps
CPU time 1.73 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 05:59:16 PM PDT 24
Peak memory 201272 kb
Host smart-fe0db2f6-5517-46a2-8fc4-de5d340ebeff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600262550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2600262550
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3307959961
Short name T452
Test name
Test status
Simulation time 256940458877 ps
CPU time 576.18 seconds
Started Aug 10 05:59:15 PM PDT 24
Finished Aug 10 06:08:52 PM PDT 24
Peak memory 201508 kb
Host smart-4ba1a1b6-ea08-4230-978b-b4dcdd0bda4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307959961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3307959961
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3070160159
Short name T268
Test name
Test status
Simulation time 161541472924 ps
CPU time 334.63 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:04:52 PM PDT 24
Peak memory 201408 kb
Host smart-1852ae8a-091b-4f29-aa7d-00531483ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070160159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3070160159
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.321115212
Short name T373
Test name
Test status
Simulation time 492507619548 ps
CPU time 1031.04 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:16:29 PM PDT 24
Peak memory 201476 kb
Host smart-25edc005-c7bf-45fe-919d-9b84dd14fb5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=321115212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.321115212
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3953900611
Short name T137
Test name
Test status
Simulation time 324412140724 ps
CPU time 175.6 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:02:02 PM PDT 24
Peak memory 201464 kb
Host smart-73fe4d56-10f0-4908-9ad9-8a0d66afcc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953900611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3953900611
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1966919915
Short name T547
Test name
Test status
Simulation time 163864900082 ps
CPU time 89.58 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:00:49 PM PDT 24
Peak memory 201440 kb
Host smart-88d2acda-f801-46c1-94b6-5918c77ede8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966919915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1966919915
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3109561522
Short name T718
Test name
Test status
Simulation time 171577937953 ps
CPU time 106.51 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 06:00:49 PM PDT 24
Peak memory 201508 kb
Host smart-f7d49bd3-0957-4235-bb63-acf4d7edc3d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109561522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3109561522
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1321913332
Short name T12
Test name
Test status
Simulation time 609569444338 ps
CPU time 1343.43 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:21:31 PM PDT 24
Peak memory 201344 kb
Host smart-b31652c9-5c5f-4b7b-8b1e-71113f8e46aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321913332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1321913332
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1937233140
Short name T566
Test name
Test status
Simulation time 68698710751 ps
CPU time 236.63 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 201852 kb
Host smart-fd1a08de-c98d-475c-bae5-47747085c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937233140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1937233140
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2337430057
Short name T469
Test name
Test status
Simulation time 37723978977 ps
CPU time 81.03 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 06:00:28 PM PDT 24
Peak memory 201356 kb
Host smart-7e8a4fa7-0291-4c2e-b1a5-6cd758dd0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337430057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2337430057
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3562743755
Short name T374
Test name
Test status
Simulation time 2961502461 ps
CPU time 4.64 seconds
Started Aug 10 05:59:07 PM PDT 24
Finished Aug 10 05:59:11 PM PDT 24
Peak memory 201276 kb
Host smart-7778227d-7886-44f7-9ff7-ea316de8c168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562743755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3562743755
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.193632161
Short name T356
Test name
Test status
Simulation time 5752124146 ps
CPU time 12.6 seconds
Started Aug 10 05:59:26 PM PDT 24
Finished Aug 10 05:59:39 PM PDT 24
Peak memory 201316 kb
Host smart-f7c34ea3-b40e-4067-b9f6-e9dffda6ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193632161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.193632161
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.875361597
Short name T288
Test name
Test status
Simulation time 495147841840 ps
CPU time 223.26 seconds
Started Aug 10 05:59:29 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 201440 kb
Host smart-e915fe7a-02a4-4a48-88b0-46e8ba795577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875361597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.875361597
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.402252058
Short name T684
Test name
Test status
Simulation time 409412508 ps
CPU time 1.55 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 05:59:20 PM PDT 24
Peak memory 201268 kb
Host smart-213ddb9b-ff32-4264-85e4-0815c14ea5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402252058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.402252058
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.639709711
Short name T89
Test name
Test status
Simulation time 164051269189 ps
CPU time 95.85 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:00:53 PM PDT 24
Peak memory 201456 kb
Host smart-5f0c9b43-29c1-480c-9b58-a6d861555f55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639709711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.639709711
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3164531283
Short name T247
Test name
Test status
Simulation time 164286250716 ps
CPU time 353.82 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 06:05:10 PM PDT 24
Peak memory 201480 kb
Host smart-bd4a4351-fd86-49e3-b58a-d95361eeb843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164531283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3164531283
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.138521727
Short name T541
Test name
Test status
Simulation time 496684614455 ps
CPU time 1078.49 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 201448 kb
Host smart-8b5afe03-6f45-4d4b-ad0d-4e347077f266
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=138521727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.138521727
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3120363838
Short name T139
Test name
Test status
Simulation time 328842246932 ps
CPU time 368.21 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:05:29 PM PDT 24
Peak memory 201444 kb
Host smart-ad46e620-e789-46ed-9f60-d7b403d8cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120363838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3120363838
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2638168983
Short name T160
Test name
Test status
Simulation time 329532414194 ps
CPU time 186.38 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:02:29 PM PDT 24
Peak memory 201368 kb
Host smart-137a1566-116a-4ee7-b90f-ecaca0781ac8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638168983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2638168983
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.313733775
Short name T230
Test name
Test status
Simulation time 189254798144 ps
CPU time 131.99 seconds
Started Aug 10 05:59:25 PM PDT 24
Finished Aug 10 06:01:37 PM PDT 24
Peak memory 201448 kb
Host smart-4bd1573f-5770-4c6a-9f5d-f08f380fbbf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313733775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.313733775
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.714178588
Short name T612
Test name
Test status
Simulation time 202593069963 ps
CPU time 124.29 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:01:26 PM PDT 24
Peak memory 201512 kb
Host smart-a69075bb-21e8-419c-bf56-e9ae0573644b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714178588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.714178588
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.446492139
Short name T346
Test name
Test status
Simulation time 115274572236 ps
CPU time 411.73 seconds
Started Aug 10 05:59:15 PM PDT 24
Finished Aug 10 06:06:07 PM PDT 24
Peak memory 201872 kb
Host smart-6bff9196-fff5-4e7e-8c30-211a6793efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446492139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.446492139
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3191812088
Short name T372
Test name
Test status
Simulation time 39366233672 ps
CPU time 39.27 seconds
Started Aug 10 05:59:21 PM PDT 24
Finished Aug 10 06:00:01 PM PDT 24
Peak memory 201372 kb
Host smart-33c63249-5f48-45bb-8c0b-43678a0d0da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191812088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3191812088
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2366262614
Short name T429
Test name
Test status
Simulation time 3432716857 ps
CPU time 8.14 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 05:59:27 PM PDT 24
Peak memory 201368 kb
Host smart-c1d5ee5a-a4ee-4eef-a14c-11b1853908d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366262614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2366262614
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.770899512
Short name T722
Test name
Test status
Simulation time 6122554537 ps
CPU time 15.05 seconds
Started Aug 10 05:59:14 PM PDT 24
Finished Aug 10 05:59:29 PM PDT 24
Peak memory 201392 kb
Host smart-acefe6f6-3977-4587-b619-bb219c57cf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770899512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.770899512
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3059836928
Short name T468
Test name
Test status
Simulation time 17585945728 ps
CPU time 43.43 seconds
Started Aug 10 05:59:38 PM PDT 24
Finished Aug 10 06:00:22 PM PDT 24
Peak memory 209824 kb
Host smart-f814f5fe-f6b0-46ab-a455-ec2fdc7e4b26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059836928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3059836928
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.135855133
Short name T198
Test name
Test status
Simulation time 405020064 ps
CPU time 0.81 seconds
Started Aug 10 05:59:11 PM PDT 24
Finished Aug 10 05:59:12 PM PDT 24
Peak memory 201264 kb
Host smart-7c594168-eb04-43f4-9350-25fc5de11823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135855133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.135855133
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3289629149
Short name T147
Test name
Test status
Simulation time 350505057311 ps
CPU time 58.94 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:00:17 PM PDT 24
Peak memory 201436 kb
Host smart-1c31201c-a490-4d1f-a6fa-f11b63d47265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289629149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3289629149
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1732794278
Short name T781
Test name
Test status
Simulation time 359163706320 ps
CPU time 787.88 seconds
Started Aug 10 05:59:25 PM PDT 24
Finished Aug 10 06:12:33 PM PDT 24
Peak memory 201500 kb
Host smart-67d222f2-d0e2-436d-bece-40d7a6d3eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732794278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1732794278
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3327373940
Short name T656
Test name
Test status
Simulation time 168342547571 ps
CPU time 100.99 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 06:01:04 PM PDT 24
Peak memory 201408 kb
Host smart-bb71b578-1fe3-45b5-b561-27ed82b68683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327373940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3327373940
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2123028374
Short name T352
Test name
Test status
Simulation time 493034854807 ps
CPU time 1197.82 seconds
Started Aug 10 05:59:19 PM PDT 24
Finished Aug 10 06:19:17 PM PDT 24
Peak memory 201480 kb
Host smart-578a91ef-9185-4bc6-9284-8ac76b1c68ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123028374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2123028374
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3791961042
Short name T694
Test name
Test status
Simulation time 492081280102 ps
CPU time 1114.93 seconds
Started Aug 10 05:59:27 PM PDT 24
Finished Aug 10 06:18:02 PM PDT 24
Peak memory 201456 kb
Host smart-341f5146-a2d9-49cb-bf7d-dccb08426950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791961042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3791961042
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2964200542
Short name T481
Test name
Test status
Simulation time 319413003283 ps
CPU time 741.01 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:11:40 PM PDT 24
Peak memory 201440 kb
Host smart-769a9c44-16d2-4ed3-8ccd-69057fae58fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964200542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2964200542
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3469624258
Short name T738
Test name
Test status
Simulation time 357489959085 ps
CPU time 228.38 seconds
Started Aug 10 05:59:22 PM PDT 24
Finished Aug 10 06:03:11 PM PDT 24
Peak memory 201456 kb
Host smart-85f8246f-6a34-4f4b-b692-e9121fb1a7cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469624258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3469624258
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3193200942
Short name T610
Test name
Test status
Simulation time 588408653211 ps
CPU time 153.77 seconds
Started Aug 10 05:59:18 PM PDT 24
Finished Aug 10 06:01:51 PM PDT 24
Peak memory 201460 kb
Host smart-e89aa4c0-635c-4711-92e1-7cb1ae77e24c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193200942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3193200942
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.173951895
Short name T535
Test name
Test status
Simulation time 116376949068 ps
CPU time 420.13 seconds
Started Aug 10 05:59:24 PM PDT 24
Finished Aug 10 06:06:24 PM PDT 24
Peak memory 201900 kb
Host smart-b5b1d13b-6a86-4eb7-8c8c-edb0eb76713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173951895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.173951895
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.830652412
Short name T599
Test name
Test status
Simulation time 32657206208 ps
CPU time 19.9 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 05:59:43 PM PDT 24
Peak memory 201344 kb
Host smart-929eb522-b02f-4599-8975-a0a8b5c327aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830652412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.830652412
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3592442952
Short name T650
Test name
Test status
Simulation time 3244105103 ps
CPU time 8.08 seconds
Started Aug 10 05:59:23 PM PDT 24
Finished Aug 10 05:59:31 PM PDT 24
Peak memory 201316 kb
Host smart-2378f425-3174-40ac-8a41-3f990ad65bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592442952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3592442952
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3098124804
Short name T380
Test name
Test status
Simulation time 5663432335 ps
CPU time 13.54 seconds
Started Aug 10 05:59:12 PM PDT 24
Finished Aug 10 05:59:26 PM PDT 24
Peak memory 201376 kb
Host smart-26cdc4cb-4557-4867-8950-44336f710556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098124804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3098124804
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3496869440
Short name T692
Test name
Test status
Simulation time 211928526560 ps
CPU time 468.52 seconds
Started Aug 10 05:59:29 PM PDT 24
Finished Aug 10 06:07:17 PM PDT 24
Peak memory 201492 kb
Host smart-d31bcb0d-1783-4445-ac8a-415335b17825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496869440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3496869440
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2051683354
Short name T17
Test name
Test status
Simulation time 29935970585 ps
CPU time 79.08 seconds
Started Aug 10 05:59:17 PM PDT 24
Finished Aug 10 06:00:41 PM PDT 24
Peak memory 210152 kb
Host smart-fb796562-6b2e-495f-9810-a953e3e99094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051683354 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2051683354
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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