Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7162	1			T5	60		T6	64		T8	57
testmodes[AdcCtrlTestmodeNormal]	5837	1			T1	1		T3	3		T5	55
testmodes[AdcCtrlTestmodeLowpower]	6167	1			T2	1		T5	45		T6	52
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3806	1			T5	21		T6	21		T8	21
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1861	1			T5	19		T6	24		T8	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1395	1			T5	19		T6	18		T8	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1869	1			T5	25		T6	26		T8	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2135	1			T3	2		T5	17		T6	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1475	1			T5	13		T6	17		T8	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1368	1			T5	14		T6	16		T8	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1524	1			T5	18		T6	19		T8	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	3034	1			T5	13		T6	17		T8	17