Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24035

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3240

1

T10

15

T11

11

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21187

1

T5

160

T6

171

T8

160

auto[1]

6088

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T34	4		-	-		-	-
values[0]	118	1			T146	12		T150	18		T237	15
values[1]	731	1			T13	5		T238	1		T175	17
values[2]	2846	1			T1	12		T2	15		T3	24
values[3]	696	1			T10	15		T11	1		T12	6
values[4]	870	1			T10	21		T53	22		T56	15
values[5]	665	1			T145	1		T153	11		T189	22
values[6]	652	1			T12	16		T13	4		T59	1
values[7]	722	1			T56	10		T176	8		T45	12
values[8]	734	1			T12	15		T59	23		T238	1
values[9]	1024	1			T7	1		T13	29		T53	9
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	891	1			T13	5		T41	12		T238	1
values[1]	2895	1			T1	12		T2	15		T3	24
values[2]	802	1			T10	21		T11	1		T53	24
values[3]	780	1			T10	15		T56	15		T216	20
values[4]	703	1			T145	1		T153	11		T189	22
values[5]	585	1			T12	16		T13	4		T59	1
values[6]	789	1			T56	10		T238	1		T176	8
values[7]	629	1			T12	15		T59	23		T216	7
values[8]	765	1			T7	1		T13	29		T152	14
values[9]	201	1			T53	9		T144	3		T40	5
minimum	18235	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	2		T41	12		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T143	1		T153	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T1	1		T2	15		T3	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	3		T12	6		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	11		T11	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T53	20		T154	21		T163	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T56	7		T216	7		T154	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	8		T146	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	3		T30	8		T169	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T145	1		T153	1		T189	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	16		T13	2		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T167	11		T148	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T56	9		T238	1		T176	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T45	12		T163	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	15		T59	11		T60	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T216	4		T176	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T177	2		T47	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	17		T152	7		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T53	3		T144	1		T40	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T239	1		T240	1		T222	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18081	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	3		T175	7		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T153	11		T148	7		T146	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T1	11		T3	21		T56	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	8		T49	7		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	10		T144	8		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T53	4		T154	2		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T56	8		T216	13		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	7		T146	6		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	6		T169	9		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T153	10		T189	10		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	2		T175	2		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T148	15		T149	8		T242	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T56	1		T176	5		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T163	1		T155	10		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T59	12		T60	10		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T216	3		T39	8		T162	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T177	3		T47	15		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	12		T152	7		T46	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T53	6		T144	2		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T240	6		T244	5		T245	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	2		T42	4		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T34	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T150	10		T237	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T146	1		T247	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	2		T238	1		T175	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T153	1		T148	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	3		T53	1		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T144	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	8		T12	6		T154	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T10	11		T56	7		T216	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	19		T146	1		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	13		T15	3		T169	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T145	1		T153	1		T189	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	16		T13	2		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T167	11		T148	1		T249	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	9		T176	3		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	12		T149	9		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	15		T59	11		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T176	1		T160	1		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	1		T53	3		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	17		T216	4		T152	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T150	8		T237	14		T250	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T146	11		T247	11		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	3		T175	7		T150	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T153	11		T148	7		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T1	11		T3	21		T56	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	8		T53	1		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T144	8		T148	1		T189	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	7		T154	2		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	10		T56	8		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	3		T146	6		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T169	9		T241	8		T252	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T153	10		T189	10		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T175	2		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	15		T249	14		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T56	1		T176	5		T209	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T149	8		T163	1		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T59	12		T153	3		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	13		T162	7		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	6		T144	2		T60	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	12		T216	3		T152	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	4		T41	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T143	1		T153	12		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T1	12		T2	1		T3	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	9		T12	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T10	11		T11	1		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T53	6		T154	3		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T56	9		T216	14		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	8		T146	7		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	1		T30	7		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T145	1		T153	11		T189	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T13	3		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T167	1		T148	16		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T56	2		T238	1		T176	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	1		T163	2		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T59	13		T60	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T216	4		T176	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T177	4		T47	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	13		T152	8		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T53	7		T144	3		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T239	1		T240	7		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18225	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	1		T41	11		T175	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T161	4		T163	2		T168	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T2	14		T54	22		T55	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	2		T12	5		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	10		T189	1		T253	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	18		T154	20		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T56	6		T216	6		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	7		T42	1		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	2		T30	7		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T189	11		T249	12		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	15		T13	1		T167	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T167	10		T149	8		T256	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T56	8		T176	2		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	11		T243	2		T257	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	14		T59	10		T60	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T216	3		T39	5		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T177	1		T47	14		T178	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	16		T152	6		T46	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T53	2		T257	13		T258	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T222	15		T244	4		T259	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T260	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T34	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T150	9		T237	15		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T146	12		T247	12		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	4		T238	1		T175	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T153	12		T148	8		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	9		T53	2		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T144	9		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	8		T12	1		T154	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T10	11		T56	9		T216	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	4		T146	7		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T45	1		T15	1		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T145	1		T153	11		T189	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T13	3		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T167	1		T148	16		T249	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T56	2		T176	6		T209	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	1		T149	9		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	1		T59	13		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T176	1		T160	1		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T7	1		T53	7		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T13	13		T216	4		T152	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T150	9		T260	10		T261	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T175	9		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T161	4		T49	7		T157	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T2	14		T41	11		T54	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	2		T163	2		T168	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T189	1		T254	11		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	7		T12	5		T154	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	10		T56	6		T216	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	18		T42	1		T254	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T45	12		T15	2		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T189	11		T255	8		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	15		T13	1		T167	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T167	10		T249	12		T256	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T56	8		T176	2		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	11		T149	8		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	14		T59	10		T177	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T46	13		T156	2		T263	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T53	2		T60	11		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	16		T216	3		T152	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23788

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3487

1

T7

1

T10

15

T11

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21170

1

T5

150

T6

170

T8

157

auto[1]

6105

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	469	1			T5	10		T6	1		T8	3
values[0]	2	1			T264	1		T265	1		-	-
values[1]	511	1			T41	12		T143	1		T144	3
values[2]	3012	1			T1	12		T2	15		T3	24
values[3]	803	1			T12	16		T13	4		T176	8
values[4]	669	1			T10	36		T13	5		T56	15
values[5]	552	1			T11	11		T12	6		T53	2
values[6]	799	1			T238	1		T167	9		T154	23
values[7]	656	1			T13	29		T53	9		T238	1
values[8]	665	1			T7	1		T60	22		T153	11
values[9]	1332	1			T12	15		T59	1		T152	14
minimum	17805	1			T5	150		T6	170		T8	157

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	756	1			T41	12		T56	10		T143	1
values[1]	3077	1			T1	12		T2	15		T3	24
values[2]	651	1			T175	5		T176	8		T162	14
values[3]	679	1			T10	36		T11	11		T13	5
values[4]	667	1			T12	6		T56	18		T176	1
values[5]	764	1			T13	29		T53	9		T238	1
values[6]	641	1			T238	1		T167	11		T153	11
values[7]	587	1			T7	1		T60	22		T153	12
values[8]	1120	1			T12	15		T53	22		T59	1
values[9]	109	1			T152	14		T45	13		T151	1
minimum	18224	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T144	1		T145	1		T40	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	12		T56	9		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	1		T2	15		T3	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	11		T216	7		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T175	3		T150	10		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T176	3		T162	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	11		T53	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	8		T11	3		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	5		T46	14		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	6		T56	9		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T238	1		T167	9		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	17		T53	3		T161	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T238	1		T153	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T167	11		T154	12		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T60	12		T153	1		T178	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	1		T146	1		T178	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T53	19		T175	10		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	15		T59	1		T161	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T151	1		T214	9		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T152	7		T45	13		T267	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18070	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	2		T40	1		T42	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T56	1		T148	7		T147	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T1	11		T3	21		T13	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T59	12		T216	13		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T175	2		T150	8		T249	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T176	5		T162	13		T269	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	10		T53	1		T189	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	7		T11	8		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	2		T46	13		T209	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T56	9		T154	2		T209	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	7		T270	10		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	12		T53	6		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T153	10		T146	12		T254	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T154	10		T189	8		T30	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T60	10		T153	11		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T146	6		T42	1		T237	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T53	3		T175	7		T153	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T161	15		T147	11		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T214	7		T266	14		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T152	7		T267	4		T271	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T268	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T5	10		T6	1		T8	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T147	1		T249	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T264	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	1		T145	1		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	12		T143	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T56	9		T59	11		T216	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	16		T13	2		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T176	3		T162	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	11		T175	3		T189	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	8		T13	2		T56	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T53	1		T143	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	3		T12	6		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T238	1		T167	9		T46	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T154	21		T160	1		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T238	1		T146	1		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	17		T53	3		T167	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	12		T153	1		T178	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	1		T154	12		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T175	10		T153	2		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	15		T59	1		T152	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17661	1			T5	150		T6	170		T8	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T53	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T147	11		T249	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T144	2		T40	1		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T148	7		T147	4		T26	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T1	11		T3	21		T173	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	1		T59	12		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T249	11		T272	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T176	5		T162	13		T273	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	10		T175	2		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	7		T13	3		T56	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T53	1		T38	2		T209	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	8		T56	9		T216	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	13		T49	7		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T154	2		T189	8		T161	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T146	12		T242	8		T254	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	12		T53	6		T28	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T60	10		T153	10		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T154	10		T146	6		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T175	7		T153	14		T148	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T152	7		T161	15		T149	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3