Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21476

1

T5

160

T6

171

T8

160

auto[ADC_CTRL_FILTER_COND_OUT]

5799

1

T1

12

T2

15

T3

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21109

1

T5

160

T6

171

T8

160

auto[1]

6166

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T216	20		T147	12		T348	19
values[0]	34	1			T253	32		T302	1		T349	1
values[1]	659	1			T7	1		T10	21		T13	29
values[2]	640	1			T176	1		T189	22		T150	26
values[3]	821	1			T10	15		T56	10		T148	16
values[4]	895	1			T11	12		T12	15		T59	23
values[5]	418	1			T41	12		T216	7		T167	11
values[6]	701	1			T146	7		T39	1		T147	5
values[7]	764	1			T13	5		T53	2		T56	18
values[8]	775	1			T12	22		T53	22		T144	3
values[9]	3301	1			T1	12		T2	15		T3	24
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T7	1		T10	21		T13	29
values[1]	2791	1			T1	12		T2	15		T3	24
values[2]	813	1			T10	15		T143	1		T153	12
values[3]	726	1			T11	12		T12	15		T59	23
values[4]	571	1			T41	12		T167	11		T161	30
values[5]	723	1			T56	18		T167	9		T148	8
values[6]	783	1			T12	16		T13	5		T53	2
values[7]	779	1			T12	6		T13	4		T53	22
values[8]	745	1			T238	1		T216	20		T144	9
values[9]	179	1			T53	9		T148	2		T45	25
minimum	18232	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	17		T42	2		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T7	1		T10	11		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T176	1		T46	14		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1510	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T143	1		T153	1		T189	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	8		T148	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	4		T59	11		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	15		T152	7		T60	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T161	15		T286	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	12		T167	11		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	9		T167	9		T177	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T148	1		T39	1		T149	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	16		T53	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	2		T146	1		T159	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	6		T144	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	2		T53	19		T56	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T216	7		T40	1		T150	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T238	1		T144	1		T175	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T148	1		T220	1		T214	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T53	3		T45	25		T163	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18070	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T350	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	12		T42	1		T242	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	10		T154	10		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	13		T150	13		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	930	1			T1	11		T3	21		T56	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T153	11		T189	10		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	7		T148	15		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	8		T59	12		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	7		T60	10		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T161	15		T286	2		T272	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T162	13		T149	8		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T56	9		T177	3		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T148	7		T249	14		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T53	1		T146	6		T189	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	3		T146	11		T275	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	2		T209	5		T163	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	2		T53	3		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T216	13		T40	1		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T144	8		T175	7		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T148	1		T214	11		T340	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T53	6		T163	7		T277	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T350	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T216	7		T348	10		T351	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T147	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T302	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T253	16		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	17		T238	1		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T10	11		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T176	1		T189	12		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T270	11		T30	8		T254	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T46	14		T178	6		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	8		T56	9		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	4		T59	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	15		T152	7		T60	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T216	4		T161	15		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	12		T167	11		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	1		T147	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	1		T162	1		T149	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T53	1		T56	9		T167	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	2		T148	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	22		T144	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T53	19		T175	3		T176	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T148	1		T40	1		T150	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1658	1			T1	1		T2	15		T3	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T216	13		T348	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T147	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	12		T42	1		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	10		T154	10		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T189	10		T150	13		T163	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T270	10		T30	6		T254	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T46	13		T26	12		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	7		T56	1		T148	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	8		T59	12		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T152	7		T60	10		T153	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T216	3		T161	15		T286	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	8		T26	7		T269	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	6		T147	4		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T162	13		T15	2		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T53	1		T56	9		T177	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	3		T148	7		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T144	2		T209	5		T273	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T53	3		T175	2		T176	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T148	1		T40	1		T150	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T1	11		T3	21		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	13		T42	2		T242	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T7	1		T10	11		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T176	1		T46	14		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T143	1		T153	12		T189	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	8		T148	16		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	10		T59	13		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T152	8		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T161	16		T286	3		T272	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	1		T167	1		T162	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T56	10		T167	1		T177	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T148	8		T39	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T53	2		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	4		T146	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	1		T144	3		T209	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	3		T53	4		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T216	14		T40	2		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T238	1		T144	9		T175	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T148	2		T220	1		T214	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T53	7		T45	2		T163	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18214	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T350	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	16		T42	1		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	10		T154	11		T30	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	13		T150	12		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1187	1			T2	14		T54	22		T55	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T189	11		T38	2		T178	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	7		T150	9		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T59	10		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	14		T152	6		T60	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T161	14		T274	5		T318	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	11		T167	10		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T56	8		T167	8		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	5		T249	12		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	15		T189	1		T161	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T159	9		T275	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	5		T273	4		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T53	18		T56	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T216	6		T150	14		T168	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T175	9		T178	13		T42	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T214	10		T340	6		T336	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T53	2		T45	23		T163	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T350	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T216	14		T348	10		T351	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T147	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T302	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T253	17		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	13		T238	1		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T10	11		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T176	1		T189	11		T150	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T270	11		T30	7		T254	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T46	14		T178	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	8		T56	2		T148	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	10		T59	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	1		T152	8		T60	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T216	4		T161	16		T286	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	1		T167	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	7		T147	5		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T39	1		T162	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T53	2		T56	10		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	4		T148	8		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T144	3		T209	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T53	4		T175	3		T176	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T148	2		T40	2		T150	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1409	1			T1	12		T2	1		T3	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T216	6		T348	9		T351	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T253	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	16		T42	1		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	10		T154	11		T256	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T189	11		T150	12		T163	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T270	10		T30	7		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	13		T178	5		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	7		T56	8		T256	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	2		T59	10		T154	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	14		T152	6		T60	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T216	3		T161	14		T274	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	11		T167	10		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T290	13		T318	10		T251	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T149	5		T15	1		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	8		T167	8		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T249	12		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	20		T273	4		T352	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T53	18		T175	2		T176	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T150	14		T168	2		T276	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1288	1			T2	14		T13	1		T53	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2