Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23588

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3687

1

T10

21

T11

12

T13

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21055

1

T5

160

T6

171

T8

160

auto[1]

6220

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	225	1			T11	1		T189	1		T242	3
values[0]	11	1			T320	1		T322	1		T323	9
values[1]	648	1			T11	11		T41	12		T53	9
values[2]	752	1			T216	20		T154	22		T45	12
values[3]	534	1			T10	15		T56	18		T59	23
values[4]	3080	1			T1	12		T2	15		T3	24
values[5]	612	1			T13	29		T53	22		T56	10
values[6]	736	1			T12	21		T13	4		T53	2
values[7]	633	1			T12	16		T167	11		T145	1
values[8]	717	1			T7	1		T13	5		T56	15
values[9]	1114	1			T144	9		T175	5		T153	12
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	563	1			T11	11		T41	12		T53	9
values[1]	729	1			T216	20		T154	22		T45	12
values[2]	623	1			T10	15		T56	18		T59	23
values[3]	2953	1			T1	12		T2	15		T3	24
values[4]	697	1			T13	4		T53	22		T56	10
values[5]	718	1			T12	37		T53	2		T152	14
values[6]	620	1			T59	1		T145	1		T153	11
values[7]	693	1			T7	1		T13	5		T56	15
values[8]	1034	1			T11	1		T144	9		T175	5
values[9]	177	1			T151	1		T286	3		T275	12
minimum	18468	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T147	1		T242	1		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	3		T41	12		T53	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	12		T45	12		T254	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T216	7		T39	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	8		T59	11		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	9		T238	1		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	11		T13	17		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T53	19		T56	9		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	2		T45	13		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	37		T53	1		T152	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	5		T42	2		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T59	1		T153	1		T169	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	1		T148	1		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T13	2		T56	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	1		T175	10		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T153	1		T30	8		T272	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	1		T144	1		T175	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T286	1		T243	8		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T151	1		T275	6		T17	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18124	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T238	1		T209	1		T178	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T147	11		T242	6		T272	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	8		T53	6		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	10		T254	4		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T216	13		T39	8		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	7		T59	12		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	9		T189	8		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	11		T3	21		T173	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	10		T13	12		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	3		T56	1		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	2		T162	13		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T53	1		T152	7		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	2		T42	1		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	10		T169	3		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T148	15		T46	13		T237	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	3		T56	8		T146	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	2		T175	7		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T153	11		T30	6		T272	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T144	8		T175	2		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T286	2		T243	11		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T275	6		T17	1		T345	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T176	5		T39	2		T42	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T209	5		T347	4		T345	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T272	1		T353	1		T340	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T11	1		T189	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T323	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T320	1		T322	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T167	9		T176	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	3		T41	12		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T154	12		T45	12		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T216	7		T39	11		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	8		T59	11		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T56	9		T238	1		T189	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T1	1		T2	15		T3	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	11		T176	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T53	19		T56	9		T177	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	17		T45	13		T269	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	21		T53	1		T152	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	2		T38	5		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	16		T167	11		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	1		T148	1		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T13	2		T56	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	1		T175	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T153	1		T146	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T144	1		T175	3		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T272	14		T250	2		T36	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T242	2		T280	8		T275	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T176	5		T147	11		T242	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	8		T53	6		T209	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T154	10		T272	10		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T216	13		T39	8		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	7		T59	12		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T56	9		T189	8		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T1	11		T3	21		T173	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	10		T153	3		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T53	3		T56	1		T177	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	12		T269	12		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T53	1		T152	7		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T38	2		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T153	10		T49	7		T150	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T148	15		T46	13		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	3		T56	8		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T144	2		T175	7		T148	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T153	11		T146	6		T26	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T144	8		T175	2		T146	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	12		T242	7		T272	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	9		T41	1		T53	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T154	11		T45	1		T254	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T216	14		T39	14		T147	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	8		T59	13		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T56	10		T238	1		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	11		T13	13		T153	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	4		T56	2		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	3		T45	1		T162	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	3		T53	2		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	5		T42	2		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T59	1		T153	11		T169	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T145	1		T148	16		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T13	4		T56	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T144	3		T175	8		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T153	12		T30	7		T272	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T11	1		T144	9		T175	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T286	3		T243	12		T250	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T151	1		T275	7		T17	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18274	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T238	1		T209	6		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T273	4		T171	11		T252	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	2		T41	11		T53	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	11		T45	11		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T216	6		T39	5		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	7		T59	10		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T56	8		T189	1		T178	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T2	14		T54	22		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	10		T13	16		T42	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T53	18		T56	8		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T45	12		T273	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	34		T152	6		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T38	2		T42	1		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T169	4		T218	15		T274	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T46	13		T255	8		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T56	6		T318	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T175	9		T149	5		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	7		T156	2		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T175	2		T161	14		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T243	7		T294	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T275	5		T17	1		T354	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T167	8		T176	2		T241	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T178	13		T169	6		T355	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T272	15		T353	1		T340	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	1		T189	1		T242	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T323	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T320	1		T322	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T167	1		T176	6		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	9		T41	1		T53	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T154	11		T45	1		T272	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T216	14		T39	14		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	8		T59	13		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T56	10		T238	1		T189	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T1	12		T2	1		T3	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T10	11		T176	1		T153	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T53	4		T56	2		T177	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	13		T45	1		T269	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	2		T53	2		T152	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	3		T38	5		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T167	1		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T145	1		T148	16		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T13	4		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T144	3		T175	8		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T153	12		T146	7		T26	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T144	9		T175	3		T146	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T36	19		T356	11		T294	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T280	8		T275	5		T340	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T323	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T167	8		T176	2		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	2		T41	11		T53	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T154	11		T45	11		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T216	6		T39	5		T326	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	7		T59	10		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T56	8		T189	1		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T2	14		T54	22		T55	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	10		T42	8		T270	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T53	18		T56	8		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	16		T45	12		T219	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	19		T152	6		T161	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T38	2		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	15		T167	10		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	13		T42	1		T169	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T56	6		T318	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T175	9		T149	5		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T30	7		T156	2		T219	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T175	2		T161	14		T47	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2