Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23963

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3312

1

T10

21

T11

11

T12

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21543

1

T5

160

T6

171

T8

160

auto[1]

5732

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	287	1			T56	10		T153	11		T146	12
values[0]	27	1			T15	3		T299	1		T300	23
values[1]	607	1			T59	1		T216	7		T144	3
values[2]	577	1			T10	15		T11	11		T12	16
values[3]	698	1			T12	6		T53	9		T56	15
values[4]	857	1			T7	1		T13	29		T41	12
values[5]	651	1			T10	21		T53	24		T56	18
values[6]	665	1			T144	9		T175	5		T38	7
values[7]	718	1			T12	15		T176	8		T160	1
values[8]	2951	1			T1	12		T2	15		T3	24
values[9]	1024	1			T11	1		T13	4		T146	13
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	621	1			T59	1		T216	7		T144	3
values[1]	635	1			T10	15		T11	11		T12	16
values[2]	689	1			T12	6		T53	9		T56	15
values[3]	950	1			T7	1		T10	21		T13	29
values[4]	491	1			T53	22		T238	1		T143	1
values[5]	742	1			T143	1		T144	9		T175	5
values[6]	2922	1			T1	12		T2	15		T3	24
values[7]	715	1			T11	1		T13	5		T148	16
values[8]	962	1			T13	4		T56	10		T153	11
values[9]	159	1			T146	12		T156	6		T239	1
minimum	18389	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T59	1		T216	4		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T153	1		T161	15		T45	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	8		T167	9		T60	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	3		T12	16		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T216	7		T167	11		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	6		T53	3		T56	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T7	1		T56	9		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	11		T13	17		T41	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	19		T238	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	1		T38	5		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T143	1		T175	3		T176	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T144	1		T150	10		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T1	1		T2	15		T3	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	15		T46	14		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T163	3		T254	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	2		T148	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	2		T56	9		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T153	1		T189	12		T47	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T299	1		T301	1		T357	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T146	1		T156	3		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18101	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	3		T237	1		T219	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T216	3		T144	2		T152	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T153	11		T161	15		T357	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	7		T60	10		T148	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	8		T154	10		T146	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T216	13		T153	3		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T53	6		T56	8		T59	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T56	9		T175	7		T42	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	10		T13	12		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T53	3		T161	7		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	2		T242	6		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T175	2		T176	5		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	8		T150	8		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T1	11		T3	21		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	13		T209	5		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T163	7		T254	9		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	3		T148	15		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T56	1		T272	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T153	10		T189	10		T47	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T301	1		T357	9		T36	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T146	11		T156	3		T306	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	2		T147	4		T209	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T237	14		T219	7		T300	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T56	9		T218	16		T280	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T153	1		T146	1		T156	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T15	3		T300	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T59	1		T216	4		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T153	1		T161	15		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	8		T167	9		T60	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	3		T12	16		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T167	11		T151	1		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	6		T53	3		T56	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T7	1		T216	7		T175	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	17		T41	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	19		T56	9		T238	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	11		T53	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T175	3		T147	1		T178	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T144	1		T38	5		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T176	3		T160	1		T149	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	15		T46	14		T270	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T1	1		T2	15		T3	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	2		T148	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	1		T13	2		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T146	1		T189	12		T47	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T56	1		T280	8		T275	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T153	10		T146	11		T156	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T216	3		T144	2		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T153	11		T161	15		T237	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	7		T60	10		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	8		T154	10		T146	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T242	2		T171	13		T337	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T53	6		T56	8		T59	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T216	13		T175	7		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	12		T40	1		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	3		T56	9		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	10		T53	1		T273	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T175	2		T147	11		T249	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	8		T38	2		T150	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T176	5		T150	13		T26	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T46	13		T270	10		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T1	11		T3	21		T173	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	3		T148	15		T162	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	2		T272	10		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T146	12		T189	10		T47	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T59	1		T216	4		T144	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T153	12		T161	16		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	8		T167	1		T60	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	9		T12	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T216	14		T167	1		T153	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T53	7		T56	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T7	1		T56	10		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	11		T13	13		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	4		T238	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	1		T38	5		T242	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T143	1		T175	3		T176	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	9		T150	9		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T1	12		T2	1		T3	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	1		T46	14		T209	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	1		T163	8		T254	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	4		T148	16		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	3		T56	2		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T153	11		T189	11		T47	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T299	1		T301	2		T357	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T146	12		T156	4		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18260	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T15	1		T237	15		T219	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T216	3		T152	6		T177	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T161	14		T45	11		T178	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	7		T167	8		T60	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	2		T12	15		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T216	6		T167	10		T273	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	5		T53	2		T56	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	8		T175	9		T42	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	10		T13	16		T41	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T53	18		T161	4		T178	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T38	2		T273	4		T252	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T175	2		T176	2		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T150	9		T15	1		T274	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T2	14		T54	22		T55	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	14		T46	13		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T163	2		T254	8		T180	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T256	26		T169	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T56	8		T218	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T189	11		T47	14		T49	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T357	10		T36	19		T303	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T156	2		T306	11		T358	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T204	12		T259	8		T311	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T15	2		T219	6		T300	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T56	2		T218	1		T280	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T153	11		T146	12		T156	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T15	1		T300	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T59	1		T216	4		T144	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	12		T161	16		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	8		T167	1		T60	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	9		T12	1		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T167	1		T151	1		T242	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T53	7		T56	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T7	1		T216	14		T175	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	13		T41	1		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T53	4		T56	10		T238	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	11		T53	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T175	3		T147	12		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	9		T38	5		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T176	6		T160	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T46	14		T270	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	12		T2	1		T3	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	4		T148	16		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	1		T13	3		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T146	13		T189	11		T47	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T56	8		T218	15		T280	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T156	2		T43	13		T306	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T15	2		T300	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T216	3		T152	6		T177	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T161	14		T45	11		T178	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	7		T167	8		T60	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	2		T12	15		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T167	10		T171	11		T52	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	5		T53	2		T56	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T216	6		T175	9		T42	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	16		T41	11		T258	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T53	18		T56	8		T161	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	10		T273	4		T307	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T175	2		T178	13		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	2		T150	9		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T176	2		T149	5		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	14		T46	13		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T2	14		T54	22		T55	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T149	8		T163	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T257	15		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T189	11		T47	14		T49	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2