Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23956

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3319

1

T10

36

T12

6

T13

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21711

1

T5

160

T6

171

T8

160

auto[1]

5564

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	321	1			T56	18		T148	8		T49	15
values[0]	6	1			T308	1		T313	2		T359	3
values[1]	842	1			T56	10		T59	23		T143	1
values[2]	829	1			T12	16		T238	1		T175	17
values[3]	738	1			T238	1		T60	22		T40	2
values[4]	621	1			T7	1		T41	12		T53	11
values[5]	2810	1			T1	12		T2	15		T3	24
values[6]	569	1			T11	11		T12	6		T53	22
values[7]	491	1			T10	15		T144	3		T152	14
values[8]	682	1			T10	21		T12	15		T13	5
values[9]	1153	1			T11	1		T13	33		T167	11
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T56	10		T148	16		T189	1
values[1]	810	1			T12	16		T238	2		T175	17
values[2]	751	1			T41	12		T53	9		T144	9
values[3]	2762	1			T1	12		T2	15		T3	24
values[4]	666	1			T53	22		T160	1		T189	10
values[5]	481	1			T10	15		T11	11		T12	6
values[6]	641	1			T12	15		T13	5		T144	3
values[7]	592	1			T10	21		T11	1		T216	20
values[8]	1134	1			T13	33		T56	18		T175	5
values[9]	190	1			T167	11		T360	1		T342	10
minimum	18515	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	1		T149	6		T26	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T56	9		T148	1		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	16		T150	15		T42	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T238	2		T175	10		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T41	12		T53	3		T154	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T144	1		T60	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	1		T56	7		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T160	1		T161	15		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	19		T189	2		T178	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	3		T152	7		T176	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	8		T12	6		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	15		T13	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T144	1		T176	1		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	1		T167	9		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	11		T216	7		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	2		T56	9		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T13	17		T175	3		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T167	11		T360	1		T221	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T342	10		T302	1		T316	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18135	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T59	11		T153	1		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	19		T30	6		T163	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T56	1		T148	15		T209	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T150	13		T42	10		T257	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T175	7		T286	2		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T53	6		T154	2		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T144	8		T60	10		T276	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T1	11		T3	21		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T53	1		T56	8		T237	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T161	15		T38	2		T162	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	3		T189	8		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	8		T152	7		T176	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T10	7		T146	6		T162	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	3		T147	11		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	2		T46	13		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	8		T272	10		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	10		T216	13		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	2		T56	9		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	12		T175	2		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T221	11		T361	13		T362	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T37	16		T311	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T146	11		T189	10		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T59	12		T153	11		T242	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T56	9		T148	1		T49	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T171	12		T352	14		T363	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T308	1		T359	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T143	1		T146	1		T189	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T56	9		T59	11		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	16		T42	13		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T238	1		T175	10		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	1		T150	15		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T238	1		T60	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T41	12		T53	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T53	1		T56	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T1	1		T2	15		T3	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T189	2		T178	14		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	3		T176	3		T177	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	6		T53	19		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	7		T147	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	8		T144	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	15		T13	2		T167	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	11		T216	7		T270	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	1		T13	2		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T13	17		T175	3		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T56	9		T148	7		T49	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T171	13		T229	12		T364	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	11		T189	10		T26	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T56	1		T59	12		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	10		T26	12		T30	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T175	7		T286	2		T273	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	1		T150	13		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T60	10		T254	4		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T53	6		T216	3		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T53	1		T56	8		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T1	11		T3	21		T173	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T189	8		T149	8		T254	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	8		T176	5		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T53	3		T146	6		T162	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	7		T147	4		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	7		T144	2		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	3		T147	11		T272	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	10		T216	13		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	2		T161	7		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	12		T175	2		T153	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T39	1		T149	1		T26	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T56	2		T148	16		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T150	14		T42	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T238	2		T175	8		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T41	1		T53	7		T154	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	9		T60	11		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	2		T56	9		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T160	1		T161	16		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T53	4		T189	9		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	9		T152	8		T176	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	8		T12	1		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T13	4		T147	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T144	3		T176	1		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	1		T167	1		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	11		T216	14		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	3		T56	10		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T13	13		T175	3		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T167	1		T360	1		T221	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T342	1		T302	1		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T59	13		T153	12		T242	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T149	5		T30	7		T163	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T56	8		T168	2		T290	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	15		T150	14		T42	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T175	9		T254	11		T273	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	11		T53	2		T154	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T60	11		T256	8		T276	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T2	14		T54	22		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T56	6		T156	2		T257	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T161	14		T38	2		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T53	18		T189	1		T178	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	2		T152	6		T176	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	7		T12	5		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	14		T13	1		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T46	13		T241	4		T344	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T167	8		T45	11		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	10		T216	6		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	1		T56	8		T161	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	16		T175	2		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T167	10		T221	6		T361	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T342	9		T316	12		T37	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T189	11		T256	18		T326	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T59	10		T251	1		T204	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T56	10		T148	8		T49	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T171	14		T352	1		T363	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T308	1		T359	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T313	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T143	1		T146	12		T189	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T56	2		T59	13		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T42	15		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T238	1		T175	8		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T40	2		T150	14		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T238	1		T60	11		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T41	1		T53	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T53	2		T56	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	12		T2	1		T3	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T189	9		T178	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	9		T176	6		T177	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	1		T53	4		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	8		T147	5		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	8		T144	3		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T13	4		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	11		T216	14		T270	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T11	1		T13	3		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	13		T175	3		T153	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T56	8		T49	7		T158	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T171	11		T352	13		T229	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T359	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T189	11		T149	5		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T56	8		T59	10		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	15		T42	8		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T175	9		T273	13		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T150	14		T42	1		T180	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	11		T254	11		T276	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	11		T53	2		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T56	6		T256	8		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T2	14		T54	22		T55	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T189	1		T178	13		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T176	2		T177	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	5		T53	18		T273	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T152	6		T150	9		T273	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T10	7		T45	12		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	14		T13	1		T167	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	10		T216	6		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	1		T167	10		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	16		T175	2		T154	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2