Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23640

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3635

1

T7

1

T10

15

T13

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21386

1

T5

160

T6

171

T7

1

auto[1]

5889

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	252	1			T7	1		T10	15		T59	1
values[0]	28	1			T182	3		T204	13		T328	2
values[1]	721	1			T53	9		T56	18		T167	11
values[2]	604	1			T144	3		T176	1		T146	13
values[3]	687	1			T13	29		T56	10		T60	22
values[4]	947	1			T12	15		T53	22		T216	7
values[5]	2960	1			T1	12		T2	15		T3	24
values[6]	748	1			T59	23		T144	9		T154	22
values[7]	495	1			T10	21		T11	1		T12	6
values[8]	633	1			T53	2		T56	15		T175	17
values[9]	987	1			T12	16		T143	1		T216	20
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T53	9		T56	18		T146	13
values[1]	537	1			T144	3		T167	11		T176	1
values[2]	922	1			T13	29		T56	10		T60	22
values[3]	3083	1			T1	12		T2	15		T3	24
values[4]	642	1			T11	11		T13	4		T238	1
values[5]	691	1			T10	21		T12	6		T41	12
values[6]	581	1			T11	1		T13	5		T53	2
values[7]	640	1			T56	15		T143	1		T153	15
values[8]	915	1			T7	1		T10	15		T12	16
values[9]	126	1			T151	1		T26	8		T318	11
minimum	18426	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T150	13		T243	8		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T53	3		T56	9		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	1		T167	11		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T177	2		T242	1		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T56	9		T145	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	17		T60	12		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T175	3		T150	10		T270	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	3		T13	2		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T167	9		T146	1		T161	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	11		T12	6		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	12		T153	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T53	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	2		T152	7		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	1		T153	2		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	7		T148	1		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	16		T216	7		T49	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	1		T10	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T253	16		T365	1		T366	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T151	1		T26	1		T318	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18102	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T28	1		T254	12		T159	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T150	13		T243	11		T309	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T53	6		T56	9		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T144	2		T161	15		T26	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T177	3		T242	8		T30	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	1		T146	11		T46	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	12		T60	10		T249	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T1	11		T3	21		T53	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T175	2		T150	8		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	8		T13	2		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T146	6		T161	7		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	10		T59	12		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T153	11		T38	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	1		T249	14		T300	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	3		T152	7		T175	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	13		T149	8		T42	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T56	8		T148	1		T149	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T216	13		T49	7		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	7		T189	8		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T253	16		T365	11		T366	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T26	7		T367	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T28	1		T254	4		T252	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T209	1		T242	1		T266	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T7	1		T10	8		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T182	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T204	13		T328	1		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T167	11		T160	1		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T53	3		T56	9		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	1		T176	1		T178	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	1		T177	2		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	9		T146	1		T161	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	17		T60	12		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	15		T53	19		T216	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	10		T249	1		T270	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T1	1		T2	15		T3	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T167	9		T175	3		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T59	11		T144	1		T154	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	1		T161	5		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	11		T11	1		T12	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	2		T41	12		T152	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	1		T153	1		T249	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T56	7		T175	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	16		T143	1		T216	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T189	2		T151	1		T15	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T209	3		T242	6		T266	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T10	7		T42	1		T26	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T328	1		T333	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T150	13		T243	11		T309	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T53	6		T56	9		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	2		T26	12		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	12		T177	3		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T56	1		T146	11		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	12		T60	10		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	3		T216	3		T176	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T150	8		T249	11		T270	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T1	11		T3	21		T11	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T175	2		T40	1		T163	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T59	12		T144	8		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	6		T161	7		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T10	10		T278	5		T368	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	3		T152	7		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T53	1		T153	3		T249	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T56	8		T175	7		T148	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T216	13		T153	10		T49	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T189	8		T272	10		T237	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T150	14		T243	12		T309	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T53	7		T56	10		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T144	3		T167	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T177	4		T242	9		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	2		T145	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T13	13		T60	11		T249	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T175	3		T150	9		T270	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	9		T13	3		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T167	1		T146	7		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	11		T12	1		T59	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	1		T153	12		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T53	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	4		T152	8		T175	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T143	1		T153	15		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	9		T148	2		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T216	14		T49	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T7	1		T10	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T253	17		T365	12		T366	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T151	1		T26	8		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18242	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T28	2		T254	5		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T150	12		T243	7		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	2		T56	8		T273	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T167	10		T161	14		T169	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T177	1		T30	7		T256	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T56	8		T46	13		T178	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	16		T60	11		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T2	14		T12	14		T53	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T175	2		T150	9		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	2		T13	1		T154	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T167	8		T161	4		T307	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	10		T12	5		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T41	11		T38	2		T326	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	12		T249	12		T304	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	1		T152	6		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T45	11		T149	11		T42	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T56	6		T149	8		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	15		T216	6		T49	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	7		T189	1		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T253	15		T311	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T318	10		T367	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T20	4		T332	8		T291	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T254	11		T159	9		T277	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T209	4		T242	7		T266	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	1		T10	8		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T182	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T204	1		T328	2		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T167	1		T160	1		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T53	7		T56	10		T147	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T144	3		T176	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T146	13		T177	4		T242	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	2		T146	12		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	13		T60	11		T237	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	1		T53	4		T216	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T150	9		T249	12		T270	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T1	12		T2	1		T3	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T167	1		T175	3		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T59	13		T144	9		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	7		T161	8		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	11		T11	1		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	4		T41	1		T152	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T53	2		T153	4		T249	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T56	9		T175	8		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T12	1		T143	1		T216	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T189	9		T151	1		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T369	5		T311	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T10	7		T42	1		T157	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T182	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T204	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T167	10		T150	12		T243	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	2		T56	8		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T178	5		T169	6		T204	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T177	1		T30	7		T256	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T56	8		T161	14		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	16		T60	11		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	14		T53	18		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	9		T270	10		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T2	14		T11	2		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	8		T175	2		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T59	10		T154	11		T189	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T161	4		T38	2		T326	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	10		T12	5		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	1		T41	11		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T249	12		T42	8		T274	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T56	6		T175	9		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	15		T216	6		T45	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T189	1		T15	2		T169	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2