Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23805

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3470

1

T12

37

T13

5

T41

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21127

1

T5

160

T6

171

T8

160

auto[1]

6148

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T237	3		T370	1		T273	32
values[0]	71	1			T150	28		T151	1		T16	18
values[1]	778	1			T53	22		T59	1		T143	1
values[2]	748	1			T7	1		T13	4		T56	10
values[3]	801	1			T10	21		T13	5		T53	9
values[4]	738	1			T12	15		T13	29		T238	1
values[5]	800	1			T10	15		T11	12		T56	15
values[6]	657	1			T144	9		T153	11		T146	12
values[7]	681	1			T143	1		T154	22		T189	1
values[8]	588	1			T12	6		T175	22		T176	1
values[9]	2964	1			T1	12		T2	15		T3	24
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T53	22		T143	1		T144	3
values[1]	863	1			T10	21		T13	4		T56	10
values[2]	677	1			T7	1		T13	5		T53	9
values[3]	776	1			T12	15		T13	29		T59	23
values[4]	860	1			T10	15		T11	12		T56	15
values[5]	644	1			T154	22		T146	12		T38	7
values[6]	2847	1			T1	12		T2	15		T3	24
values[7]	563	1			T53	2		T175	5		T160	1
values[8]	727	1			T12	16		T41	12		T56	18
values[9]	119	1			T42	23		T157	11		T239	1
minimum	18430	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T143	1		T144	1		T154	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	19		T152	7		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	11		T13	2		T39	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	9		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T162	1		T270	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	2		T53	3		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	17		T59	11		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	15		T167	20		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	8		T11	4		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T56	7		T60	12		T176	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	5		T39	1		T163	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T154	12		T146	1		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	1		T2	15		T3	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	6		T175	10		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T175	3		T45	13		T49	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T53	1		T160	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	9		T216	7		T249	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	16		T41	12		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T42	13		T157	6		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T301	1		T287	1		T371	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18109	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T59	1		T216	4		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	2		T154	2		T189	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	3		T152	7		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	10		T13	2		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T56	1		T146	6		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T162	7		T270	10		T155	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	3		T53	6		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	12		T59	12		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T161	15		T242	6		T286	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	7		T11	8		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T56	8		T60	10		T176	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	2		T163	7		T157	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T154	10		T146	11		T26	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T1	11		T3	21		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T175	7		T161	7		T40	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T175	2		T49	7		T286	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	1		T155	2		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T56	9		T216	13		T249	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T148	7		T189	8		T47	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T42	10		T157	5		T337	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T301	1		T287	12		T371	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T216	3		T209	5		T43	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	1		T370	1		T273	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T280	9		T52	6		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T204	13		T371	1		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T150	15		T151	1		T16	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T143	1		T144	1		T149	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T53	19		T59	1		T216	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	1		T13	2		T154	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T56	9		T146	1		T46	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	11		T162	1		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	2		T53	3		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	17		T238	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	15		T167	20		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	8		T11	4		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T56	7		T60	12		T176	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T144	1		T153	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	1		T242	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T143	1		T49	8		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T154	12		T189	1		T161	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T175	3		T176	1		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	6		T175	10		T40	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T1	1		T2	15		T3	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	16		T41	12		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T237	2		T273	18		T157	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T280	8		T52	1		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T109	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T150	13		T16	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	2		T149	8		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	3		T216	3		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T154	2		T189	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	1		T146	6		T46	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	10		T162	7		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	3		T53	6		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	12		T153	11		T177	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T161	15		T242	6		T286	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	7		T11	8		T59	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T56	8		T60	10		T176	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T144	8		T153	10		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	11		T242	2		T26	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	7		T147	4		T241	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T154	10		T161	7		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T175	2		T209	3		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T175	7		T40	1		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T1	11		T3	21		T56	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T53	1		T148	7		T189	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T143	1		T144	3		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	4		T152	8		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T10	11		T13	3		T39	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T56	2		T146	7		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T162	8		T270	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	4		T53	7		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	13		T59	13		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T167	2		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T10	8		T11	10		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T56	9		T60	11		T176	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T38	5		T39	1		T163	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T154	11		T146	12		T26	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T1	12		T2	1		T3	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T175	8		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T175	3		T45	1		T49	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	2		T160	1		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T56	10		T216	14		T249	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	1		T41	1		T148	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T42	15		T157	6		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T301	2		T287	13		T371	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18246	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T59	1		T216	4		T209	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T154	20		T189	11		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	18		T152	6		T46	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	10		T13	1		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T56	8		T178	5		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T270	10		T284	13		T304	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	1		T53	2		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	16		T59	10		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	14		T167	18		T161	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	7		T11	2		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	6		T60	11		T176	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	2		T163	2		T256	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T154	11		T256	8		T218	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T2	14		T54	22		T55	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	5		T175	9		T161	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T175	2		T45	12		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T221	7		T325	17		T319	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T56	8		T216	6		T249	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	15		T41	11		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T42	8		T157	5		T336	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T371	10		T372	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T251	1		T204	12		T303	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T216	3		T318	10		T43	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T237	3		T370	1		T273	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T280	9		T52	4		T301	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T204	1		T371	1		T109	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T150	14		T151	1		T16	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T143	1		T144	3		T149	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	4		T59	1		T216	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T13	3		T154	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T56	2		T146	7		T46	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	11		T162	8		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	4		T53	7		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	13		T238	1		T153	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T167	2		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	8		T11	10		T59	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T56	9		T60	11		T176	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T144	9		T153	11		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T146	12		T242	3		T26	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	1		T49	8		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T154	11		T189	1		T161	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T175	3		T176	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	1		T175	8		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T1	12		T2	1		T3	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	1		T41	1		T53	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T273	13		T157	5		T373	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T280	8		T52	3		T367	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T204	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	14		T16	4		T341	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	11		T42	1		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	18		T216	3		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T154	20		T189	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	8		T46	13		T178	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	10		T304	4		T257	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	1		T53	2		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	16		T177	1		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	14		T167	18		T161	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	7		T11	2		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T56	6		T60	11		T176	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	2		T163	2		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T218	15		T243	7		T355	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T49	7		T256	18		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T154	11		T161	4		T256	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T175	2		T45	11		T254	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	5		T175	9		T325	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T2	14		T54	22		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	15		T41	11		T189	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2