Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21457

1

T5

160

T6

171

T8

160

auto[ADC_CTRL_FILTER_COND_OUT]

5818

1

T1

12

T2

15

T3

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21129

1

T5

160

T6

171

T8

160

auto[1]

6146

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T238	1		T216	20		T175	17
values[0]	66	1			T253	32		T36	34		-	-
values[1]	543	1			T7	1		T10	21		T59	1
values[2]	748	1			T13	29		T176	1		T46	27
values[3]	784	1			T56	10		T148	16		T160	1
values[4]	842	1			T10	15		T11	12		T12	15
values[5]	508	1			T41	12		T216	7		T167	11
values[6]	655	1			T177	5		T39	1		T147	5
values[7]	783	1			T13	5		T53	2		T56	18
values[8]	744	1			T12	22		T144	3		T175	5
values[9]	3151	1			T1	12		T2	15		T3	24
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	659	1			T7	1		T10	21		T13	29
values[1]	2820	1			T1	12		T2	15		T3	24
values[2]	873	1			T10	15		T11	11		T143	1
values[3]	699	1			T11	1		T12	15		T59	23
values[4]	520	1			T41	12		T167	11		T161	30
values[5]	780	1			T13	5		T56	18		T148	8
values[6]	709	1			T12	16		T53	2		T167	9
values[7]	843	1			T12	6		T53	22		T56	15
values[8]	767	1			T13	4		T53	9		T238	1
values[9]	145	1			T45	12		T147	12		T163	10
minimum	18460	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	17		T238	1		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T10	11		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T176	1		T46	14		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1513	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	3		T143	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	8		T148	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	1		T59	11		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	15		T152	7		T60	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T161	15		T286	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T41	12		T167	11		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T56	9		T177	2		T189	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	2		T148	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	16		T53	1		T167	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T146	1		T159	10		T275	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	6		T144	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	19		T56	7		T175	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T216	7		T148	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	2		T53	3		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T340	7		T336	12		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T45	12		T147	1		T163	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18137	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T145	1		T154	12		T249	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	12		T243	11		T252	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	10		T146	12		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	13		T150	13		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T1	11		T3	21		T56	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	8		T153	11		T189	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	7		T148	15		T162	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	12		T216	3		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	7		T60	10		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	15		T286	2		T272	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T162	13		T149	8		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	9		T177	3		T189	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	3		T148	7		T249	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T53	1		T146	6		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	11		T275	6		T172	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T144	2		T209	5		T163	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	3		T56	8		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T216	13		T148	1		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	2		T53	6		T144	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T340	5		T37	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T147	11		T163	7		T277	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	2		T42	5		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T154	10		T249	11		T255	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T216	7		T348	10		T257	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T238	1		T175	10		T45	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T36	20		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T238	1		T42	2		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T10	11		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	17		T176	1		T46	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T270	11		T30	8		T254	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T189	12		T178	6		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T56	9		T148	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	4		T59	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	8		T12	15		T152	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T216	4		T161	15		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	12		T167	11		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T177	2		T147	1		T285	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	1		T162	1		T149	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T53	1		T56	9		T167	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	2		T148	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	22		T144	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T175	3		T176	3		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T148	1		T40	1		T150	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1605	1			T1	1		T2	15		T3	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T216	13		T348	9		T257	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T175	7		T42	10		T242	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T36	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T42	1		T118	6		T334	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	10		T154	10		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	12		T46	13		T150	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T270	10		T30	6		T254	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T189	10		T26	12		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T56	1		T148	15		T162	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	8		T59	12		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	7		T152	7		T60	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T216	3		T161	15		T286	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	8		T26	7		T269	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T177	3		T147	4		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T162	13		T15	2		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T53	1		T56	9		T146	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	3		T148	7		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T144	2		T209	5		T163	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T175	2		T176	5		T281	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T148	1		T40	1		T150	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	990	1			T1	11		T3	21		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	13		T238	1		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T10	11		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T176	1		T46	14		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1274	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	9		T143	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	8		T148	16		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	1		T59	13		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T152	8		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T161	16		T286	3		T272	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	1		T167	1		T162	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T56	10		T177	4		T189	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	4		T148	8		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T53	2		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T146	12		T159	1		T275	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	1		T144	3		T209	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T53	4		T56	9		T175	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T216	14		T148	2		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	3		T53	7		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T340	6		T336	1		T37	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T45	1		T147	12		T163	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18250	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T145	1		T154	11		T249	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	16		T15	2		T315	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	10		T30	7		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	13		T150	12		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1189	1			T2	14		T54	22		T55	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T189	11		T178	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	7		T150	9		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T59	10		T216	3		T154	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	14		T152	6		T60	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T161	14		T273	13		T274	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	11		T167	10		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T56	8		T177	1		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T149	5		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	15		T167	8		T161	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T159	9		T275	5		T16	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	5		T273	4		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	18		T56	6		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T216	6		T150	14		T168	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T53	2		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T340	6		T336	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T45	11		T163	2		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T42	1		T116	6		T183	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T154	11		T256	8		T255	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T216	14		T348	10		T257	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T238	1		T175	8		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T36	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T253	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T238	1		T42	2		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	1		T10	11		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	13		T176	1		T46	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T270	11		T30	7		T254	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T189	11		T178	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	2		T148	16		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	10		T59	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T10	8		T12	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T216	4		T161	16		T286	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T41	1		T167	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T177	4		T147	5		T285	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T39	1		T162	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T53	2		T56	10		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	4		T148	8		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T144	3		T209	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T175	3		T176	6		T281	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T148	2		T40	2		T150	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1342	1			T1	12		T2	1		T3	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T216	6		T348	9		T257	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T175	9		T45	11		T42	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T36	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T253	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T42	1		T15	2		T284	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	10		T154	11		T256	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	16		T46	13		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T270	10		T30	7		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T189	11		T178	5		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T56	8		T150	9		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	2		T59	10		T154	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	7		T12	14		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T216	3		T161	14		T273	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	11		T167	10		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T177	1		T290	13		T318	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	5		T15	1		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	8		T167	8		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T249	12		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	20		T273	4		T352	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T175	2		T176	2		T275	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T150	14		T168	2		T276	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T2	14		T13	1		T53	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2