Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T144	3		T145	1		T40	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T41	1		T56	2		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	12		T2	1		T3	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T59	13		T216	14		T177	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T175	3		T150	9		T249	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T176	6		T162	14		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	11		T53	2		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	8		T11	9		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T38	5		T46	14		T209	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T56	10		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T238	1		T167	1		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	13		T53	7		T161	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T238	1		T153	11		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T167	1		T154	11		T189	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T60	11		T153	12		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	1		T146	7		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T53	4		T175	8		T153	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T12	1		T59	1		T161	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T151	1		T214	8		T266	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T152	8		T45	1		T267	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18214	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T268	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T42	8		T274	5		T275	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	11		T56	8		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T2	14		T12	15		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	10		T216	6		T177	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T175	2		T150	9		T276	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T176	2		T256	18		T277	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	10		T189	11		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	7		T11	2		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	2		T46	13		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	5		T56	8		T154	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T167	8		T49	7		T270	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	16		T53	2		T161	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T254	11		T157	5		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T167	10		T154	11		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T60	11		T178	13		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T178	5		T42	1		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T53	18		T175	9		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	14		T161	14		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T214	8		T102	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T152	6		T45	12		T267	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T5	10		T6	1		T8	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T147	12		T249	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T264	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T144	3		T145	1		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	1		T143	1		T148	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T56	2		T59	13		T216	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T13	3		T249	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T176	6		T162	14		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	11		T175	3		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	8		T13	4		T56	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	2		T143	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	9		T12	1		T56	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T238	1		T167	1		T46	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T154	3		T160	1		T189	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T238	1		T146	13		T242	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	13		T53	7		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T60	11		T153	11		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	1		T154	11		T146	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T175	8		T153	16		T148	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T12	1		T59	1		T152	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17805	1			T5	150		T6	170		T8	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T53	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T274	5		T275	5		T278	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	11		T149	5		T256	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T2	14		T54	22		T55	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T56	8		T59	10		T216	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	15		T13	1		T254	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T176	2		T256	18		T273	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	10		T175	2		T189	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	7		T13	1		T56	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T38	2		T163	2		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	2		T12	5		T56	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T167	8		T46	13		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T154	20		T189	1		T161	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T254	11		T157	5		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	16		T53	2		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	11		T178	13		T257	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T154	11		T178	5		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T175	9		T149	11		T150	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	14		T152	6		T161	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2