Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23610

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3665

1

T7

1

T10

36

T11

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21017

1

T5

150

T6

170

T8

157

auto[1]

6258

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	796	1			T5	10		T6	1		T8	3
values[0]	2	1			T264	1		T279	1		-	-
values[1]	597	1			T41	12		T143	1		T144	3
values[2]	2916	1			T1	12		T2	15		T3	24
values[3]	806	1			T12	16		T13	4		T176	8
values[4]	661	1			T10	36		T13	5		T216	7
values[5]	601	1			T11	11		T12	6		T53	2
values[6]	801	1			T13	29		T238	1		T167	9
values[7]	603	1			T53	9		T238	1		T167	11
values[8]	691	1			T7	1		T60	22		T153	23
values[9]	996	1			T12	15		T53	22		T59	1
minimum	17805	1			T5	150		T6	170		T8	157

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	577	1			T41	12		T56	10		T143	1
values[1]	3111	1			T1	12		T2	15		T3	24
values[2]	679	1			T175	5		T176	8		T162	14
values[3]	612	1			T10	36		T13	5		T53	2
values[4]	690	1			T11	11		T12	6		T56	18
values[5]	768	1			T13	29		T53	9		T238	1
values[6]	575	1			T238	1		T167	11		T153	11
values[7]	657	1			T7	1		T60	22		T153	12
values[8]	1065	1			T12	15		T53	22		T59	1
values[9]	158	1			T45	13		T151	1		T43	31
minimum	18383	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T56	9		T146	1		T40	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	12		T143	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T1	1		T2	15		T3	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	16		T13	2		T59	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T249	1		T276	13		T280	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T175	3		T176	3		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T53	1		T143	1		T189	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	19		T13	2		T56	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T56	9		T176	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	3		T12	6		T154	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	17		T238	1		T167	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T53	3		T161	5		T270	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T238	1		T153	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T167	11		T154	12		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T60	12		T153	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	1		T178	20		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T12	15		T53	19		T175	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T59	1		T152	7		T161	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T151	1		T17	4		T214	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T45	13		T43	19		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18110	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T144	1		T189	1		T169	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	1		T146	11		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T148	7		T147	4		T26	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T1	11		T3	21		T173	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	2		T59	12		T216	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T249	11		T276	2		T280	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T175	2		T176	5		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T53	1		T189	10		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	17		T13	3		T56	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T56	9		T38	2		T46	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	8		T154	2		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	12		T49	7		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T53	6		T161	7		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	10		T146	12		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T154	10		T189	8		T30	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T60	10		T153	11		T146	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T42	1		T281	11		T169	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T53	3		T175	7		T153	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T152	7		T161	15		T149	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T17	1		T214	7		T267	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T43	12		T20	11		T282	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T144	2		T229	8		T283	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	522	1			T5	10		T6	1		T8	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T45	13		T284	14		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T264	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	1		T40	4		T42	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	12		T143	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T59	11		T216	7		T177	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T249	1		T285	1		T254	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	16		T13	2		T176	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T189	12		T26	1		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	19		T13	2		T216	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	1		T56	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	3		T12	6		T56	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	17		T238	1		T167	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T154	21		T160	1		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T238	1		T146	1		T157	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	3		T167	11		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T60	12		T153	2		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	1		T154	12		T178	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	15		T53	19		T175	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	1		T152	7		T161	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17661	1			T5	150		T6	170		T8	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T153	3		T147	11		T214	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T287	12		T288	1		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	1		T42	10		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	2		T148	7		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	11		T3	21		T56	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	12		T216	13		T177	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T249	11		T254	9		T276	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	2		T176	5		T39	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T189	10		T26	12		T286	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	17		T13	3		T216	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T53	1		T56	9		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	8		T56	8		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	12		T46	13		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T154	2		T189	8		T161	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T146	12		T157	5		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	6		T28	1		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T60	10		T153	21		T146	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T154	10		T42	1		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T53	3		T175	7		T148	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T152	7		T161	15		T149	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T56	2		T146	12		T40	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	1		T143	1		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T1	12		T2	1		T3	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T12	1		T13	3		T59	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T249	12		T276	3		T280	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T175	3		T176	6		T162	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T53	2		T143	1		T189	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	19		T13	4		T56	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T56	10		T176	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	9		T12	1		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	13		T238	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T53	7		T161	8		T270	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T238	1		T153	11		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	1		T154	11		T189	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T60	11		T153	12		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	1		T178	2		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T12	1		T53	4		T175	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T59	1		T152	8		T161	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	1		T17	4		T214	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T45	1		T43	18		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18246	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T144	3		T189	1		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	8		T42	8		T256	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T41	11		T149	5		T275	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T2	14		T54	22		T55	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	15		T13	1		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T276	12		T280	8		T290	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T175	2		T176	2		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T189	11		T163	2		T180	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	17		T13	1		T56	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T56	8		T38	2		T46	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	2		T12	5		T154	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	16		T167	8		T49	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	2		T161	4		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T157	5		T159	9		T204	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T167	10		T154	11		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T60	11		T150	14		T257	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T178	18		T42	1		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	14		T53	18		T175	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	6		T161	14		T149	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T17	1		T214	8		T222	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T45	12		T43	13		T291	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T292	15		T293	15		T294	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T169	6		T283	5		T295	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	547	1			T5	10		T6	1		T8	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T45	1		T284	1		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T264	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T145	1		T40	5		T42	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T41	1		T143	1		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T59	13		T216	14		T177	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T249	12		T285	1		T254	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	1		T13	3		T176	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T189	11		T26	13		T286	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	19		T13	4		T216	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T53	2		T56	10		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	9		T12	1		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	13		T238	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T154	3		T160	1		T189	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T238	1		T146	13		T157	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	7		T167	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T60	11		T153	23		T146	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T154	11		T178	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	1		T53	4		T175	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T59	1		T152	8		T161	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17805	1			T5	150		T6	170		T8	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T214	8		T222	15		T296	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T45	12		T284	13		T288	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	8		T256	8		T274	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	11		T149	5		T169	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T2	14		T54	22		T55	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T59	10		T216	6		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T254	8		T218	15		T276	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	15		T13	1		T176	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T189	11		T180	10		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	17		T13	1		T216	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T56	8		T38	2		T163	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	2		T12	5		T56	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	16		T167	8		T46	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T154	20		T189	1		T161	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T157	5		T159	9		T204	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	2		T167	10		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	11		T150	14		T257	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T154	11		T178	18		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	14		T53	18		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T152	6		T161	14		T149	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2