Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23968

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3307

1

T10

36

T12

6

T13

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21739

1

T5

160

T6

171

T8

160

auto[1]

5536

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T167	11		T266	12		-	-
values[0]	41	1			T146	12		T248	1		T308	1
values[1]	747	1			T59	23		T143	1		T153	12
values[2]	896	1			T12	16		T56	10		T238	1
values[3]	684	1			T238	1		T60	22		T146	13
values[4]	680	1			T7	1		T41	12		T53	11
values[5]	2787	1			T1	12		T2	15		T3	24
values[6]	635	1			T10	15		T11	11		T12	6
values[7]	445	1			T216	20		T144	3		T152	14
values[8]	757	1			T10	21		T12	15		T13	5
values[9]	1367	1			T11	1		T13	33		T56	18
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	971	1			T56	10		T59	23		T143	1
values[1]	820	1			T12	16		T238	2		T175	17
values[2]	804	1			T41	12		T53	9		T144	9
values[3]	2715	1			T1	12		T2	15		T3	24
values[4]	646	1			T53	22		T160	1		T189	10
values[5]	468	1			T11	11		T12	6		T152	14
values[6]	719	1			T10	15		T12	15		T13	5
values[7]	542	1			T10	21		T11	1		T167	9
values[8]	1139	1			T13	29		T56	18		T175	5
values[9]	185	1			T13	4		T167	11		T161	12
minimum	18266	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T143	1		T146	1		T189	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T56	9		T59	11		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	16		T150	15		T42	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T238	2		T175	10		T151	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T41	12		T53	3		T154	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	1		T60	12		T256	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T53	1		T56	7		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T53	19		T160	1		T161	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T189	2		T178	14		T149	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	3		T152	7		T176	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	6		T146	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	15		T13	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	8		T216	7		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	1		T167	9		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	11		T154	12		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T56	9		T148	1		T49	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T13	17		T175	3		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T13	2		T167	11		T161	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T202	1		T299	1		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T155	1		T248	1		T204	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T146	11		T189	10		T26	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T56	1		T59	12		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T150	13		T42	10		T309	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T175	7		T286	2		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T53	6		T154	2		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	8		T60	10		T310	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T1	11		T3	21		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T53	1		T56	8		T237	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T53	3		T161	15		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T189	8		T149	8		T254	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	8		T152	7		T176	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T146	6		T162	7		T26	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T147	11		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	7		T216	13		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T39	8		T272	10		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	10		T154	10		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T56	9		T148	7		T49	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	12		T175	2		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T13	2		T161	7		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T37	16		T311	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T155	2		T312	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T167	11		T266	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T146	1		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T248	1		T313	1		T193	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T143	1		T189	12		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T59	11		T153	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	16		T40	1		T42	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T56	9		T238	1		T175	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	1		T150	15		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T238	1		T60	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	1		T41	12		T53	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	1		T56	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T1	1		T2	15		T3	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T189	2		T178	14		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	3		T53	19		T176	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	8		T12	6		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T152	7		T147	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T216	7		T144	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	15		T13	2		T167	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	11		T154	12		T270	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T11	1		T13	2		T56	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T13	17		T175	3		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T266	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T146	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T313	1		T193	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T189	10		T26	7		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T59	12		T153	11		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T40	1		T42	10		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T56	1		T175	7		T286	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T146	12		T150	13		T242	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	10		T254	4		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T53	6		T216	3		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T53	1		T56	8		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T1	11		T3	21		T173	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T189	8		T149	8		T254	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	8		T53	3		T176	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T10	7		T146	6		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T152	7		T147	4		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T216	13		T144	2		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	3		T147	11		T272	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	10		T154	10		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T13	2		T56	9		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T13	12		T175	2		T153	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T143	1		T146	12		T189	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T56	2		T59	13		T153	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T150	14		T42	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T238	2		T175	8		T151	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T41	1		T53	7		T154	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	9		T60	11		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T53	2		T56	9		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T53	4		T160	1		T161	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T189	9		T178	1		T149	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	9		T152	8		T176	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T146	7		T162	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	1		T13	4		T147	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	8		T216	14		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T167	1		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	11		T154	11		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T56	10		T148	8		T49	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	13		T175	3		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T13	3		T167	1		T161	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T202	1		T299	1		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T155	3		T248	1		T204	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T189	11		T149	5		T30	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	8		T59	10		T168	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	15		T150	14		T42	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T175	9		T254	11		T273	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T41	11		T53	2		T154	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T60	11		T256	8		T314	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	14		T54	22		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T56	6		T156	2		T257	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	18		T161	14		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T189	1		T178	13		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T152	6		T176	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T12	5		T273	1		T315	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	14		T13	1		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	7		T216	6		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T167	8		T45	11		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	10		T154	11		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	8		T49	7		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	16		T175	2		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T13	1		T167	10		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T316	12		T37	16		T311	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T204	12		T263	11		T317	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T167	1		T266	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T146	12		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	1		T313	2		T193	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T143	1		T189	11		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T59	13		T153	12		T148	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	1		T40	2		T42	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T56	2		T238	1		T175	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T146	13		T150	14		T242	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T238	1		T60	11		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	1		T41	1		T53	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	2		T56	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T1	12		T2	1		T3	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T189	9		T178	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	9		T53	4		T176	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	8		T12	1		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	8		T147	5		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T216	14		T144	3		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	1		T13	4		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	11		T154	11		T270	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T11	1		T13	3		T56	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T13	13		T175	3		T153	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T167	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T193	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T189	11		T149	5		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T59	10		T168	2		T290	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	15		T42	8		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T56	8		T175	9		T273	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	14		T180	17		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T60	11		T254	11		T318	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T41	11		T53	2		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	6		T256	8		T257	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T2	14		T54	22		T55	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T189	1		T178	13		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	2		T53	18		T176	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	7		T12	5		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T152	6		T150	9		T273	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T216	6		T46	13		T255	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	14		T13	1		T167	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	10		T154	11		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	1		T56	8		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	16		T175	2		T47	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2