Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23599

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3676

1

T10

21

T11

12

T13

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21054

1

T5

160

T6

171

T8

160

auto[1]

6221

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T153	12		T319	11		-	-
values[0]	50	1			T320	1		T321	23		T322	1
values[1]	630	1			T11	11		T41	12		T53	9
values[2]	665	1			T154	22		T45	12		T39	19
values[3]	617	1			T10	15		T56	18		T238	1
values[4]	3022	1			T1	12		T2	15		T3	24
values[5]	671	1			T13	29		T53	22		T56	10
values[6]	721	1			T12	21		T13	4		T148	8
values[7]	655	1			T12	16		T53	2		T167	11
values[8]	702	1			T13	5		T56	15		T59	1
values[9]	1306	1			T7	1		T11	1		T144	9
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	841	1			T11	11		T41	12		T53	9
values[1]	690	1			T56	18		T216	20		T154	22
values[2]	662	1			T10	15		T59	23		T238	1
values[3]	2934	1			T1	12		T2	15		T3	24
values[4]	725	1			T13	4		T53	22		T56	10
values[5]	693	1			T12	21		T53	2		T167	11
values[6]	574	1			T12	16		T59	1		T145	1
values[7]	707	1			T7	1		T13	5		T56	15
values[8]	925	1			T11	1		T175	5		T153	12
values[9]	310	1			T144	9		T151	1		T286	3
minimum	18214	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T167	9		T176	3		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	3		T41	12		T53	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T154	12		T45	12		T254	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	9		T216	7		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	8		T59	11		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T238	1		T176	1		T189	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	11		T13	17		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T53	19		T56	9		T152	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	2		T45	13		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	21		T53	1		T167	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T38	5		T42	2		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	16		T59	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T145	1		T148	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T13	2		T56	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	1		T175	10		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T153	1		T26	1		T30	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T11	1		T175	3		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T286	1		T257	30		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T144	1		T151	1		T275	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T176	5		T147	11		T242	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	8		T53	6		T209	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T154	10		T254	4		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	9		T216	13		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	7		T59	12		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T189	8		T42	10		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	11		T3	21		T173	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	10		T13	12		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T53	3		T56	1		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	2		T162	13		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	1		T161	7		T49	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	2		T42	1		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	10		T169	3		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T148	15		T237	14		T281	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	3		T56	8		T146	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T144	2		T175	7		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T153	11		T26	12		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T175	2		T146	11		T161	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T286	2		T257	27		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T144	8		T275	6		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T153	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T321	10		T323	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	1		T322	1		T324	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T167	9		T176	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	3		T41	12		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T154	12		T45	12		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	11		T147	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	8		T143	2		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T56	9		T238	1		T216	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T1	1		T2	15		T3	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	11		T176	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T53	19		T56	9		T152	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	17		T45	13		T15	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	21		T148	1		T161	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	2		T38	5		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	16		T53	1		T167	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	1		T148	1		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	2		T56	7		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	1		T175	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T7	1		T146	1		T30	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T11	1		T144	1		T175	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T153	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T321	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T324	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T176	5		T147	11		T242	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	8		T53	6		T209	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T154	10		T272	10		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	8		T147	4		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	7		T216	3		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T56	9		T216	13		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T1	11		T3	21		T59	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	10		T153	3		T189	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	3		T56	1		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	12		T15	2		T269	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	7		T161	7		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	2		T38	2		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T53	1		T153	10		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T148	15		T46	13		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	3		T56	8		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	2		T175	7		T148	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T146	6		T30	7		T286	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T144	8		T175	2		T146	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T167	1		T176	6		T147	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	9		T41	1		T53	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T154	11		T45	1		T254	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T56	10		T216	14		T39	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	8		T59	13		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T238	1		T176	1		T189	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	11		T13	13		T153	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	4		T56	2		T152	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	3		T45	1		T162	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	2		T53	2		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	5		T42	2		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T59	1		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	1		T148	16		T237	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T13	4		T56	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T144	3		T175	8		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T153	12		T26	13		T30	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T11	1		T175	3		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T286	3		T257	29		T250	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T144	9		T151	1		T275	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T167	8		T176	2		T273	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	2		T41	11		T53	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	11		T45	11		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	8		T216	6		T39	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	7		T59	10		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T189	1		T178	5		T42	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T2	14		T54	22		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	10		T13	16		T43	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T53	18		T56	8		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T45	12		T273	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	19		T167	10		T161	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	2		T42	1		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	15		T169	4		T218	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T182	2		T204	2		T283	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T56	6		T318	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T175	9		T46	13		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	7		T156	2		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T175	2		T161	14		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T257	28		T325	17		T294	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T275	5		T17	1		T204	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T153	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T319	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T321	14		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T320	1		T322	1		T324	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T167	1		T176	6		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	9		T41	1		T53	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T154	11		T45	1		T272	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	14		T147	5		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	8		T143	2		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	10		T238	1		T216	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	12		T2	1		T3	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T10	11		T176	1		T153	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T53	4		T56	2		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	13		T45	1		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	2		T148	8		T161	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	3		T38	5		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T53	2		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	1		T148	16		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	4		T56	9		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T144	3		T175	8		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T7	1		T146	7		T30	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	450	1			T11	1		T144	9		T175	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T319	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T321	9		T323	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T167	8		T176	2		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T41	11		T53	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	11		T45	11		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T39	5		T326	11		T277	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	7		T216	3		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T56	8		T216	6		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	14		T54	22		T55	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	10		T189	1		T42	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T53	18		T56	8		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	16		T45	12		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	19		T161	4		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T38	2		T273	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	15		T167	10		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	13		T42	1		T168	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T56	6		T318	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T175	9		T149	5		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	7		T156	2		T219	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T175	2		T161	14		T47	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2