Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23494

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3781

1

T7

1

T10

15

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21414

1

T5

160

T6

171

T8

160

auto[1]

5861

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T180	14		T327	6		-	-
values[0]	57	1			T277	27		T328	2		T20	10
values[1]	695	1			T53	9		T56	18		T167	11
values[2]	594	1			T144	3		T176	1		T146	13
values[3]	662	1			T13	29		T56	10		T60	22
values[4]	968	1			T12	15		T53	22		T216	7
values[5]	2976	1			T1	12		T2	15		T3	24
values[6]	751	1			T59	23		T144	9		T154	22
values[7]	469	1			T10	21		T11	1		T12	6
values[8]	633	1			T53	2		T56	15		T175	17
values[9]	1237	1			T7	1		T10	15		T12	16
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	845	1			T53	9		T56	18		T146	13
values[1]	543	1			T144	3		T167	11		T176	1
values[2]	923	1			T12	15		T13	29		T53	22
values[3]	3060	1			T1	12		T2	15		T3	24
values[4]	678	1			T11	11		T13	4		T238	1
values[5]	677	1			T10	21		T41	12		T59	23
values[6]	545	1			T11	1		T12	6		T53	2
values[7]	722	1			T13	5		T56	15		T143	1
values[8]	728	1			T7	1		T10	15		T12	16
values[9]	272	1			T49	15		T209	4		T151	1
minimum	18282	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T150	13		T159	10		T290	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T53	3		T56	9		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	1		T167	11		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T177	2		T161	15		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	15		T53	19		T56	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	17		T60	12		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T1	1		T2	15		T3	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T175	3		T150	10		T270	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	3		T13	2		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T167	9		T148	1		T154	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	11		T59	11		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	12		T153	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	1		T53	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	6		T175	10		T47	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	2		T56	7		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T189	2		T149	9		T15	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	16		T40	4		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T10	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T49	8		T209	1		T329	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T151	1		T26	1		T275	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18082	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T277	12		T330	1		T331	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T150	13		T290	13		T243	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T53	6		T56	9		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	2		T26	12		T269	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T177	3		T161	15		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T53	3		T56	1		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	12		T60	10		T249	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T1	11		T3	21		T173	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T175	2		T150	8		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	8		T13	2		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T148	15		T154	2		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	10		T59	12		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T153	11		T38	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T53	1		T152	7		T249	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T175	7		T47	15		T209	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	3		T56	8		T153	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T189	8		T149	8		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	1		T162	7		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	7		T216	13		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T49	7		T209	3		T329	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T26	7		T275	6		T253	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T277	15		T331	13		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T180	14		T327	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T328	1		T20	8		T332	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T277	12		T333	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T167	11		T150	13		T159	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T53	3		T56	9		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	1		T176	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	1		T177	2		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T56	9		T146	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	17		T60	12		T161	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	15		T53	19		T216	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T160	1		T150	10		T249	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T1	1		T2	15		T3	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T167	9		T175	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T59	11		T144	1		T154	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T146	1		T161	5		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T10	11		T11	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	6		T41	12		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T53	1		T56	7		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T175	10		T149	9		T158	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	16		T143	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T7	1		T10	8		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T328	1		T20	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T277	15		T333	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T150	13		T290	13		T243	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	6		T56	9		T26	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T144	2		T26	12		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	12		T177	3		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T56	1		T146	11		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	12		T60	10		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T53	3		T216	3		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T150	8		T249	11		T270	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T1	11		T3	21		T11	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T175	2		T148	15		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T59	12		T144	8		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	6		T161	7		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T10	10		T13	3		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T153	11		T47	15		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	1		T56	8		T153	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T175	7		T149	8		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T153	10		T49	7		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T10	7		T216	13		T189	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T150	14		T159	1		T290	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T53	7		T56	10		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	3		T167	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T177	4		T161	16		T242	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T53	4		T56	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T13	13		T60	11		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	12		T2	1		T3	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T175	3		T150	9		T270	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	9		T13	3		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T167	1		T148	16		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	11		T59	13		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	1		T153	12		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	1		T53	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T175	8		T47	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	4		T56	9		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T189	9		T149	9		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T40	5		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T10	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T49	8		T209	4		T329	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T151	1		T26	8		T275	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18228	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T277	16		T330	1		T331	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	12		T159	9		T290	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	2		T56	8		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T167	10		T169	6		T280	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T177	1		T161	14		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	14		T53	18		T56	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	16		T60	11		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T2	14		T54	22		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T175	2		T150	9		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	2		T13	1		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T167	8		T154	20		T161	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	10		T59	10		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T41	11		T38	2		T326	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T152	6		T45	12		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	5		T175	9		T47	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T56	6		T45	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T189	1		T149	8		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	15		T178	13		T273	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	7		T216	6		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T49	7		T329	14		T311	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T275	5		T318	10		T253	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T291	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T180	1		T327	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T328	2		T20	6		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T277	16		T333	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T167	1		T150	14		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T53	7		T56	10		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	3		T176	1		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T146	13		T177	4		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	2		T146	12		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	13		T60	11		T161	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T53	4		T216	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T160	1		T150	9		T249	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T1	12		T2	1		T3	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T167	1		T175	3		T148	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T59	13		T144	9		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T146	7		T161	8		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	11		T11	1		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T41	1		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T53	2		T56	9		T153	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T175	8		T149	9		T158	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T12	1		T143	1		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	424	1			T7	1		T10	8		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T180	13		T327	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T20	4		T332	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T167	10		T150	12		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	2		T56	8		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T169	6		T280	8		T204	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T177	1		T30	7		T256	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T56	8		T178	5		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	16		T60	11		T161	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	14		T53	18		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	9		T270	10		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T2	14		T11	2		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T167	8		T175	2		T154	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T59	10		T154	11		T189	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T161	4		T180	10		T326	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T10	10		T13	1		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	5		T41	11		T47	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T56	6		T45	12		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T175	9		T149	8		T158	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	15		T45	11		T49	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	7		T216	6		T189	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2