Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23735

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3540

1

T12

37

T13

5

T41

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21043

1

T5

160

T6

171

T8

160

auto[1]

6232

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T239	1		T334	10		T335	1
values[0]	104	1			T150	28		T151	1		T16	18
values[1]	743	1			T53	22		T59	1		T143	1
values[2]	718	1			T7	1		T13	4		T56	10
values[3]	788	1			T10	21		T13	5		T53	9
values[4]	742	1			T12	15		T13	29		T238	2
values[5]	789	1			T10	15		T11	12		T56	15
values[6]	758	1			T144	9		T153	11		T146	12
values[7]	593	1			T143	1		T154	22		T189	1
values[8]	646	1			T12	6		T175	22		T176	1
values[9]	3159	1			T1	12		T2	15		T3	24
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T53	22		T143	1		T216	7
values[1]	853	1			T7	1		T10	21		T13	4
values[2]	698	1			T13	5		T53	9		T238	1
values[3]	832	1			T12	15		T13	29		T59	23
values[4]	816	1			T10	15		T11	12		T56	15
values[5]	690	1			T154	22		T146	12		T189	1
values[6]	2836	1			T1	12		T2	15		T3	24
values[7]	557	1			T53	2		T175	5		T160	1
values[8]	701	1			T12	16		T41	12		T56	18
values[9]	125	1			T47	30		T15	10		T239	1
minimum	18234	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T143	1		T144	1		T154	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T53	19		T216	4		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	1		T10	11		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T56	9		T146	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	2		T270	11		T285	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	2		T53	3		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	17		T59	11		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	15		T167	11		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	8		T11	4		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T56	7		T144	1		T60	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	5		T39	1		T163	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T154	12		T146	1		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T1	1		T2	15		T3	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	6		T143	1		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T175	3		T45	13		T286	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T53	1		T160	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T56	9		T216	7		T249	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	16		T41	12		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T239	1		T336	9		T334	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T47	15		T15	8		T337	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18089	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T144	2		T154	2		T146	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	3		T216	3		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	10		T13	2		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T56	1		T146	6		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T162	20		T270	10		T155	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	3		T53	6		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	12		T59	12		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T161	15		T242	6		T274	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	7		T11	8		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T56	8		T144	8		T60	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	2		T163	7		T157	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	10		T146	11		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T1	11		T3	21		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T175	7		T161	7		T40	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T175	2		T286	10		T272	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	1		T155	2		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	9		T216	13		T249	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	7		T189	8		T26	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T334	9		T313	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T47	15		T15	2		T337	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	2		T42	4		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T239	1		T334	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T335	1		T338	3		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T16	10		T251	3		T331	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T150	15		T151	1		T339	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T59	1		T143	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T53	19		T216	4		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T13	2		T154	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T56	9		T146	1		T39	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	11		T162	1		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	2		T53	3		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	17		T238	1		T167	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	15		T238	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	8		T11	4		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	7		T167	11		T60	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T153	1		T38	5		T163	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	1		T146	1		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	1		T147	1		T241	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	1		T154	12		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T175	3		T176	1		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	6		T175	10		T40	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T1	1		T2	15		T3	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	16		T41	12		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T334	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T338	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T16	8		T251	1		T331	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T150	13		T338	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T144	2		T146	12		T189	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T53	3		T216	3		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	2		T154	2		T150	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	1		T146	6		T39	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	10		T162	7		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	3		T53	6		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	12		T153	11		T177	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	1		T161	15		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	7		T11	8		T59	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T56	8		T60	10		T176	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	10		T38	2		T163	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T144	8		T146	11		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T147	4		T241	8		T253	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	10		T161	7		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T175	2		T49	7		T209	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T175	7		T40	1		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T1	11		T3	21		T56	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T53	1		T148	7		T189	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T143	1		T144	3		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T53	4		T216	4		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T10	11		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T56	2		T146	7		T39	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T162	22		T270	11		T285	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	4		T53	7		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	13		T59	13		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T167	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	8		T11	10		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T56	9		T144	9		T60	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	5		T39	1		T163	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T154	11		T146	12		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T1	12		T2	1		T3	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T143	1		T175	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T175	3		T45	1		T286	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T53	2		T160	1		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T56	10		T216	14		T249	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T41	1		T148	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	1		T336	1		T334	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T47	16		T15	7		T337	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18221	1			T5	160		T6	171		T8	160
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T154	20		T189	11		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	18		T216	3		T152	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	10		T13	1		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T56	8		T39	5		T178	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T270	10		T284	13		T304	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T53	2		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	16		T59	10		T167	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	14		T167	10		T161	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T10	7		T11	2		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T56	6		T60	11		T176	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	2		T163	2		T256	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	11		T256	8		T218	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T2	14		T54	22		T55	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	5		T175	9		T161	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T175	2		T45	12		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T221	7		T325	17		T319	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	8		T216	6		T249	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	15		T41	11		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T336	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T47	14		T15	3		T340	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T17	1		T185	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T239	1		T334	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T335	1		T338	7		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T16	14		T251	3		T331	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T150	14		T151	1		T339	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T59	1		T143	1		T144	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	4		T216	4		T152	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T13	3		T154	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T56	2		T146	7		T39	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	11		T162	8		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	4		T53	7		T153	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	13		T238	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T238	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	8		T11	10		T59	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T56	9		T167	1		T60	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T153	11		T38	5		T163	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T144	9		T146	12		T242	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	1		T147	5		T241	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	1		T154	11		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T175	3		T176	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	1		T175	8		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T1	12		T2	1		T3	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T12	1		T41	1		T53	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T338	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T16	4		T251	1		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	14		T338	4		T341	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T189	11		T149	11		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	18		T216	3		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T154	20		T178	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	8		T39	5		T178	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	10		T270	10		T304	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	1		T53	2		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	16		T167	8		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	14		T161	14		T274	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	7		T11	2		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T56	6		T167	10		T60	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	2		T163	2		T256	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T218	15		T171	11		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T241	4		T253	15		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	11		T161	4		T256	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T175	2		T45	11		T49	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	5		T175	9		T325	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T2	14		T54	22		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	15		T41	11		T189	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2