Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27275

1

T1

12

T2

15

T3

24

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24052

1

T1

12

T2

15

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3223

1

T10

15

T11

11

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21174

1

T5

160

T6

171

T8

160

auto[1]

6101

1

T1

12

T2

15

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23047

1

T1

1

T2

15

T3

3

auto[1]

4228

1

T1

11

T3

21

T10

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T53	9		T144	3		T152	14
values[0]	24	1			T250	3		T260	21		-	-
values[1]	801	1			T13	5		T41	12		T175	17
values[2]	2823	1			T1	12		T2	15		T3	24
values[3]	734	1			T11	1		T12	6		T144	9
values[4]	788	1			T10	36		T53	22		T56	15
values[5]	819	1			T145	1		T153	11		T189	22
values[6]	566	1			T12	16		T13	4		T59	1
values[7]	767	1			T56	10		T176	8		T45	12
values[8]	667	1			T12	15		T59	23		T238	1
values[9]	844	1			T7	1		T13	29		T216	7
minimum	18213	1			T5	160		T6	171		T8	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T13	5		T41	12		T238	1
values[1]	2912	1			T1	12		T2	15		T3	24
values[2]	776	1			T10	21		T11	1		T53	24
values[3]	806	1			T10	15		T56	15		T216	20
values[4]	743	1			T13	4		T145	1		T153	11
values[5]	583	1			T12	16		T56	10		T59	1
values[6]	761	1			T12	15		T238	1		T176	8
values[7]	626	1			T59	23		T216	7		T60	22
values[8]	754	1			T7	1		T13	29		T152	14
values[9]	200	1			T53	9		T144	3		T272	15
minimum	18444	1			T5	160		T6	171		T8	160

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

3881

1

T2

14

T10

17

T11

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T41	12		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T143	1		T153	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T1	1		T2	15		T3	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	3		T12	6		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T10	11		T11	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T53	20		T154	21		T163	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T56	7		T216	7		T154	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	8		T146	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	2		T153	1		T45	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T145	1		T189	12		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	16		T56	9		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	11		T148	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	15		T238	1		T176	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	12		T162	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T59	11		T60	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T216	4		T176	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T47	15		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	17		T152	7		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T53	3		T144	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T240	1		T222	16		T244	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18108	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T146	1		T157	6		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	3		T175	7		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T153	11		T148	7		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T1	11		T3	21		T56	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	8		T49	7		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	10		T144	8		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T53	4		T154	2		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T56	8		T216	13		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	7		T146	6		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T153	10		T30	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T189	10		T147	4		T249	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T56	1		T175	2		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T148	15		T149	8		T242	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T176	5		T40	1		T209	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T162	7		T163	1		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	12		T60	10		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T216	3		T39	8		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	15		T40	1		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	12		T152	7		T46	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T53	6		T144	2		T272	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T240	6		T244	5		T245	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	2		T42	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T146	11		T157	5		T247	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T53	3		T144	1		T40	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T152	7		T150	15		T342	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T250	1		T260	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	2		T41	12		T175	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T153	1		T146	2		T161	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T1	1		T2	15		T3	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	3		T53	1		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T144	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	6		T154	21		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	11		T56	7		T216	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	8		T53	19		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	1		T45	13		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T145	1		T189	12		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	16		T13	2		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T167	11		T148	1		T249	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T56	9		T176	3		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	12		T149	9		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	15		T59	11		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T176	1		T160	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T60	12		T47	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	17		T216	4		T46	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T53	6		T144	2		T40	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T152	7		T150	13		T343	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T250	2		T260	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	3		T175	7		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T153	11		T146	23		T161	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T1	11		T3	21		T56	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	8		T53	1		T148	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T144	8		T148	1		T189	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T154	2		T163	2		T281	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	10		T56	8		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	7		T53	3		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T153	10		T169	9		T241	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T189	10		T147	4		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	2		T175	2		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T148	15		T249	14		T286	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T56	1		T176	5		T209	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T149	8		T242	6		T163	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T59	12		T153	3		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T162	7		T249	11		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T60	10		T47	15		T209	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	12		T216	3		T46	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T42	4		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	4		T41	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T143	1		T153	12		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	12		T2	1		T3	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	9		T12	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	11		T11	1		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	6		T154	3		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T56	9		T216	14		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	8		T146	7		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	3		T153	11		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T145	1		T189	11		T147	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T56	2		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T167	1		T148	16		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T12	1		T238	1		T176	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	1		T162	8		T163	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T59	13		T60	11		T153	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T216	4		T176	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	1		T47	16		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	13		T152	8		T46	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T53	7		T144	3		T272	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T240	7		T222	1		T244	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18303	1			T5	160		T6	171		T8	160
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T146	12		T157	6		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T41	11		T175	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T161	4		T163	2		T168	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T2	14		T54	22		T55	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	2		T12	5		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	10		T189	1		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	18		T154	20		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T56	6		T216	6		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	7		T42	1		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T45	12		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T189	11		T249	12		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	15		T56	8		T167	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T167	10		T149	8		T256	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	14		T176	2		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	11		T243	2		T257	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T59	10		T60	11		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T216	3		T39	5		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T47	14		T178	5		T256	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	16		T152	6		T46	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T53	2		T257	13		T344	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T222	15		T244	4		T259	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T273	13		T294	4		T338	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T157	5		T183	2		T345	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T53	7		T144	3		T40	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	8		T150	14		T342	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T250	3		T260	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	4		T41	1		T175	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T153	12		T146	25		T161	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T1	12		T2	1		T3	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T53	2		T143	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T144	9		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T154	3		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T10	11		T56	9		T216	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	8		T53	4		T146	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T153	11		T45	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T145	1		T189	11		T147	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	1		T13	3		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T167	1		T148	16		T249	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T56	2		T176	6		T209	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	1		T149	9		T242	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T59	13		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	1		T160	1		T162	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T60	11		T47	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	13		T216	4		T46	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18213	1			T5	160		T6	171		T8	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T53	2		T344	14		T346	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T152	6		T150	14		T342	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T260	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T41	11		T175	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T161	4		T168	2		T157	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T2	14		T54	22		T55	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	2		T49	7		T42	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T189	1		T254	11		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	5		T154	20		T163	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	10		T56	6		T216	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	7		T53	18		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	12		T15	2		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T189	11		T255	8		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	15		T13	1		T167	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T167	10		T249	12		T256	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T56	8		T176	2		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	11		T149	8		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	14		T59	10		T177	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T156	2		T263	11		T347	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T60	11		T47	14		T178	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	16		T216	3		T46	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23394

1

T1

12

T2

1

T3

24

auto[1]

auto[0]

3881

1

T2

14

T10

17

T11

2