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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.32


Total test records in report: 919
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T790 /workspace/coverage/default/16.adc_ctrl_poweron_counter.1577568211 Aug 11 06:41:31 PM PDT 24 Aug 11 06:41:38 PM PDT 24 2770626079 ps
T791 /workspace/coverage/default/9.adc_ctrl_filters_polled.1668216447 Aug 11 06:40:52 PM PDT 24 Aug 11 06:43:53 PM PDT 24 326588766552 ps
T792 /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1949408493 Aug 11 06:42:02 PM PDT 24 Aug 11 06:48:19 PM PDT 24 165515379629 ps
T793 /workspace/coverage/default/34.adc_ctrl_stress_all.2300273664 Aug 11 06:42:43 PM PDT 24 Aug 11 06:54:27 PM PDT 24 613500434393 ps
T137 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.752690251 Aug 11 06:22:46 PM PDT 24 Aug 11 06:22:49 PM PDT 24 2492405535 ps
T71 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2765332099 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:06 PM PDT 24 717844788 ps
T72 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.208362052 Aug 11 06:22:58 PM PDT 24 Aug 11 06:23:00 PM PDT 24 666145306 ps
T794 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4230904203 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:57 PM PDT 24 334879033 ps
T73 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1329393216 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:59 PM PDT 24 429453601 ps
T124 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.880037851 Aug 11 06:22:54 PM PDT 24 Aug 11 06:22:55 PM PDT 24 474804857 ps
T125 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3796945432 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:37 PM PDT 24 654496279 ps
T64 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3877724320 Aug 11 06:22:52 PM PDT 24 Aug 11 06:22:58 PM PDT 24 4329135909 ps
T138 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.511034330 Aug 11 06:22:42 PM PDT 24 Aug 11 06:22:44 PM PDT 24 513562062 ps
T83 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2218780856 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:03 PM PDT 24 393751972 ps
T68 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3429429003 Aug 11 06:22:56 PM PDT 24 Aug 11 06:23:00 PM PDT 24 4461020613 ps
T77 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3807134791 Aug 11 06:22:56 PM PDT 24 Aug 11 06:23:00 PM PDT 24 544823793 ps
T795 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3131580130 Aug 11 06:22:59 PM PDT 24 Aug 11 06:23:00 PM PDT 24 519999766 ps
T84 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.640398710 Aug 11 06:22:59 PM PDT 24 Aug 11 06:23:01 PM PDT 24 445742758 ps
T796 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2670533908 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:59 PM PDT 24 322421354 ps
T126 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2824593283 Aug 11 06:22:59 PM PDT 24 Aug 11 06:23:00 PM PDT 24 576650888 ps
T797 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2102807496 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:57 PM PDT 24 530556633 ps
T139 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2016564318 Aug 11 06:23:02 PM PDT 24 Aug 11 06:23:03 PM PDT 24 357591742 ps
T798 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2396326075 Aug 11 06:23:02 PM PDT 24 Aug 11 06:23:03 PM PDT 24 539029005 ps
T67 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2863094954 Aug 11 06:22:52 PM PDT 24 Aug 11 06:22:54 PM PDT 24 464974952 ps
T78 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.797803849 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:59 PM PDT 24 411910165 ps
T93 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.81849265 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:59 PM PDT 24 557902663 ps
T799 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1080231918 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:59 PM PDT 24 345008458 ps
T79 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1559318550 Aug 11 06:22:58 PM PDT 24 Aug 11 06:23:02 PM PDT 24 551351312 ps
T65 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2030837038 Aug 11 06:22:36 PM PDT 24 Aug 11 06:23:37 PM PDT 24 26597249596 ps
T66 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1615682197 Aug 11 06:23:09 PM PDT 24 Aug 11 06:23:21 PM PDT 24 2534657343 ps
T140 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1568456364 Aug 11 06:22:53 PM PDT 24 Aug 11 06:22:54 PM PDT 24 503375520 ps
T800 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2635132963 Aug 11 06:22:40 PM PDT 24 Aug 11 06:22:42 PM PDT 24 720226524 ps
T801 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2901692135 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:58 PM PDT 24 528992083 ps
T802 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4006271059 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:42 PM PDT 24 580045087 ps
T803 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3987494619 Aug 11 06:22:35 PM PDT 24 Aug 11 06:22:36 PM PDT 24 415199955 ps
T804 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.138237906 Aug 11 06:22:38 PM PDT 24 Aug 11 06:22:40 PM PDT 24 428063604 ps
T805 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3204567012 Aug 11 06:23:05 PM PDT 24 Aug 11 06:23:06 PM PDT 24 450175541 ps
T806 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3444017368 Aug 11 06:22:35 PM PDT 24 Aug 11 06:22:37 PM PDT 24 440847452 ps
T69 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2113618741 Aug 11 06:22:38 PM PDT 24 Aug 11 06:22:50 PM PDT 24 8156016717 ps
T127 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4104832199 Aug 11 06:22:46 PM PDT 24 Aug 11 06:22:47 PM PDT 24 378528999 ps
T807 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2945198845 Aug 11 06:23:03 PM PDT 24 Aug 11 06:23:05 PM PDT 24 327254612 ps
T70 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.860281603 Aug 11 06:22:51 PM PDT 24 Aug 11 06:23:03 PM PDT 24 4396657619 ps
T808 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2127963669 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:38 PM PDT 24 2563565872 ps
T809 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4250153421 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:57 PM PDT 24 570694671 ps
T810 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.860729321 Aug 11 06:23:09 PM PDT 24 Aug 11 06:23:10 PM PDT 24 345046005 ps
T811 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3297087414 Aug 11 06:23:07 PM PDT 24 Aug 11 06:23:08 PM PDT 24 326588022 ps
T812 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.189482426 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:05 PM PDT 24 421200076 ps
T74 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.749172541 Aug 11 06:22:59 PM PDT 24 Aug 11 06:23:06 PM PDT 24 4357621693 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1797191953 Aug 11 06:22:55 PM PDT 24 Aug 11 06:22:57 PM PDT 24 557365908 ps
T128 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2991863564 Aug 11 06:22:38 PM PDT 24 Aug 11 06:22:41 PM PDT 24 893265017 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1818639002 Aug 11 06:22:55 PM PDT 24 Aug 11 06:22:56 PM PDT 24 308293210 ps
T374 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3917212303 Aug 11 06:22:57 PM PDT 24 Aug 11 06:23:18 PM PDT 24 8239177363 ps
T375 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1230397080 Aug 11 06:22:38 PM PDT 24 Aug 11 06:23:00 PM PDT 24 8796585521 ps
T815 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2201987487 Aug 11 06:22:39 PM PDT 24 Aug 11 06:22:40 PM PDT 24 735976733 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3631746061 Aug 11 06:22:58 PM PDT 24 Aug 11 06:23:01 PM PDT 24 2152523771 ps
T817 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.754980592 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:53 PM PDT 24 335517288 ps
T818 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2926044264 Aug 11 06:22:52 PM PDT 24 Aug 11 06:22:57 PM PDT 24 4111157019 ps
T819 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3742585879 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:05 PM PDT 24 323702207 ps
T820 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4276975138 Aug 11 06:23:08 PM PDT 24 Aug 11 06:23:09 PM PDT 24 332381910 ps
T821 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.329379776 Aug 11 06:23:10 PM PDT 24 Aug 11 06:23:13 PM PDT 24 419470964 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3870192679 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:59 PM PDT 24 544918584 ps
T129 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3190739144 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:02 PM PDT 24 535162086 ps
T823 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3236438846 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:59 PM PDT 24 499857127 ps
T824 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3083888702 Aug 11 06:22:50 PM PDT 24 Aug 11 06:22:52 PM PDT 24 341483812 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3358913777 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:46 PM PDT 24 4932492322 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3066300230 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:06 PM PDT 24 490032145 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2187447055 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:42 PM PDT 24 783989093 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3305803184 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:38 PM PDT 24 443257795 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1532893878 Aug 11 06:22:39 PM PDT 24 Aug 11 06:22:40 PM PDT 24 404859956 ps
T829 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3756272356 Aug 11 06:23:10 PM PDT 24 Aug 11 06:23:11 PM PDT 24 368756697 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.579551638 Aug 11 06:22:58 PM PDT 24 Aug 11 06:23:00 PM PDT 24 461018195 ps
T831 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1170153821 Aug 11 06:23:02 PM PDT 24 Aug 11 06:23:03 PM PDT 24 460515453 ps
T832 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2479389357 Aug 11 06:22:53 PM PDT 24 Aug 11 06:22:53 PM PDT 24 535120339 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2972868310 Aug 11 06:22:57 PM PDT 24 Aug 11 06:23:02 PM PDT 24 4628805846 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4126810949 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:39 PM PDT 24 464048462 ps
T835 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.61780692 Aug 11 06:23:00 PM PDT 24 Aug 11 06:23:01 PM PDT 24 321907927 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1256430874 Aug 11 06:22:45 PM PDT 24 Aug 11 06:22:48 PM PDT 24 549092495 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2894899834 Aug 11 06:22:34 PM PDT 24 Aug 11 06:22:36 PM PDT 24 952898331 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1602559075 Aug 11 06:23:00 PM PDT 24 Aug 11 06:23:04 PM PDT 24 2528575048 ps
T376 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.839004772 Aug 11 06:22:40 PM PDT 24 Aug 11 06:22:48 PM PDT 24 8313351938 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.963670639 Aug 11 06:22:57 PM PDT 24 Aug 11 06:23:00 PM PDT 24 364757482 ps
T840 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3597098007 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:45 PM PDT 24 4859517715 ps
T841 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4028007363 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:55 PM PDT 24 525811775 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1483105398 Aug 11 06:22:40 PM PDT 24 Aug 11 06:22:51 PM PDT 24 4380946844 ps
T843 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.878378001 Aug 11 06:23:07 PM PDT 24 Aug 11 06:23:08 PM PDT 24 500356925 ps
T844 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2259169704 Aug 11 06:23:16 PM PDT 24 Aug 11 06:23:21 PM PDT 24 3827532356 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1430369612 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:42 PM PDT 24 520526755 ps
T131 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3511904209 Aug 11 06:22:52 PM PDT 24 Aug 11 06:22:54 PM PDT 24 312801821 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3598957080 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:40 PM PDT 24 379358278 ps
T132 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.802033160 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:38 PM PDT 24 389771826 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1278981704 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:53 PM PDT 24 472624172 ps
T848 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.837040056 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:44 PM PDT 24 4740672534 ps
T849 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1196388835 Aug 11 06:23:05 PM PDT 24 Aug 11 06:23:08 PM PDT 24 373319963 ps
T850 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1094132687 Aug 11 06:22:57 PM PDT 24 Aug 11 06:23:09 PM PDT 24 5019899705 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1828008351 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:38 PM PDT 24 504740554 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1790168703 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:57 PM PDT 24 356401296 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3524870893 Aug 11 06:22:44 PM PDT 24 Aug 11 06:22:46 PM PDT 24 490337007 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.412992363 Aug 11 06:22:52 PM PDT 24 Aug 11 06:23:02 PM PDT 24 3963881778 ps
T854 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1662828813 Aug 11 06:23:03 PM PDT 24 Aug 11 06:23:04 PM PDT 24 492737205 ps
T134 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.500186010 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:58 PM PDT 24 394554959 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1080935228 Aug 11 06:22:39 PM PDT 24 Aug 11 06:22:44 PM PDT 24 1565292648 ps
T856 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3628572103 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:52 PM PDT 24 506609441 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.570137240 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:06 PM PDT 24 428674018 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1726329603 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:52 PM PDT 24 510667247 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2689185886 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:49 PM PDT 24 8764343660 ps
T860 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3589247830 Aug 11 06:23:07 PM PDT 24 Aug 11 06:23:08 PM PDT 24 533809922 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2584919782 Aug 11 06:22:39 PM PDT 24 Aug 11 06:22:45 PM PDT 24 2415752249 ps
T862 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.966915440 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:06 PM PDT 24 409146101 ps
T135 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4008343519 Aug 11 06:22:53 PM PDT 24 Aug 11 06:22:56 PM PDT 24 1219786407 ps
T863 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3398495691 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:02 PM PDT 24 355966143 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2033579763 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:43 PM PDT 24 386261097 ps
T136 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1709206533 Aug 11 06:22:35 PM PDT 24 Aug 11 06:24:55 PM PDT 24 40498740273 ps
T865 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.138141564 Aug 11 06:22:38 PM PDT 24 Aug 11 06:22:44 PM PDT 24 8586158124 ps
T866 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4216618770 Aug 11 06:22:58 PM PDT 24 Aug 11 06:22:59 PM PDT 24 331633650 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.451115273 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:58 PM PDT 24 353097712 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2364950843 Aug 11 06:22:37 PM PDT 24 Aug 11 06:24:41 PM PDT 24 25974620982 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2450902317 Aug 11 06:22:31 PM PDT 24 Aug 11 06:22:32 PM PDT 24 603356693 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2906091599 Aug 11 06:22:38 PM PDT 24 Aug 11 06:22:41 PM PDT 24 420265764 ps
T871 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1162425711 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:02 PM PDT 24 458899149 ps
T872 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3524551764 Aug 11 06:22:33 PM PDT 24 Aug 11 06:22:35 PM PDT 24 653099760 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1975022624 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:05 PM PDT 24 508040414 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1378435842 Aug 11 06:23:03 PM PDT 24 Aug 11 06:23:18 PM PDT 24 5026773087 ps
T875 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1380009603 Aug 11 06:23:06 PM PDT 24 Aug 11 06:23:07 PM PDT 24 445696034 ps
T876 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1497373181 Aug 11 06:22:31 PM PDT 24 Aug 11 06:24:02 PM PDT 24 23168788831 ps
T877 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3029418753 Aug 11 06:23:06 PM PDT 24 Aug 11 06:23:07 PM PDT 24 405884892 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2746187313 Aug 11 06:22:58 PM PDT 24 Aug 11 06:22:59 PM PDT 24 331998414 ps
T85 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3783141115 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:45 PM PDT 24 9393313176 ps
T879 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.855110793 Aug 11 06:23:11 PM PDT 24 Aug 11 06:23:12 PM PDT 24 567661757 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.894880377 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:39 PM PDT 24 572712876 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3596231860 Aug 11 06:22:51 PM PDT 24 Aug 11 06:22:54 PM PDT 24 2453969134 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1319236566 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:39 PM PDT 24 1184785128 ps
T883 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3469262646 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:03 PM PDT 24 447988112 ps
T86 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2059403026 Aug 11 06:22:55 PM PDT 24 Aug 11 06:23:03 PM PDT 24 8481540074 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2684271108 Aug 11 06:22:48 PM PDT 24 Aug 11 06:22:50 PM PDT 24 686331483 ps
T885 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2844310678 Aug 11 06:22:45 PM PDT 24 Aug 11 06:22:47 PM PDT 24 332016584 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.118270556 Aug 11 06:22:54 PM PDT 24 Aug 11 06:22:55 PM PDT 24 459626019 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.259708660 Aug 11 06:22:54 PM PDT 24 Aug 11 06:23:07 PM PDT 24 8645949360 ps
T888 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2980585095 Aug 11 06:22:58 PM PDT 24 Aug 11 06:22:59 PM PDT 24 391418286 ps
T889 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2504790481 Aug 11 06:22:56 PM PDT 24 Aug 11 06:23:14 PM PDT 24 4622447085 ps
T890 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3649059056 Aug 11 06:22:37 PM PDT 24 Aug 11 06:22:38 PM PDT 24 324164337 ps
T891 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.213929667 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:59 PM PDT 24 335085932 ps
T892 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.386232252 Aug 11 06:23:05 PM PDT 24 Aug 11 06:23:06 PM PDT 24 542535964 ps
T893 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1914407740 Aug 11 06:23:04 PM PDT 24 Aug 11 06:23:05 PM PDT 24 396158239 ps
T894 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3366936299 Aug 11 06:23:12 PM PDT 24 Aug 11 06:23:14 PM PDT 24 351968049 ps
T895 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1578269611 Aug 11 06:22:39 PM PDT 24 Aug 11 06:22:41 PM PDT 24 359546025 ps
T896 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2866972107 Aug 11 06:22:59 PM PDT 24 Aug 11 06:23:02 PM PDT 24 1082584772 ps
T897 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.855419424 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:58 PM PDT 24 500079189 ps
T898 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.923863267 Aug 11 06:22:41 PM PDT 24 Aug 11 06:22:43 PM PDT 24 575647004 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3012063947 Aug 11 06:23:11 PM PDT 24 Aug 11 06:23:17 PM PDT 24 4897126134 ps
T900 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3080729830 Aug 11 06:23:05 PM PDT 24 Aug 11 06:23:07 PM PDT 24 438120314 ps
T901 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3248120346 Aug 11 06:22:55 PM PDT 24 Aug 11 06:23:06 PM PDT 24 3917764099 ps
T902 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1935305229 Aug 11 06:22:51 PM PDT 24 Aug 11 06:23:37 PM PDT 24 52036448257 ps
T903 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1371363370 Aug 11 06:22:57 PM PDT 24 Aug 11 06:22:58 PM PDT 24 500008582 ps
T904 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.819833790 Aug 11 06:23:15 PM PDT 24 Aug 11 06:23:22 PM PDT 24 2348278246 ps
T905 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2437395109 Aug 11 06:22:49 PM PDT 24 Aug 11 06:22:53 PM PDT 24 605414269 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1180827786 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:46 PM PDT 24 4115640723 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1582372658 Aug 11 06:22:47 PM PDT 24 Aug 11 06:22:51 PM PDT 24 4580904489 ps
T908 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4166504533 Aug 11 06:23:01 PM PDT 24 Aug 11 06:23:04 PM PDT 24 600351816 ps
T909 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1720604130 Aug 11 06:23:06 PM PDT 24 Aug 11 06:23:07 PM PDT 24 472029207 ps
T910 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1137445553 Aug 11 06:22:44 PM PDT 24 Aug 11 06:22:46 PM PDT 24 467833062 ps
T911 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2807808276 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:40 PM PDT 24 9154742503 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.998305564 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:42 PM PDT 24 8073374879 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2753948569 Aug 11 06:22:57 PM PDT 24 Aug 11 06:23:01 PM PDT 24 8432689968 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.956185394 Aug 11 06:22:36 PM PDT 24 Aug 11 06:22:39 PM PDT 24 1334451635 ps
T915 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3274300399 Aug 11 06:22:35 PM PDT 24 Aug 11 06:22:37 PM PDT 24 311007571 ps
T916 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3740606551 Aug 11 06:22:56 PM PDT 24 Aug 11 06:22:58 PM PDT 24 513273465 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3706874184 Aug 11 06:22:42 PM PDT 24 Aug 11 06:22:44 PM PDT 24 435338213 ps
T918 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.480102750 Aug 11 06:23:06 PM PDT 24 Aug 11 06:23:07 PM PDT 24 306253334 ps
T919 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1588859117 Aug 11 06:23:08 PM PDT 24 Aug 11 06:23:09 PM PDT 24 309839272 ps

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.794154975
Short name T10
Test name
Test status
Simulation time 339166404706 ps
CPU time 156.49 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:44:17 PM PDT 24
Peak memory 201416 kb
Host smart-535a69f9-7aba-476b-b020-72101b153edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794154975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
794154975
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1806151820
Short name T8
Test name
Test status
Simulation time 116926274027 ps
CPU time 441.62 seconds
Started Aug 11 06:44:47 PM PDT 24
Finished Aug 11 06:52:09 PM PDT 24
Peak memory 201832 kb
Host smart-fce11ce3-94cb-4d70-b116-ef9f7e4b712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806151820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1806151820
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2844552379
Short name T56
Test name
Test status
Simulation time 510044285095 ps
CPU time 277.55 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:45:34 PM PDT 24
Peak memory 201444 kb
Host smart-c6b3798e-3382-40b9-b522-e4b9985017c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844552379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2844552379
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3235867993
Short name T15
Test name
Test status
Simulation time 343847511342 ps
CPU time 142.46 seconds
Started Aug 11 06:42:14 PM PDT 24
Finished Aug 11 06:44:37 PM PDT 24
Peak memory 217820 kb
Host smart-20870ce8-f502-464a-bb1a-0955b27558f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235867993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3235867993
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3382026497
Short name T13
Test name
Test status
Simulation time 505716210220 ps
CPU time 620.85 seconds
Started Aug 11 06:43:39 PM PDT 24
Finished Aug 11 06:54:00 PM PDT 24
Peak memory 201480 kb
Host smart-c0d0f6e6-e956-4d78-9b87-7deaf49469ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382026497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3382026497
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2456135482
Short name T150
Test name
Test status
Simulation time 530521693440 ps
CPU time 107.58 seconds
Started Aug 11 06:43:15 PM PDT 24
Finished Aug 11 06:45:02 PM PDT 24
Peak memory 201500 kb
Host smart-e42dbe1a-09a0-45c1-a5df-dfb7e66f3f94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456135482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2456135482
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.127365302
Short name T189
Test name
Test status
Simulation time 509663310854 ps
CPU time 279.35 seconds
Started Aug 11 06:41:53 PM PDT 24
Finished Aug 11 06:46:32 PM PDT 24
Peak memory 201440 kb
Host smart-ea4d435a-0e31-499c-998c-ae2452e2e23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127365302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
127365302
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2344316884
Short name T53
Test name
Test status
Simulation time 495809679870 ps
CPU time 648.66 seconds
Started Aug 11 06:42:07 PM PDT 24
Finished Aug 11 06:52:56 PM PDT 24
Peak memory 201444 kb
Host smart-75023a35-6a2c-44ca-8555-229e82a86361
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344316884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2344316884
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4280041512
Short name T153
Test name
Test status
Simulation time 502150605635 ps
CPU time 186.2 seconds
Started Aug 11 06:44:20 PM PDT 24
Finished Aug 11 06:47:26 PM PDT 24
Peak memory 201488 kb
Host smart-c9bd1102-43fc-40d4-a423-1dda5860fc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280041512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4280041512
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3807134791
Short name T77
Test name
Test status
Simulation time 544823793 ps
CPU time 3.46 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201652 kb
Host smart-6a55d706-c061-415f-aa62-ab270fae632a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807134791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3807134791
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2590728242
Short name T273
Test name
Test status
Simulation time 503007530963 ps
CPU time 1075.14 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:58:46 PM PDT 24
Peak memory 201460 kb
Host smart-683044ae-6cd2-4702-b62d-f8398a34499d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590728242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2590728242
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3857661682
Short name T76
Test name
Test status
Simulation time 8005548703 ps
CPU time 9.62 seconds
Started Aug 11 06:40:44 PM PDT 24
Finished Aug 11 06:40:54 PM PDT 24
Peak memory 218256 kb
Host smart-0d77f974-f032-44af-87ab-adaba2508954
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857661682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3857661682
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2318367607
Short name T256
Test name
Test status
Simulation time 639132886422 ps
CPU time 359.93 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:46:58 PM PDT 24
Peak memory 201412 kb
Host smart-aec7573e-abb1-4fdb-ade4-973f9e06e5ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318367607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2318367607
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1588820297
Short name T156
Test name
Test status
Simulation time 671741524909 ps
CPU time 1622.59 seconds
Started Aug 11 06:42:09 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 201428 kb
Host smart-8bb2554b-3acc-4ea8-9f5c-a0911949994e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588820297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1588820297
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.641430515
Short name T161
Test name
Test status
Simulation time 348187052184 ps
CPU time 359.18 seconds
Started Aug 11 06:44:28 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 201396 kb
Host smart-dd95e3a1-a5fb-41a9-85a6-8b954adc44f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641430515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.641430515
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2863094954
Short name T67
Test name
Test status
Simulation time 464974952 ps
CPU time 1.91 seconds
Started Aug 11 06:22:52 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 201300 kb
Host smart-05563acd-4247-4ca8-bc9d-fd1d8cc0af17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863094954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2863094954
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.405124596
Short name T55
Test name
Test status
Simulation time 202177096877 ps
CPU time 218.51 seconds
Started Aug 11 06:42:22 PM PDT 24
Finished Aug 11 06:46:01 PM PDT 24
Peak memory 201464 kb
Host smart-7258470e-5cc7-4d63-9b21-5607c1dd872e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405124596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.405124596
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.105679217
Short name T257
Test name
Test status
Simulation time 518489210296 ps
CPU time 1221.81 seconds
Started Aug 11 06:42:48 PM PDT 24
Finished Aug 11 07:03:10 PM PDT 24
Peak memory 201448 kb
Host smart-d649e137-d3a3-4592-8f79-2512f31bd2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105679217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.105679217
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2972157461
Short name T204
Test name
Test status
Simulation time 568270697855 ps
CPU time 350.01 seconds
Started Aug 11 06:43:03 PM PDT 24
Finished Aug 11 06:48:53 PM PDT 24
Peak memory 201452 kb
Host smart-bb5496aa-b8b9-4243-8754-d88583152720
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972157461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2972157461
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2351233897
Short name T281
Test name
Test status
Simulation time 490124076953 ps
CPU time 1029.47 seconds
Started Aug 11 06:42:14 PM PDT 24
Finished Aug 11 06:59:24 PM PDT 24
Peak memory 201408 kb
Host smart-a8a773f3-fe76-4264-a54e-df7a9bf5bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351233897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2351233897
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3966774181
Short name T151
Test name
Test status
Simulation time 492125990367 ps
CPU time 1128.56 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:59:41 PM PDT 24
Peak memory 201524 kb
Host smart-ba5e7b8a-b24d-4264-8749-c0b54bbd80fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966774181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3966774181
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3457585940
Short name T253
Test name
Test status
Simulation time 358718306519 ps
CPU time 223.33 seconds
Started Aug 11 06:43:11 PM PDT 24
Finished Aug 11 06:46:54 PM PDT 24
Peak memory 201400 kb
Host smart-3d55cd8d-7940-4076-8869-5d8767b7b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457585940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3457585940
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3190375315
Short name T277
Test name
Test status
Simulation time 353617339487 ps
CPU time 743.35 seconds
Started Aug 11 06:44:42 PM PDT 24
Finished Aug 11 06:57:06 PM PDT 24
Peak memory 201416 kb
Host smart-31e6343d-0a11-4885-b7d3-4e15f6dc5349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190375315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3190375315
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.521842849
Short name T278
Test name
Test status
Simulation time 505190383657 ps
CPU time 541.51 seconds
Started Aug 11 06:42:10 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 201420 kb
Host smart-0a2e0b27-f35b-4ff4-82be-02ba59bc3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521842849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.521842849
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3684605
Short name T242
Test name
Test status
Simulation time 480154564553 ps
CPU time 523.4 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:52:24 PM PDT 24
Peak memory 201400 kb
Host smart-2b241e8d-4c22-474f-8139-67591ebcac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3684605
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1737244420
Short name T162
Test name
Test status
Simulation time 623562614878 ps
CPU time 2132.49 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 210052 kb
Host smart-f134f4c1-2400-45e7-a996-759e5fe477c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737244420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1737244420
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1868233699
Short name T301
Test name
Test status
Simulation time 321679402972 ps
CPU time 110.09 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:33 PM PDT 24
Peak memory 201496 kb
Host smart-23c8a8be-13bf-4955-b7ea-066b92d1a630
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868233699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1868233699
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1606466054
Short name T412
Test name
Test status
Simulation time 382467695 ps
CPU time 0.82 seconds
Started Aug 11 06:41:25 PM PDT 24
Finished Aug 11 06:41:26 PM PDT 24
Peak memory 201396 kb
Host smart-1a28c6f2-84c8-4704-bb11-07397457023c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606466054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1606466054
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2072310613
Short name T42
Test name
Test status
Simulation time 185700110701 ps
CPU time 190.68 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:44:50 PM PDT 24
Peak memory 212860 kb
Host smart-5a04fa63-7ff6-4248-b0de-3109061ecba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072310613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2072310613
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2360971176
Short name T167
Test name
Test status
Simulation time 453204548038 ps
CPU time 260.41 seconds
Started Aug 11 06:42:12 PM PDT 24
Finished Aug 11 06:46:33 PM PDT 24
Peak memory 201468 kb
Host smart-a736f21a-9865-4ab1-8002-9573f630d22d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360971176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2360971176
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.728622037
Short name T37
Test name
Test status
Simulation time 488196024747 ps
CPU time 741.17 seconds
Started Aug 11 06:42:22 PM PDT 24
Finished Aug 11 06:54:43 PM PDT 24
Peak memory 201464 kb
Host smart-a58eac40-1565-415f-aa7a-6a0e095bd1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728622037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
728622037
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3429429003
Short name T68
Test name
Test status
Simulation time 4461020613 ps
CPU time 3.99 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201496 kb
Host smart-2b388df5-e02a-4f15-abd2-ea5ca2be1795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429429003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3429429003
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3112568336
Short name T147
Test name
Test status
Simulation time 328628145207 ps
CPU time 115.02 seconds
Started Aug 11 06:41:08 PM PDT 24
Finished Aug 11 06:43:04 PM PDT 24
Peak memory 201416 kb
Host smart-f28b9a88-3ebd-4eef-86a3-cc9ade3cf753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112568336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3112568336
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2620985295
Short name T313
Test name
Test status
Simulation time 618784450194 ps
CPU time 147.26 seconds
Started Aug 11 06:43:25 PM PDT 24
Finished Aug 11 06:45:52 PM PDT 24
Peak memory 201416 kb
Host smart-1343a973-1e27-4fc1-8794-50b494734db1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620985295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2620985295
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3737836124
Short name T254
Test name
Test status
Simulation time 385174467333 ps
CPU time 912.78 seconds
Started Aug 11 06:41:08 PM PDT 24
Finished Aug 11 06:56:21 PM PDT 24
Peak memory 201496 kb
Host smart-096abd0b-0f0b-420a-b0a3-97daf4a9f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737836124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3737836124
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3498408385
Short name T245
Test name
Test status
Simulation time 59016164311 ps
CPU time 121.46 seconds
Started Aug 11 06:41:46 PM PDT 24
Finished Aug 11 06:43:47 PM PDT 24
Peak memory 209852 kb
Host smart-af5fd3e5-fd09-40ee-b197-6c01ceb456a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498408385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3498408385
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1998683512
Short name T20
Test name
Test status
Simulation time 454006985496 ps
CPU time 172.84 seconds
Started Aug 11 06:43:35 PM PDT 24
Finished Aug 11 06:46:28 PM PDT 24
Peak memory 210176 kb
Host smart-69ff7e92-81e4-4040-80df-d7751ec0b11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998683512 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1998683512
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4285339766
Short name T36
Test name
Test status
Simulation time 366002610781 ps
CPU time 855.25 seconds
Started Aug 11 06:45:23 PM PDT 24
Finished Aug 11 06:59:38 PM PDT 24
Peak memory 201416 kb
Host smart-5e75ebc4-04ed-46ed-967f-849496453e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285339766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4285339766
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3316079123
Short name T345
Test name
Test status
Simulation time 517127038867 ps
CPU time 292.43 seconds
Started Aug 11 06:41:03 PM PDT 24
Finished Aug 11 06:45:56 PM PDT 24
Peak memory 201504 kb
Host smart-1183577e-ac6e-41e2-8542-eea10e2187df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316079123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3316079123
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1732644055
Short name T229
Test name
Test status
Simulation time 447248486849 ps
CPU time 702.52 seconds
Started Aug 11 06:42:16 PM PDT 24
Finished Aug 11 06:53:59 PM PDT 24
Peak memory 212800 kb
Host smart-b29495c4-8dd0-4044-a550-1cc9b75d073a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732644055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1732644055
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.121809135
Short name T250
Test name
Test status
Simulation time 328669175562 ps
CPU time 387.48 seconds
Started Aug 11 06:43:17 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 201444 kb
Host smart-eda2b06b-f4ba-4466-988f-cb6c142f80d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121809135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.121809135
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1947829449
Short name T216
Test name
Test status
Simulation time 336067296652 ps
CPU time 204.39 seconds
Started Aug 11 06:44:16 PM PDT 24
Finished Aug 11 06:47:40 PM PDT 24
Peak memory 201452 kb
Host smart-8947f490-2692-4a27-9964-5b0f88a7800d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947829449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1947829449
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3188024878
Short name T320
Test name
Test status
Simulation time 161161004989 ps
CPU time 87 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:43:02 PM PDT 24
Peak memory 201460 kb
Host smart-d85e5448-f85b-415e-b098-db5d06b8896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188024878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3188024878
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3252579090
Short name T251
Test name
Test status
Simulation time 122242576095 ps
CPU time 132.3 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:43:50 PM PDT 24
Peak memory 209768 kb
Host smart-219050f2-c48c-487e-acc1-96e7a1881c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252579090 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3252579090
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.264458422
Short name T264
Test name
Test status
Simulation time 507303182831 ps
CPU time 1096.57 seconds
Started Aug 11 06:42:15 PM PDT 24
Finished Aug 11 07:00:31 PM PDT 24
Peak memory 201444 kb
Host smart-25fb1b78-00b9-4744-8e75-7c5dc5eb1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264458422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.264458422
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1996300590
Short name T221
Test name
Test status
Simulation time 512388001350 ps
CPU time 303.97 seconds
Started Aug 11 06:43:44 PM PDT 24
Finished Aug 11 06:48:48 PM PDT 24
Peak memory 201372 kb
Host smart-dfdd68cc-cc16-45f2-b99f-536f8515c7a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996300590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1996300590
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2991863564
Short name T128
Test name
Test status
Simulation time 893265017 ps
CPU time 2.76 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:22:41 PM PDT 24
Peak memory 201448 kb
Host smart-ed66256c-b9e0-40ee-bccb-a061d1e3fea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991863564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2991863564
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3822172428
Short name T267
Test name
Test status
Simulation time 90852779803 ps
CPU time 97.17 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:42:28 PM PDT 24
Peak memory 218316 kb
Host smart-b02aab75-4417-4545-a93b-a0bc75e78f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822172428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3822172428
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1732307009
Short name T323
Test name
Test status
Simulation time 516723783988 ps
CPU time 1210.14 seconds
Started Aug 11 06:41:12 PM PDT 24
Finished Aug 11 07:01:22 PM PDT 24
Peak memory 201444 kb
Host smart-2a70a122-6b27-460c-bca3-990df96418ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732307009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1732307009
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2323629129
Short name T329
Test name
Test status
Simulation time 526300649460 ps
CPU time 1183.93 seconds
Started Aug 11 06:41:30 PM PDT 24
Finished Aug 11 07:01:14 PM PDT 24
Peak memory 201500 kb
Host smart-44ab4260-8660-4e81-8c32-071a27bd05ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323629129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2323629129
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4277268640
Short name T338
Test name
Test status
Simulation time 543385677404 ps
CPU time 1282.7 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 07:03:06 PM PDT 24
Peak memory 201468 kb
Host smart-48d3edbc-4db0-44fd-bec7-d4d7ea54f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277268640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4277268640
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2061799207
Short name T92
Test name
Test status
Simulation time 233701474709 ps
CPU time 102.79 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:45:23 PM PDT 24
Peak memory 209776 kb
Host smart-9db166a8-d28c-4e01-81dc-663d2e132948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061799207 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2061799207
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.235711207
Short name T146
Test name
Test status
Simulation time 483294220382 ps
CPU time 1156.89 seconds
Started Aug 11 06:43:54 PM PDT 24
Finished Aug 11 07:03:11 PM PDT 24
Peak memory 201408 kb
Host smart-5537d2f9-f5b9-46a8-af7f-21274cfa7603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235711207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.235711207
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.873093844
Short name T350
Test name
Test status
Simulation time 516166052455 ps
CPU time 178.99 seconds
Started Aug 11 06:41:22 PM PDT 24
Finished Aug 11 06:44:21 PM PDT 24
Peak memory 201416 kb
Host smart-1ffe2497-9476-429b-b0b2-987c304504ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873093844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.873093844
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2926082554
Short name T180
Test name
Test status
Simulation time 549833510375 ps
CPU time 1262.71 seconds
Started Aug 11 06:41:46 PM PDT 24
Finished Aug 11 07:02:49 PM PDT 24
Peak memory 201392 kb
Host smart-94886ecb-76f0-4206-9e6d-1b56db5351b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926082554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2926082554
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.375819724
Short name T299
Test name
Test status
Simulation time 486918167742 ps
CPU time 986.41 seconds
Started Aug 11 06:43:03 PM PDT 24
Finished Aug 11 06:59:30 PM PDT 24
Peak memory 201400 kb
Host smart-7dbb5338-140e-45d8-aa0a-888c67481729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375819724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.375819724
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4197502655
Short name T60
Test name
Test status
Simulation time 345551244120 ps
CPU time 729.7 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:53:03 PM PDT 24
Peak memory 210016 kb
Host smart-2201eb31-da13-454c-806e-e329b48fb970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197502655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4197502655
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1602559075
Short name T838
Test name
Test status
Simulation time 2528575048 ps
CPU time 3.82 seconds
Started Aug 11 06:23:00 PM PDT 24
Finished Aug 11 06:23:04 PM PDT 24
Peak memory 201228 kb
Host smart-70079c61-fbbd-4bc5-9990-21eee5309f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602559075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1602559075
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.831799908
Short name T163
Test name
Test status
Simulation time 497352986780 ps
CPU time 315.1 seconds
Started Aug 11 06:41:19 PM PDT 24
Finished Aug 11 06:46:34 PM PDT 24
Peak memory 201408 kb
Host smart-b3e0cc7b-b583-489a-b88f-ca2f4b128531
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831799908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.831799908
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3489767303
Short name T334
Test name
Test status
Simulation time 496220589190 ps
CPU time 1216.41 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 201424 kb
Host smart-d531e49c-f68c-463f-afd2-70e3de3c190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489767303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3489767303
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.91730497
Short name T259
Test name
Test status
Simulation time 547883516776 ps
CPU time 1123.88 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 07:00:16 PM PDT 24
Peak memory 201436 kb
Host smart-1b0eb076-b77f-4e31-8b7d-fe1256dd680c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91730497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_w
akeup.91730497
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4129863919
Short name T359
Test name
Test status
Simulation time 584274518330 ps
CPU time 327.29 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 201440 kb
Host smart-4981b71b-676f-4442-a92e-026bd767686d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129863919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4129863919
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3506007013
Short name T182
Test name
Test status
Simulation time 338332938070 ps
CPU time 196.11 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:44:57 PM PDT 24
Peak memory 201400 kb
Host smart-f48fbb05-f561-4839-8b7f-88b3acffe358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506007013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3506007013
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2900484937
Short name T34
Test name
Test status
Simulation time 35908075852 ps
CPU time 83.97 seconds
Started Aug 11 06:42:04 PM PDT 24
Finished Aug 11 06:43:28 PM PDT 24
Peak memory 209852 kb
Host smart-7035ee37-8ab2-4353-a275-2e5c2f2e671f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900484937 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2900484937
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1012430990
Short name T43
Test name
Test status
Simulation time 246533142058 ps
CPU time 353.48 seconds
Started Aug 11 06:44:25 PM PDT 24
Finished Aug 11 06:50:18 PM PDT 24
Peak memory 210160 kb
Host smart-6d01a2b9-d8c7-49c4-b742-e0cc1a605c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012430990 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1012430990
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1815818792
Short name T319
Test name
Test status
Simulation time 191699341852 ps
CPU time 108.47 seconds
Started Aug 11 06:44:38 PM PDT 24
Finished Aug 11 06:46:27 PM PDT 24
Peak memory 201428 kb
Host smart-66e0131d-def1-49b5-a730-548d1f82209b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815818792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1815818792
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4178927208
Short name T268
Test name
Test status
Simulation time 321205535313 ps
CPU time 362.87 seconds
Started Aug 11 06:45:02 PM PDT 24
Finished Aug 11 06:51:05 PM PDT 24
Peak memory 201468 kb
Host smart-a4bfd767-3265-4207-adaf-0ed01bc5889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178927208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4178927208
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3677656715
Short name T260
Test name
Test status
Simulation time 511163985970 ps
CPU time 310.64 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:46:02 PM PDT 24
Peak memory 201516 kb
Host smart-d0a74845-3e04-45f8-8fbe-ee071abcd88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677656715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3677656715
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.98309963
Short name T302
Test name
Test status
Simulation time 485316597456 ps
CPU time 545.05 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:49:56 PM PDT 24
Peak memory 201456 kb
Host smart-311871e3-823c-4604-b2b9-84e5570bda26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98309963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.98309963
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3825746284
Short name T300
Test name
Test status
Simulation time 546046220186 ps
CPU time 1297.41 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 07:02:23 PM PDT 24
Peak memory 201364 kb
Host smart-b1af0045-0d8b-4b3e-aec8-bbad7f8004c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825746284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3825746284
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4170472304
Short name T232
Test name
Test status
Simulation time 116899867443 ps
CPU time 409.37 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:48:14 PM PDT 24
Peak memory 201804 kb
Host smart-785e7662-4675-4cde-8bda-b5a16817341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170472304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4170472304
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.552271327
Short name T266
Test name
Test status
Simulation time 492281071076 ps
CPU time 590.5 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:51:30 PM PDT 24
Peak memory 201408 kb
Host smart-c7ceaffc-e117-4db7-a3b1-69dd748b12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552271327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.552271327
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.184476797
Short name T367
Test name
Test status
Simulation time 342557013974 ps
CPU time 795.77 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:54:59 PM PDT 24
Peak memory 201436 kb
Host smart-aef5c5c3-2450-4cdb-9c23-e705daa5c339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184476797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.184476797
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3532815420
Short name T298
Test name
Test status
Simulation time 180643541559 ps
CPU time 203.57 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:45:00 PM PDT 24
Peak memory 201412 kb
Host smart-94fec87f-04ed-426b-b34c-27223fc18d0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532815420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3532815420
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4027929766
Short name T336
Test name
Test status
Simulation time 354601348151 ps
CPU time 193.4 seconds
Started Aug 11 06:42:05 PM PDT 24
Finished Aug 11 06:45:19 PM PDT 24
Peak memory 201436 kb
Host smart-adb55b38-1fdc-40dc-a29c-5ded9d32ea6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027929766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4027929766
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.802165068
Short name T243
Test name
Test status
Simulation time 514878248319 ps
CPU time 988.65 seconds
Started Aug 11 06:42:35 PM PDT 24
Finished Aug 11 06:59:04 PM PDT 24
Peak memory 201420 kb
Host smart-43c3892f-7acc-412a-a8e5-8f5d19e7556d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802165068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.802165068
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2672614363
Short name T17
Test name
Test status
Simulation time 418846563117 ps
CPU time 166.36 seconds
Started Aug 11 06:43:08 PM PDT 24
Finished Aug 11 06:45:54 PM PDT 24
Peak memory 218124 kb
Host smart-e59e33fd-7043-46e5-821a-4103e880fc77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672614363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2672614363
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3598957080
Short name T846
Test name
Test status
Simulation time 379358278 ps
CPU time 3.31 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 217976 kb
Host smart-a476d4fd-8a39-4643-aa12-c1a2c77c68d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598957080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3598957080
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2059403026
Short name T86
Test name
Test status
Simulation time 8481540074 ps
CPU time 7.6 seconds
Started Aug 11 06:22:55 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201632 kb
Host smart-66f4109d-c2d6-4c5d-9dfd-97f35c2d2269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059403026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2059403026
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.998305564
Short name T912
Test name
Test status
Simulation time 8073374879 ps
CPU time 5.02 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:42 PM PDT 24
Peak memory 201688 kb
Host smart-2200f56b-6c87-4ed2-8ee8-cbf4cb07dee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998305564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.998305564
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3731139011
Short name T231
Test name
Test status
Simulation time 117557418858 ps
CPU time 414.62 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 201924 kb
Host smart-eb8796be-dc6d-452b-aaa9-ab213185fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731139011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3731139011
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1879071341
Short name T3
Test name
Test status
Simulation time 490108743160 ps
CPU time 1105.41 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:59:11 PM PDT 24
Peak memory 201472 kb
Host smart-c2eb4005-b94c-4887-a334-d4bcc9e394d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879071341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1879071341
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2734326939
Short name T372
Test name
Test status
Simulation time 554152776186 ps
CPU time 1345.19 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 07:03:12 PM PDT 24
Peak memory 201412 kb
Host smart-1e18cd13-65ee-4eee-a474-98f273ffa657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734326939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2734326939
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1597011379
Short name T305
Test name
Test status
Simulation time 183257707115 ps
CPU time 194.13 seconds
Started Aug 11 06:41:15 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 201360 kb
Host smart-5866c3d2-9093-4f68-af78-19999a831771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597011379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1597011379
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2924777269
Short name T291
Test name
Test status
Simulation time 367484515554 ps
CPU time 399.13 seconds
Started Aug 11 06:41:12 PM PDT 24
Finished Aug 11 06:47:51 PM PDT 24
Peak memory 201496 kb
Host smart-6dbcf051-4e98-4f5f-871a-33611e6d6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924777269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2924777269
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1527836992
Short name T324
Test name
Test status
Simulation time 502977574753 ps
CPU time 587.48 seconds
Started Aug 11 06:41:28 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 201408 kb
Host smart-1f952619-9674-43e3-b501-5ade33f4103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527836992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1527836992
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3917599739
Short name T658
Test name
Test status
Simulation time 216040800779 ps
CPU time 1003.2 seconds
Started Aug 11 06:41:23 PM PDT 24
Finished Aug 11 06:58:07 PM PDT 24
Peak memory 201860 kb
Host smart-ac3aeb98-51c3-4cb7-a9ae-4d37841a2ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917599739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3917599739
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1944137849
Short name T155
Test name
Test status
Simulation time 331514465806 ps
CPU time 108.78 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:31 PM PDT 24
Peak memory 201476 kb
Host smart-9fe54aa6-679e-4636-82c2-3c8577a5b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944137849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1944137849
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.288322742
Short name T382
Test name
Test status
Simulation time 69108159088 ps
CPU time 371.16 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:47:45 PM PDT 24
Peak memory 201760 kb
Host smart-84992136-be88-4d2d-a147-83562c42b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288322742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.288322742
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2742109405
Short name T228
Test name
Test status
Simulation time 124206045106 ps
CPU time 405.98 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:48:27 PM PDT 24
Peak memory 201880 kb
Host smart-83ab7a69-c29e-494a-a7b6-7d6feb457beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742109405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2742109405
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3085795083
Short name T369
Test name
Test status
Simulation time 413020703784 ps
CPU time 890.98 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:56:32 PM PDT 24
Peak memory 201484 kb
Host smart-ea97825e-c198-44ac-a2f3-07453da9cee2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085795083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3085795083
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.670069812
Short name T380
Test name
Test status
Simulation time 96796578372 ps
CPU time 506.2 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:50:07 PM PDT 24
Peak memory 201812 kb
Host smart-37953602-0c7f-48df-9066-02f8e94ccce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670069812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.670069812
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2274368680
Short name T333
Test name
Test status
Simulation time 485057593958 ps
CPU time 568.88 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 201656 kb
Host smart-efa103a4-b453-4eb3-a205-be3eb44f97c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274368680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2274368680
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3384432578
Short name T283
Test name
Test status
Simulation time 168859399301 ps
CPU time 28.77 seconds
Started Aug 11 06:41:48 PM PDT 24
Finished Aug 11 06:42:17 PM PDT 24
Peak memory 201432 kb
Host smart-b6f5fa30-9da9-4882-bd4a-ab805ddeba85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384432578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3384432578
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3905096907
Short name T193
Test name
Test status
Simulation time 326224575210 ps
CPU time 121.73 seconds
Started Aug 11 06:42:16 PM PDT 24
Finished Aug 11 06:44:17 PM PDT 24
Peak memory 201452 kb
Host smart-aeb97e11-d62a-48be-a76a-696f77a2014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905096907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3905096907
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.60338998
Short name T102
Test name
Test status
Simulation time 377629098223 ps
CPU time 672.5 seconds
Started Aug 11 06:42:49 PM PDT 24
Finished Aug 11 06:54:02 PM PDT 24
Peak memory 201476 kb
Host smart-3d3320bf-56c3-44f4-898c-4177db2130cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60338998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gatin
g.60338998
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3981213761
Short name T293
Test name
Test status
Simulation time 361815683959 ps
CPU time 875.39 seconds
Started Aug 11 06:42:50 PM PDT 24
Finished Aug 11 06:57:25 PM PDT 24
Peak memory 201404 kb
Host smart-9532339e-0ffa-4d52-ba8e-e9fa3cf584e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981213761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3981213761
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1273571698
Short name T321
Test name
Test status
Simulation time 179186156453 ps
CPU time 79.47 seconds
Started Aug 11 06:44:31 PM PDT 24
Finished Aug 11 06:45:50 PM PDT 24
Peak memory 201552 kb
Host smart-4f7dca02-12a1-472a-8ae8-604126943a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273571698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1273571698
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.111390914
Short name T249
Test name
Test status
Simulation time 376343113697 ps
CPU time 886.82 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:55:44 PM PDT 24
Peak memory 201456 kb
Host smart-0192ede1-85ca-4d9a-896c-5b011dda0f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111390914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.111390914
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2411190209
Short name T109
Test name
Test status
Simulation time 330011883065 ps
CPU time 796.89 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:54:21 PM PDT 24
Peak memory 201496 kb
Host smart-c3f1f3d9-9902-4fc7-99f6-06d2798c6d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411190209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2411190209
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2894899834
Short name T837
Test name
Test status
Simulation time 952898331 ps
CPU time 1.77 seconds
Started Aug 11 06:22:34 PM PDT 24
Finished Aug 11 06:22:36 PM PDT 24
Peak memory 201512 kb
Host smart-30854b6a-29c7-48e8-bf34-1bd7ef5a19ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894899834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2894899834
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1497373181
Short name T876
Test name
Test status
Simulation time 23168788831 ps
CPU time 90.28 seconds
Started Aug 11 06:22:31 PM PDT 24
Finished Aug 11 06:24:02 PM PDT 24
Peak memory 201640 kb
Host smart-b91e256d-af13-4497-adda-0ede022b08a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497373181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1497373181
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1319236566
Short name T882
Test name
Test status
Simulation time 1184785128 ps
CPU time 1.39 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:39 PM PDT 24
Peak memory 201324 kb
Host smart-74d53bc7-6a34-40e5-bcec-371cc2f2de7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319236566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1319236566
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3524870893
Short name T852
Test name
Test status
Simulation time 490337007 ps
CPU time 1.9 seconds
Started Aug 11 06:22:44 PM PDT 24
Finished Aug 11 06:22:46 PM PDT 24
Peak memory 201480 kb
Host smart-0d3d55c7-3a2e-4578-947a-4638ac2d5e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524870893 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3524870893
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2450902317
Short name T869
Test name
Test status
Simulation time 603356693 ps
CPU time 0.9 seconds
Started Aug 11 06:22:31 PM PDT 24
Finished Aug 11 06:22:32 PM PDT 24
Peak memory 201400 kb
Host smart-a8852834-ebba-4894-a009-71b498fd3bbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450902317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2450902317
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1726329603
Short name T858
Test name
Test status
Simulation time 510667247 ps
CPU time 1.82 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:52 PM PDT 24
Peak memory 201300 kb
Host smart-60cc7c0e-1b3f-4c40-a8fe-e19c79c45934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726329603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1726329603
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.412992363
Short name T853
Test name
Test status
Simulation time 3963881778 ps
CPU time 9.78 seconds
Started Aug 11 06:22:52 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 201544 kb
Host smart-c5cc981c-3d45-4c0f-9ece-f43fbf3ddf95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412992363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.412992363
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.860281603
Short name T70
Test name
Test status
Simulation time 4396657619 ps
CPU time 12.02 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201620 kb
Host smart-b0b99e83-088d-44e8-b899-93d3c82104e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860281603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.860281603
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1935305229
Short name T902
Test name
Test status
Simulation time 52036448257 ps
CPU time 46.21 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:23:37 PM PDT 24
Peak memory 201464 kb
Host smart-92d5f286-9c18-4f9a-9e9b-e249be654925
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935305229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1935305229
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2187447055
Short name T130
Test name
Test status
Simulation time 783989093 ps
CPU time 1.11 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:42 PM PDT 24
Peak memory 201328 kb
Host smart-e39bc206-bd72-4d94-a2ba-d64a54c2a528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187447055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2187447055
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.878378001
Short name T843
Test name
Test status
Simulation time 500356925 ps
CPU time 1.28 seconds
Started Aug 11 06:23:07 PM PDT 24
Finished Aug 11 06:23:08 PM PDT 24
Peak memory 201488 kb
Host smart-0f121abd-480e-4871-a246-01b39edc417d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878378001 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.878378001
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.138237906
Short name T804
Test name
Test status
Simulation time 428063604 ps
CPU time 1.83 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 201348 kb
Host smart-a91ae756-cd9a-4886-bc79-85d7ad53bd76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138237906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.138237906
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3649059056
Short name T890
Test name
Test status
Simulation time 324164337 ps
CPU time 0.86 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 201264 kb
Host smart-8f5d0483-55b1-4bb8-a736-a7725db5cc9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649059056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3649059056
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1080935228
Short name T855
Test name
Test status
Simulation time 1565292648 ps
CPU time 4.97 seconds
Started Aug 11 06:22:39 PM PDT 24
Finished Aug 11 06:22:44 PM PDT 24
Peak memory 201356 kb
Host smart-77bf31bc-d623-4274-9022-67ae37f0adea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080935228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1080935228
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3524551764
Short name T872
Test name
Test status
Simulation time 653099760 ps
CPU time 1.84 seconds
Started Aug 11 06:22:33 PM PDT 24
Finished Aug 11 06:22:35 PM PDT 24
Peak memory 201648 kb
Host smart-eb4650b3-94b3-4275-8304-3b83636f79a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524551764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3524551764
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.754980592
Short name T817
Test name
Test status
Simulation time 335517288 ps
CPU time 1.68 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:53 PM PDT 24
Peak memory 201172 kb
Host smart-a9fa78e6-4cb7-4120-85b2-86057a021eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754980592 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.754980592
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3511904209
Short name T131
Test name
Test status
Simulation time 312801821 ps
CPU time 1.32 seconds
Started Aug 11 06:22:52 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 201360 kb
Host smart-496ccffe-c553-4bed-af01-a6eba51d5a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511904209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3511904209
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4006271059
Short name T802
Test name
Test status
Simulation time 580045087 ps
CPU time 0.84 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:42 PM PDT 24
Peak memory 201240 kb
Host smart-2868b2c3-0648-45b3-b312-0295259b3885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006271059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4006271059
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1582372658
Short name T907
Test name
Test status
Simulation time 4580904489 ps
CPU time 3.43 seconds
Started Aug 11 06:22:47 PM PDT 24
Finished Aug 11 06:22:51 PM PDT 24
Peak memory 201584 kb
Host smart-df9190b8-9a6f-425b-a9ac-002958835053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582372658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1582372658
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1278981704
Short name T847
Test name
Test status
Simulation time 472624172 ps
CPU time 1.7 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:53 PM PDT 24
Peak memory 201652 kb
Host smart-40e4e0b6-3eb9-47d7-b185-c451f744e3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278981704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1278981704
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3358913777
Short name T825
Test name
Test status
Simulation time 4932492322 ps
CPU time 4.39 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:46 PM PDT 24
Peak memory 201660 kb
Host smart-97a1db92-110a-4ad3-bd07-df5f9ca80840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358913777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3358913777
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.579551638
Short name T830
Test name
Test status
Simulation time 461018195 ps
CPU time 1.42 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201496 kb
Host smart-2b9e04d0-f4c6-4ebd-af30-edd8f7542442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579551638 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.579551638
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1430369612
Short name T845
Test name
Test status
Simulation time 520526755 ps
CPU time 0.94 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:42 PM PDT 24
Peak memory 201360 kb
Host smart-37067854-c2f3-4705-a2bd-a09b5e425b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430369612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1430369612
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3631746061
Short name T816
Test name
Test status
Simulation time 2152523771 ps
CPU time 2.89 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:23:01 PM PDT 24
Peak memory 201408 kb
Host smart-7bf7efe8-ef1d-4a9d-8946-17c51acaf0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631746061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3631746061
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1196388835
Short name T849
Test name
Test status
Simulation time 373319963 ps
CPU time 2.52 seconds
Started Aug 11 06:23:05 PM PDT 24
Finished Aug 11 06:23:08 PM PDT 24
Peak memory 217376 kb
Host smart-1b3e5cfc-9975-456c-84e0-8ace1d0cf172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196388835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1196388835
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.839004772
Short name T376
Test name
Test status
Simulation time 8313351938 ps
CPU time 8.04 seconds
Started Aug 11 06:22:40 PM PDT 24
Finished Aug 11 06:22:48 PM PDT 24
Peak memory 201708 kb
Host smart-9e6794b7-ac79-459f-af7e-c5cb2867ab3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839004772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.839004772
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.451115273
Short name T867
Test name
Test status
Simulation time 353097712 ps
CPU time 1.49 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201472 kb
Host smart-f014b3d6-bbd4-4f0d-af08-80d655266061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451115273 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.451115273
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1568456364
Short name T140
Test name
Test status
Simulation time 503375520 ps
CPU time 0.9 seconds
Started Aug 11 06:22:53 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 201316 kb
Host smart-9435e225-4352-44dc-8d06-01f4e52ce1d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568456364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1568456364
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.855419424
Short name T897
Test name
Test status
Simulation time 500079189 ps
CPU time 0.88 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201292 kb
Host smart-b642c802-44b5-4911-a6e8-d6bce00d2ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855419424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.855419424
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1378435842
Short name T874
Test name
Test status
Simulation time 5026773087 ps
CPU time 15.16 seconds
Started Aug 11 06:23:03 PM PDT 24
Finished Aug 11 06:23:18 PM PDT 24
Peak memory 201608 kb
Host smart-d6fb9bd2-64b1-4621-b4c3-f15f5df9ba4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378435842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1378435842
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4028007363
Short name T841
Test name
Test status
Simulation time 525811775 ps
CPU time 3.64 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:55 PM PDT 24
Peak memory 217576 kb
Host smart-d572fdcd-5189-4cb3-af95-d826fe6d93bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028007363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4028007363
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3597098007
Short name T840
Test name
Test status
Simulation time 4859517715 ps
CPU time 3.73 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:45 PM PDT 24
Peak memory 201684 kb
Host smart-019ffea4-80c0-4d34-82dd-e6516c823c40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597098007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3597098007
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2635132963
Short name T800
Test name
Test status
Simulation time 720226524 ps
CPU time 1.08 seconds
Started Aug 11 06:22:40 PM PDT 24
Finished Aug 11 06:22:42 PM PDT 24
Peak memory 201464 kb
Host smart-7f8cde35-6018-4d91-a547-6f90f66782db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635132963 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2635132963
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2824593283
Short name T126
Test name
Test status
Simulation time 576650888 ps
CPU time 1.09 seconds
Started Aug 11 06:22:59 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201360 kb
Host smart-1a9033ad-f5a2-483a-b832-1487b4028139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824593283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2824593283
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3628572103
Short name T856
Test name
Test status
Simulation time 506609441 ps
CPU time 0.8 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:52 PM PDT 24
Peak memory 201348 kb
Host smart-5df031d8-a4fd-4cd5-b9e0-62244dfa5e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628572103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3628572103
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3596231860
Short name T881
Test name
Test status
Simulation time 2453969134 ps
CPU time 3.33 seconds
Started Aug 11 06:22:51 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 201012 kb
Host smart-1c2c9767-769a-4310-b4ba-29d1565bcede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596231860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3596231860
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.963670639
Short name T839
Test name
Test status
Simulation time 364757482 ps
CPU time 2.52 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201688 kb
Host smart-8e6d4a36-f338-4d69-a93f-8806e97716f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963670639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.963670639
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3248120346
Short name T901
Test name
Test status
Simulation time 3917764099 ps
CPU time 10.99 seconds
Started Aug 11 06:22:55 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201656 kb
Host smart-1e215349-7079-49dd-b80f-264f05e7ad22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248120346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3248120346
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1797191953
Short name T813
Test name
Test status
Simulation time 557365908 ps
CPU time 2.25 seconds
Started Aug 11 06:22:55 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201432 kb
Host smart-2d98817c-6bf0-4493-b72c-46ffd40db66c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797191953 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1797191953
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1137445553
Short name T910
Test name
Test status
Simulation time 467833062 ps
CPU time 1.33 seconds
Started Aug 11 06:22:44 PM PDT 24
Finished Aug 11 06:22:46 PM PDT 24
Peak memory 201344 kb
Host smart-2c49563b-0c82-465f-95d3-637fe927328c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137445553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1137445553
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3706874184
Short name T917
Test name
Test status
Simulation time 435338213 ps
CPU time 1.43 seconds
Started Aug 11 06:22:42 PM PDT 24
Finished Aug 11 06:22:44 PM PDT 24
Peak memory 201336 kb
Host smart-fefc8ac0-6848-407f-9684-0c8c99a6eddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706874184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3706874184
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1559318550
Short name T79
Test name
Test status
Simulation time 551351312 ps
CPU time 3.33 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 217980 kb
Host smart-cd042075-f09d-4aa2-976a-bbdeb0823569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559318550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1559318550
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2753948569
Short name T913
Test name
Test status
Simulation time 8432689968 ps
CPU time 4.39 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:23:01 PM PDT 24
Peak memory 201648 kb
Host smart-562309fb-2841-4189-ad83-8479723bbde4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753948569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2753948569
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.81849265
Short name T93
Test name
Test status
Simulation time 557902663 ps
CPU time 1.33 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201444 kb
Host smart-a114685c-00da-4d25-9f43-e96470163b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81849265 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.81849265
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.880037851
Short name T124
Test name
Test status
Simulation time 474804857 ps
CPU time 0.93 seconds
Started Aug 11 06:22:54 PM PDT 24
Finished Aug 11 06:22:55 PM PDT 24
Peak memory 201352 kb
Host smart-0b690227-8dd8-4f87-a471-03422e7fec9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880037851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.880037851
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1818639002
Short name T814
Test name
Test status
Simulation time 308293210 ps
CPU time 0.85 seconds
Started Aug 11 06:22:55 PM PDT 24
Finished Aug 11 06:22:56 PM PDT 24
Peak memory 201344 kb
Host smart-9eb5a99d-051a-480d-9356-b55a7cba8bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818639002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1818639002
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2926044264
Short name T818
Test name
Test status
Simulation time 4111157019 ps
CPU time 4.83 seconds
Started Aug 11 06:22:52 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201556 kb
Host smart-b9761549-1ded-429e-b1a3-d4c68fdd5a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926044264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2926044264
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3870192679
Short name T822
Test name
Test status
Simulation time 544918584 ps
CPU time 2.94 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 217676 kb
Host smart-918597d8-dd03-48a5-a025-6a08cdda3d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870192679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3870192679
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1483105398
Short name T842
Test name
Test status
Simulation time 4380946844 ps
CPU time 11.38 seconds
Started Aug 11 06:22:40 PM PDT 24
Finished Aug 11 06:22:51 PM PDT 24
Peak memory 201684 kb
Host smart-0adddec8-6782-445e-9c15-248e35eac412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483105398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1483105398
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2218780856
Short name T83
Test name
Test status
Simulation time 393751972 ps
CPU time 1.8 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201456 kb
Host smart-97e6fdad-de32-4a29-9425-f198b5614d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218780856 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2218780856
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2746187313
Short name T878
Test name
Test status
Simulation time 331998414 ps
CPU time 0.9 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201340 kb
Host smart-6dff69f3-311e-4787-9f4e-58099b41907e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746187313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2746187313
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3083888702
Short name T824
Test name
Test status
Simulation time 341483812 ps
CPU time 1.37 seconds
Started Aug 11 06:22:50 PM PDT 24
Finished Aug 11 06:22:52 PM PDT 24
Peak memory 201304 kb
Host smart-189554cd-d9ff-40bc-ae17-45dc0bc23ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083888702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3083888702
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2972868310
Short name T833
Test name
Test status
Simulation time 4628805846 ps
CPU time 4.74 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 201616 kb
Host smart-5f4fdbe9-e3ee-48fd-861d-7b3ab05fc07b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972868310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2972868310
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2765332099
Short name T71
Test name
Test status
Simulation time 717844788 ps
CPU time 1.86 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201640 kb
Host smart-0f797822-ad22-478b-8e5e-b64c3b364176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765332099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2765332099
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.749172541
Short name T74
Test name
Test status
Simulation time 4357621693 ps
CPU time 6.67 seconds
Started Aug 11 06:22:59 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201608 kb
Host smart-cf352046-48b3-4f6c-9ce2-7edf2bf69934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749172541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.749172541
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1662828813
Short name T854
Test name
Test status
Simulation time 492737205 ps
CPU time 1.17 seconds
Started Aug 11 06:23:03 PM PDT 24
Finished Aug 11 06:23:04 PM PDT 24
Peak memory 201520 kb
Host smart-611c329a-c9cb-4dc0-9def-b1ebb594075d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662828813 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1662828813
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2016564318
Short name T139
Test name
Test status
Simulation time 357591742 ps
CPU time 1.14 seconds
Started Aug 11 06:23:02 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201336 kb
Host smart-dca3fb0d-da96-4abb-9ea5-c15da0fbbbc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016564318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2016564318
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4230904203
Short name T794
Test name
Test status
Simulation time 334879033 ps
CPU time 1.39 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201324 kb
Host smart-160d7f36-8447-4ed9-a67c-68f7a5f185e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230904203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4230904203
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3012063947
Short name T899
Test name
Test status
Simulation time 4897126134 ps
CPU time 6.53 seconds
Started Aug 11 06:23:11 PM PDT 24
Finished Aug 11 06:23:17 PM PDT 24
Peak memory 201572 kb
Host smart-68245c78-5051-49ce-96b2-b6def67a18c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012063947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3012063947
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.640398710
Short name T84
Test name
Test status
Simulation time 445742758 ps
CPU time 1.7 seconds
Started Aug 11 06:22:59 PM PDT 24
Finished Aug 11 06:23:01 PM PDT 24
Peak memory 201672 kb
Host smart-fda525d2-fbcb-4633-ae94-c2c23286126f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640398710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.640398710
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3917212303
Short name T374
Test name
Test status
Simulation time 8239177363 ps
CPU time 20.73 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:23:18 PM PDT 24
Peak memory 201684 kb
Host smart-11da8670-e464-4d84-9af7-798468e9ab8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917212303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3917212303
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1790168703
Short name T851
Test name
Test status
Simulation time 356401296 ps
CPU time 1.4 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201300 kb
Host smart-e88a8dba-c6b2-4c27-bdc3-410e1324f2d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790168703 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1790168703
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3190739144
Short name T129
Test name
Test status
Simulation time 535162086 ps
CPU time 0.85 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 201328 kb
Host smart-8c3ef533-037a-46f2-ab97-b0a36fd2d2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190739144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3190739144
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.189482426
Short name T812
Test name
Test status
Simulation time 421200076 ps
CPU time 0.9 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 201348 kb
Host smart-91193a64-403e-412b-933c-8afb341ab5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189482426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.189482426
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2259169704
Short name T844
Test name
Test status
Simulation time 3827532356 ps
CPU time 4.67 seconds
Started Aug 11 06:23:16 PM PDT 24
Finished Aug 11 06:23:21 PM PDT 24
Peak memory 201572 kb
Host smart-e8e4d113-d726-4e47-a6ba-aa469ee27958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259169704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2259169704
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4166504533
Short name T908
Test name
Test status
Simulation time 600351816 ps
CPU time 3.24 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:04 PM PDT 24
Peak memory 201660 kb
Host smart-0aa83fe1-faa7-4a5f-aff0-6831eebed69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166504533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4166504533
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1914407740
Short name T893
Test name
Test status
Simulation time 396158239 ps
CPU time 0.99 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 201472 kb
Host smart-1a839fb1-da7b-492c-8836-db2bc4f46fa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914407740 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1914407740
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.500186010
Short name T134
Test name
Test status
Simulation time 394554959 ps
CPU time 1.26 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201384 kb
Host smart-fd4befaa-9066-40ce-9e4d-5173874d9235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500186010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.500186010
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1975022624
Short name T873
Test name
Test status
Simulation time 508040414 ps
CPU time 0.92 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 201336 kb
Host smart-9dd8af7e-be3a-4042-a8ad-f7500db0f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975022624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1975022624
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.819833790
Short name T904
Test name
Test status
Simulation time 2348278246 ps
CPU time 2.57 seconds
Started Aug 11 06:23:15 PM PDT 24
Finished Aug 11 06:23:22 PM PDT 24
Peak memory 201372 kb
Host smart-b11a1c92-ed6e-42fc-98a3-4c058b5195cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819833790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.819833790
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.329379776
Short name T821
Test name
Test status
Simulation time 419470964 ps
CPU time 2.61 seconds
Started Aug 11 06:23:10 PM PDT 24
Finished Aug 11 06:23:13 PM PDT 24
Peak memory 218024 kb
Host smart-26b899d4-4a4a-4cdd-bfdb-a2db4643ea31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329379776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.329379776
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4008343519
Short name T135
Test name
Test status
Simulation time 1219786407 ps
CPU time 2.71 seconds
Started Aug 11 06:22:53 PM PDT 24
Finished Aug 11 06:22:56 PM PDT 24
Peak memory 201444 kb
Host smart-bef24c8a-282f-4945-8507-9c193c6ab56e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008343519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4008343519
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2364950843
Short name T868
Test name
Test status
Simulation time 25974620982 ps
CPU time 123.13 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:24:41 PM PDT 24
Peak memory 201544 kb
Host smart-610ebfe7-1c6a-494f-bc23-a71122b7fb4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364950843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2364950843
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2866972107
Short name T896
Test name
Test status
Simulation time 1082584772 ps
CPU time 3.23 seconds
Started Aug 11 06:22:59 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 200272 kb
Host smart-20acab81-b36d-4779-9a38-f723f5251b14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866972107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2866972107
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2033579763
Short name T864
Test name
Test status
Simulation time 386261097 ps
CPU time 1.89 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:43 PM PDT 24
Peak memory 201456 kb
Host smart-921f6fa4-3433-46c4-ae8e-e3c33406cd72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033579763 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2033579763
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1578269611
Short name T895
Test name
Test status
Simulation time 359546025 ps
CPU time 1.11 seconds
Started Aug 11 06:22:39 PM PDT 24
Finished Aug 11 06:22:41 PM PDT 24
Peak memory 201364 kb
Host smart-d2e0ca3a-b492-4378-b59c-86e407132b95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578269611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1578269611
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2901692135
Short name T801
Test name
Test status
Simulation time 528992083 ps
CPU time 0.98 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201336 kb
Host smart-f67d33d1-de94-4990-acc1-b069c9559e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901692135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2901692135
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2127963669
Short name T808
Test name
Test status
Simulation time 2563565872 ps
CPU time 2.24 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 201280 kb
Host smart-685c604e-65f1-45c6-beac-49fe93ff6bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127963669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2127963669
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1256430874
Short name T836
Test name
Test status
Simulation time 549092495 ps
CPU time 2.82 seconds
Started Aug 11 06:22:45 PM PDT 24
Finished Aug 11 06:22:48 PM PDT 24
Peak memory 201640 kb
Host smart-dc68dbdf-a07a-47c4-9a8f-2efdfcf105b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256430874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1256430874
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.138141564
Short name T865
Test name
Test status
Simulation time 8586158124 ps
CPU time 6.48 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:22:44 PM PDT 24
Peak memory 201636 kb
Host smart-4ebcdc55-f49b-45be-924d-e61d9d081e44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138141564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.138141564
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3297087414
Short name T811
Test name
Test status
Simulation time 326588022 ps
CPU time 1.38 seconds
Started Aug 11 06:23:07 PM PDT 24
Finished Aug 11 06:23:08 PM PDT 24
Peak memory 201344 kb
Host smart-f8b716a9-bb70-4ba0-9dd2-778f96d043ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297087414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3297087414
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3469262646
Short name T883
Test name
Test status
Simulation time 447988112 ps
CPU time 1.65 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201356 kb
Host smart-16e27ce0-b25d-4247-bbcb-ff7aaa14e486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469262646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3469262646
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2479389357
Short name T832
Test name
Test status
Simulation time 535120339 ps
CPU time 0.76 seconds
Started Aug 11 06:22:53 PM PDT 24
Finished Aug 11 06:22:53 PM PDT 24
Peak memory 201356 kb
Host smart-74552068-68df-42ce-905b-a4b8c1d3d967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479389357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2479389357
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.966915440
Short name T862
Test name
Test status
Simulation time 409146101 ps
CPU time 1.56 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201304 kb
Host smart-671aeff4-2455-4774-a84f-b2a935d580b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966915440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.966915440
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.855110793
Short name T879
Test name
Test status
Simulation time 567661757 ps
CPU time 0.81 seconds
Started Aug 11 06:23:11 PM PDT 24
Finished Aug 11 06:23:12 PM PDT 24
Peak memory 201320 kb
Host smart-73f51924-f9ab-41af-869d-a781b3d5b7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855110793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.855110793
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1588859117
Short name T919
Test name
Test status
Simulation time 309839272 ps
CPU time 1.37 seconds
Started Aug 11 06:23:08 PM PDT 24
Finished Aug 11 06:23:09 PM PDT 24
Peak memory 201356 kb
Host smart-014c8f8b-5ca8-4f2b-855e-613a43a1c677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588859117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1588859117
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.860729321
Short name T810
Test name
Test status
Simulation time 345046005 ps
CPU time 0.85 seconds
Started Aug 11 06:23:09 PM PDT 24
Finished Aug 11 06:23:10 PM PDT 24
Peak memory 201388 kb
Host smart-cceed58b-66d2-4904-8c60-46f461a37b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860729321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.860729321
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4216618770
Short name T866
Test name
Test status
Simulation time 331633650 ps
CPU time 0.79 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201332 kb
Host smart-c84df46d-4540-4378-b5c6-b69c404881a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216618770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.4216618770
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1720604130
Short name T909
Test name
Test status
Simulation time 472029207 ps
CPU time 1.11 seconds
Started Aug 11 06:23:06 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201352 kb
Host smart-97a8fd16-cb67-4c7d-b434-908df95801f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720604130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1720604130
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2670533908
Short name T796
Test name
Test status
Simulation time 322421354 ps
CPU time 1.35 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201356 kb
Host smart-aa5d888c-4290-449d-96ab-77510333c2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670533908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2670533908
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2684271108
Short name T884
Test name
Test status
Simulation time 686331483 ps
CPU time 2.25 seconds
Started Aug 11 06:22:48 PM PDT 24
Finished Aug 11 06:22:50 PM PDT 24
Peak memory 201524 kb
Host smart-d3b1ca26-79ae-4feb-819a-e3cebaccfb88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684271108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2684271108
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1709206533
Short name T136
Test name
Test status
Simulation time 40498740273 ps
CPU time 139.77 seconds
Started Aug 11 06:22:35 PM PDT 24
Finished Aug 11 06:24:55 PM PDT 24
Peak memory 201516 kb
Host smart-443589c9-ff12-4825-9933-d8412dc06273
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709206533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1709206533
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.894880377
Short name T880
Test name
Test status
Simulation time 572712876 ps
CPU time 1.81 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:39 PM PDT 24
Peak memory 201400 kb
Host smart-1e8c3702-7ab3-4c0a-8a4d-3de45611a3cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894880377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.894880377
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.923863267
Short name T898
Test name
Test status
Simulation time 575647004 ps
CPU time 1.42 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:43 PM PDT 24
Peak memory 201456 kb
Host smart-7f5b9e9f-7510-4209-bfbc-247c88901607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923863267 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.923863267
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1828008351
Short name T133
Test name
Test status
Simulation time 504740554 ps
CPU time 1.41 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 201400 kb
Host smart-65e1704c-fb0b-4797-bdfb-89647080386c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828008351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1828008351
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4126810949
Short name T834
Test name
Test status
Simulation time 464048462 ps
CPU time 1.15 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:39 PM PDT 24
Peak memory 201260 kb
Host smart-6dd3c31b-ae33-4632-a542-af522e0965eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126810949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4126810949
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1094132687
Short name T850
Test name
Test status
Simulation time 5019899705 ps
CPU time 11.89 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:23:09 PM PDT 24
Peak memory 201592 kb
Host smart-d67cd589-514f-4f9f-adbe-282ae77ccab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094132687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1094132687
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1180827786
Short name T906
Test name
Test status
Simulation time 4115640723 ps
CPU time 10.03 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:46 PM PDT 24
Peak memory 201824 kb
Host smart-3f8f88d7-8690-4d46-a6e8-11d5bfb3a4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180827786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1180827786
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3029418753
Short name T877
Test name
Test status
Simulation time 405884892 ps
CPU time 0.86 seconds
Started Aug 11 06:23:06 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201292 kb
Host smart-8989686d-5ea3-491a-9816-5cbb1025daf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029418753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3029418753
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1380009603
Short name T875
Test name
Test status
Simulation time 445696034 ps
CPU time 0.88 seconds
Started Aug 11 06:23:06 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201292 kb
Host smart-941481c0-1dfd-4094-960b-e4faa9eba543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380009603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1380009603
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2102807496
Short name T797
Test name
Test status
Simulation time 530556633 ps
CPU time 0.93 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201332 kb
Host smart-7b71ec4f-d1c5-4a6a-949b-ab85626fd6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102807496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2102807496
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3398495691
Short name T863
Test name
Test status
Simulation time 355966143 ps
CPU time 0.83 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 201292 kb
Host smart-3ad56b0d-81e7-466c-b0e4-d14f0f305c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398495691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3398495691
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1080231918
Short name T799
Test name
Test status
Simulation time 345008458 ps
CPU time 1.27 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201380 kb
Host smart-e1b1e389-5a9a-4ff9-b050-84bfe6728dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080231918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1080231918
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3756272356
Short name T829
Test name
Test status
Simulation time 368756697 ps
CPU time 0.85 seconds
Started Aug 11 06:23:10 PM PDT 24
Finished Aug 11 06:23:11 PM PDT 24
Peak memory 201308 kb
Host smart-fa782d30-7d9d-4bb5-ab84-3897390efb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756272356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3756272356
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.386232252
Short name T892
Test name
Test status
Simulation time 542535964 ps
CPU time 0.78 seconds
Started Aug 11 06:23:05 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201368 kb
Host smart-b5fced2a-a124-497c-bfa1-8f38f8258ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386232252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.386232252
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2396326075
Short name T798
Test name
Test status
Simulation time 539029005 ps
CPU time 0.92 seconds
Started Aug 11 06:23:02 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201160 kb
Host smart-792851b7-5cfd-451e-9b46-a5b736d062ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396326075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2396326075
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1170153821
Short name T831
Test name
Test status
Simulation time 460515453 ps
CPU time 0.94 seconds
Started Aug 11 06:23:02 PM PDT 24
Finished Aug 11 06:23:03 PM PDT 24
Peak memory 201328 kb
Host smart-d11a07bb-07b0-40ea-87b6-6a5f51dca147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170153821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1170153821
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1162425711
Short name T871
Test name
Test status
Simulation time 458899149 ps
CPU time 0.96 seconds
Started Aug 11 06:23:01 PM PDT 24
Finished Aug 11 06:23:02 PM PDT 24
Peak memory 201348 kb
Host smart-487d3859-3006-4620-bdd0-f4ecf7c04559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162425711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1162425711
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.956185394
Short name T914
Test name
Test status
Simulation time 1334451635 ps
CPU time 2.57 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:39 PM PDT 24
Peak memory 201576 kb
Host smart-e65e744b-0eef-479c-af9a-988803a0d598
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956185394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.956185394
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2030837038
Short name T65
Test name
Test status
Simulation time 26597249596 ps
CPU time 60.1 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:23:37 PM PDT 24
Peak memory 201624 kb
Host smart-a5314a26-2515-4954-bcdf-a424c88ff9bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030837038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2030837038
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2201987487
Short name T815
Test name
Test status
Simulation time 735976733 ps
CPU time 1.17 seconds
Started Aug 11 06:22:39 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 201364 kb
Host smart-53df079b-9ab4-4619-b759-bcfdecf6dfdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201987487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2201987487
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3305803184
Short name T827
Test name
Test status
Simulation time 443257795 ps
CPU time 1.1 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 201468 kb
Host smart-398ea414-67e9-481c-a0c5-784e6cb97f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305803184 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3305803184
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.511034330
Short name T138
Test name
Test status
Simulation time 513562062 ps
CPU time 1.98 seconds
Started Aug 11 06:22:42 PM PDT 24
Finished Aug 11 06:22:44 PM PDT 24
Peak memory 201216 kb
Host smart-9aa128ff-b156-41ff-80ad-24f62b4b6c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511034330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.511034330
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3987494619
Short name T803
Test name
Test status
Simulation time 415199955 ps
CPU time 0.92 seconds
Started Aug 11 06:22:35 PM PDT 24
Finished Aug 11 06:22:36 PM PDT 24
Peak memory 201380 kb
Host smart-f37f90c0-986e-44d5-b78e-43ab8006cbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987494619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3987494619
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2584919782
Short name T861
Test name
Test status
Simulation time 2415752249 ps
CPU time 5.86 seconds
Started Aug 11 06:22:39 PM PDT 24
Finished Aug 11 06:22:45 PM PDT 24
Peak memory 201420 kb
Host smart-4a248045-7ad1-40d0-884a-b1af2cbc6919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584919782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2584919782
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1329393216
Short name T73
Test name
Test status
Simulation time 429453601 ps
CPU time 2.58 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201632 kb
Host smart-39de0591-0686-42e7-97eb-838304f18cee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329393216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1329393216
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2113618741
Short name T69
Test name
Test status
Simulation time 8156016717 ps
CPU time 12.05 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:22:50 PM PDT 24
Peak memory 201680 kb
Host smart-9cceb7fe-7adc-483a-8224-b5f9c3cfa08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113618741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2113618741
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2945198845
Short name T807
Test name
Test status
Simulation time 327254612 ps
CPU time 1.43 seconds
Started Aug 11 06:23:03 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 201340 kb
Host smart-461e3253-2149-4b25-85a9-d9021a023681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945198845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2945198845
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.61780692
Short name T835
Test name
Test status
Simulation time 321907927 ps
CPU time 1.05 seconds
Started Aug 11 06:23:00 PM PDT 24
Finished Aug 11 06:23:01 PM PDT 24
Peak memory 201244 kb
Host smart-5f3e615b-575d-4702-b84f-720f50be0a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61780692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.61780692
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.480102750
Short name T918
Test name
Test status
Simulation time 306253334 ps
CPU time 1.3 seconds
Started Aug 11 06:23:06 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201372 kb
Host smart-f29ade34-f4d5-4d2e-82b8-4a02b08a4f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480102750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.480102750
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3366936299
Short name T894
Test name
Test status
Simulation time 351968049 ps
CPU time 1.13 seconds
Started Aug 11 06:23:12 PM PDT 24
Finished Aug 11 06:23:14 PM PDT 24
Peak memory 201372 kb
Host smart-fb92afed-7dc6-4251-8942-b17fe60e2b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366936299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3366936299
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.213929667
Short name T891
Test name
Test status
Simulation time 335085932 ps
CPU time 1.36 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201528 kb
Host smart-d8b84f82-6a09-4d57-9538-1f736626d7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213929667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.213929667
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4276975138
Short name T820
Test name
Test status
Simulation time 332381910 ps
CPU time 1.01 seconds
Started Aug 11 06:23:08 PM PDT 24
Finished Aug 11 06:23:09 PM PDT 24
Peak memory 201328 kb
Host smart-468fcf20-8690-4408-b59b-0e60a9245179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276975138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4276975138
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3080729830
Short name T900
Test name
Test status
Simulation time 438120314 ps
CPU time 1.64 seconds
Started Aug 11 06:23:05 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201336 kb
Host smart-192a06ee-f261-4ceb-a6d5-1fc1c689cf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080729830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3080729830
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3131580130
Short name T795
Test name
Test status
Simulation time 519999766 ps
CPU time 0.75 seconds
Started Aug 11 06:22:59 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201328 kb
Host smart-e9242ff3-1b8d-488c-8399-45b30e8dbc67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131580130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3131580130
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3204567012
Short name T805
Test name
Test status
Simulation time 450175541 ps
CPU time 1.15 seconds
Started Aug 11 06:23:05 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201376 kb
Host smart-7e5cc1a2-27b7-4560-9a89-913b8012d8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204567012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3204567012
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3589247830
Short name T860
Test name
Test status
Simulation time 533809922 ps
CPU time 1.2 seconds
Started Aug 11 06:23:07 PM PDT 24
Finished Aug 11 06:23:08 PM PDT 24
Peak memory 201324 kb
Host smart-e3a232b4-0a24-44e8-9fa1-af1b070454f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589247830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3589247830
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3740606551
Short name T916
Test name
Test status
Simulation time 513273465 ps
CPU time 1.84 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201460 kb
Host smart-2fcd81ed-c64c-48c8-adf4-caa173681c97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740606551 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3740606551
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.118270556
Short name T886
Test name
Test status
Simulation time 459626019 ps
CPU time 1.32 seconds
Started Aug 11 06:22:54 PM PDT 24
Finished Aug 11 06:22:55 PM PDT 24
Peak memory 201336 kb
Host smart-24eecfd5-eb09-4fdd-9760-cedf11c10a74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118270556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.118270556
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3742585879
Short name T819
Test name
Test status
Simulation time 323702207 ps
CPU time 0.82 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 201324 kb
Host smart-6779cde8-aa35-4012-b1cc-998838977974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742585879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3742585879
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.752690251
Short name T137
Test name
Test status
Simulation time 2492405535 ps
CPU time 2.73 seconds
Started Aug 11 06:22:46 PM PDT 24
Finished Aug 11 06:22:49 PM PDT 24
Peak memory 201448 kb
Host smart-2b2e5172-d993-40ac-8986-cea4e5a6e233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752690251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.752690251
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.797803849
Short name T78
Test name
Test status
Simulation time 411910165 ps
CPU time 2.93 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 209800 kb
Host smart-42d479fe-97e4-497d-9ef2-cf75ec829d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797803849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.797803849
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1230397080
Short name T375
Test name
Test status
Simulation time 8796585521 ps
CPU time 21.79 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 201688 kb
Host smart-94747d0c-25d1-4c0f-9c96-86f934f8d617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230397080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1230397080
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3066300230
Short name T826
Test name
Test status
Simulation time 490032145 ps
CPU time 1.92 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201484 kb
Host smart-e7c189b8-b180-4dfc-9a1d-2e556a8f095e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066300230 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3066300230
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3274300399
Short name T915
Test name
Test status
Simulation time 311007571 ps
CPU time 1.42 seconds
Started Aug 11 06:22:35 PM PDT 24
Finished Aug 11 06:22:37 PM PDT 24
Peak memory 201272 kb
Host smart-41aef9ff-0283-411f-b446-c7e5ca462b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274300399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3274300399
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2980585095
Short name T888
Test name
Test status
Simulation time 391418286 ps
CPU time 0.86 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201368 kb
Host smart-c4eab873-7ea8-4964-8d52-1eae823227f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980585095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2980585095
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.837040056
Short name T848
Test name
Test status
Simulation time 4740672534 ps
CPU time 6.4 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:44 PM PDT 24
Peak memory 201580 kb
Host smart-69385cff-1bd6-491b-9ee7-29ef4561a7de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837040056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.837040056
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1371363370
Short name T903
Test name
Test status
Simulation time 500008582 ps
CPU time 1.49 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201620 kb
Host smart-d107d787-8df4-4d7b-9d35-edc1566b7620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371363370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1371363370
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3783141115
Short name T85
Test name
Test status
Simulation time 9393313176 ps
CPU time 7.44 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:45 PM PDT 24
Peak memory 201664 kb
Host smart-ce04df11-ee4b-4480-8cbb-11d6d722b9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783141115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3783141115
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3444017368
Short name T806
Test name
Test status
Simulation time 440847452 ps
CPU time 1.19 seconds
Started Aug 11 06:22:35 PM PDT 24
Finished Aug 11 06:22:37 PM PDT 24
Peak memory 201432 kb
Host smart-8dfe7074-6d2a-4b08-82bd-bfc4039a742c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444017368 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3444017368
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3796945432
Short name T125
Test name
Test status
Simulation time 654496279 ps
CPU time 0.91 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:37 PM PDT 24
Peak memory 201388 kb
Host smart-b407f37c-dd10-4961-a628-9b9dad52c2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796945432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3796945432
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3236438846
Short name T823
Test name
Test status
Simulation time 499857127 ps
CPU time 1.8 seconds
Started Aug 11 06:22:57 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 201388 kb
Host smart-291aa5bb-63c1-4cd9-b108-fc86e1688970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236438846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3236438846
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1615682197
Short name T66
Test name
Test status
Simulation time 2534657343 ps
CPU time 11.99 seconds
Started Aug 11 06:23:09 PM PDT 24
Finished Aug 11 06:23:21 PM PDT 24
Peak memory 201408 kb
Host smart-d642316f-8233-4523-8127-10a6a0b0d144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615682197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1615682197
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.208362052
Short name T72
Test name
Test status
Simulation time 666145306 ps
CPU time 1.82 seconds
Started Aug 11 06:22:58 PM PDT 24
Finished Aug 11 06:23:00 PM PDT 24
Peak memory 217844 kb
Host smart-2f85ffbf-7f99-4133-9e82-e087b5e55421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208362052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.208362052
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2689185886
Short name T859
Test name
Test status
Simulation time 8764343660 ps
CPU time 7.16 seconds
Started Aug 11 06:22:41 PM PDT 24
Finished Aug 11 06:22:49 PM PDT 24
Peak memory 201604 kb
Host smart-815adc96-4568-4aff-8447-b1f6c5e16fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689185886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2689185886
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.570137240
Short name T857
Test name
Test status
Simulation time 428674018 ps
CPU time 1.44 seconds
Started Aug 11 06:23:04 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 201464 kb
Host smart-a134bdee-1a82-40d8-9f9a-52a051a36bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570137240 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.570137240
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4104832199
Short name T127
Test name
Test status
Simulation time 378528999 ps
CPU time 0.89 seconds
Started Aug 11 06:22:46 PM PDT 24
Finished Aug 11 06:22:47 PM PDT 24
Peak memory 201320 kb
Host smart-fd772fdc-b186-4664-a291-78880ec3446c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104832199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4104832199
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4250153421
Short name T809
Test name
Test status
Simulation time 570694671 ps
CPU time 0.87 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:22:57 PM PDT 24
Peak memory 201304 kb
Host smart-06d7795c-aca7-44e5-a7dd-96dca61fb5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250153421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4250153421
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2504790481
Short name T889
Test name
Test status
Simulation time 4622447085 ps
CPU time 17.56 seconds
Started Aug 11 06:22:56 PM PDT 24
Finished Aug 11 06:23:14 PM PDT 24
Peak memory 201576 kb
Host smart-d52b2946-d5ef-475c-869c-2b5ed474d327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504790481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2504790481
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2906091599
Short name T870
Test name
Test status
Simulation time 420265764 ps
CPU time 2.51 seconds
Started Aug 11 06:22:38 PM PDT 24
Finished Aug 11 06:22:41 PM PDT 24
Peak memory 201584 kb
Host smart-8345a955-daa5-47b6-bbb0-f090cf234919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906091599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2906091599
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.259708660
Short name T887
Test name
Test status
Simulation time 8645949360 ps
CPU time 12.8 seconds
Started Aug 11 06:22:54 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 201644 kb
Host smart-cc4ac041-014c-42b2-be98-8d8de83b4ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259708660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.259708660
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2844310678
Short name T885
Test name
Test status
Simulation time 332016584 ps
CPU time 1.27 seconds
Started Aug 11 06:22:45 PM PDT 24
Finished Aug 11 06:22:47 PM PDT 24
Peak memory 201472 kb
Host smart-a7cb730e-53a7-4cab-ae82-e9713c45c2c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844310678 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2844310678
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.802033160
Short name T132
Test name
Test status
Simulation time 389771826 ps
CPU time 0.89 seconds
Started Aug 11 06:22:37 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 201316 kb
Host smart-c8f10e63-bf42-46fb-bba0-2cfc41a79031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802033160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.802033160
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1532893878
Short name T828
Test name
Test status
Simulation time 404859956 ps
CPU time 0.84 seconds
Started Aug 11 06:22:39 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 201380 kb
Host smart-4751914d-c831-4bd6-8f1b-ec915c4fc9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532893878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1532893878
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3877724320
Short name T64
Test name
Test status
Simulation time 4329135909 ps
CPU time 5.55 seconds
Started Aug 11 06:22:52 PM PDT 24
Finished Aug 11 06:22:58 PM PDT 24
Peak memory 201560 kb
Host smart-489af75c-79c7-4238-83e0-3423bfa393d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877724320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3877724320
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2437395109
Short name T905
Test name
Test status
Simulation time 605414269 ps
CPU time 3.7 seconds
Started Aug 11 06:22:49 PM PDT 24
Finished Aug 11 06:22:53 PM PDT 24
Peak memory 217512 kb
Host smart-13dc565a-90ca-447a-be5a-58a06956e0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437395109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2437395109
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2807808276
Short name T911
Test name
Test status
Simulation time 9154742503 ps
CPU time 3.47 seconds
Started Aug 11 06:22:36 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 201688 kb
Host smart-5c04b489-0ba9-4b2e-87dd-4c9cde73cb47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807808276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2807808276
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2064419808
Short name T477
Test name
Test status
Simulation time 356389099 ps
CPU time 0.81 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:40:49 PM PDT 24
Peak memory 201236 kb
Host smart-483609bb-eed9-4dac-8e01-81eca32075cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064419808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2064419808
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1339669210
Short name T108
Test name
Test status
Simulation time 595850309853 ps
CPU time 358.31 seconds
Started Aug 11 06:40:43 PM PDT 24
Finished Aug 11 06:46:42 PM PDT 24
Peak memory 201460 kb
Host smart-6db65858-69d7-4d26-9ced-2587808600bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339669210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1339669210
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3566247054
Short name T272
Test name
Test status
Simulation time 332469952743 ps
CPU time 752.47 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:53:22 PM PDT 24
Peak memory 201440 kb
Host smart-4f47787a-b4d6-468e-85f1-e22dea453182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566247054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3566247054
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2313465343
Short name T560
Test name
Test status
Simulation time 326057066520 ps
CPU time 761.53 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:53:27 PM PDT 24
Peak memory 201504 kb
Host smart-82fd2092-7bac-46af-834c-f960a342786c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313465343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2313465343
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2704892092
Short name T541
Test name
Test status
Simulation time 326910119651 ps
CPU time 331.5 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:46:21 PM PDT 24
Peak memory 201480 kb
Host smart-6e4a490d-edb8-4d7c-bf4a-d1453f4722a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704892092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2704892092
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1892914268
Short name T355
Test name
Test status
Simulation time 167059099511 ps
CPU time 50.49 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 201436 kb
Host smart-d284fc44-9e3f-4b31-9549-0519b2957cfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892914268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1892914268
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1468424757
Short name T2
Test name
Test status
Simulation time 208635612324 ps
CPU time 179.97 seconds
Started Aug 11 06:40:43 PM PDT 24
Finished Aug 11 06:43:43 PM PDT 24
Peak memory 201416 kb
Host smart-b2982af9-ce13-4274-b4a6-13bd32bbac4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468424757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1468424757
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3248843710
Short name T419
Test name
Test status
Simulation time 34145185744 ps
CPU time 21.41 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:41:12 PM PDT 24
Peak memory 201348 kb
Host smart-760234ff-1886-48e4-809a-334f230a425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248843710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3248843710
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4248808169
Short name T470
Test name
Test status
Simulation time 4133696376 ps
CPU time 9.75 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:40:58 PM PDT 24
Peak memory 201288 kb
Host smart-8243e4d0-dc25-4167-bc1b-ae29946b7f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248808169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4248808169
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2409670079
Short name T782
Test name
Test status
Simulation time 5676634850 ps
CPU time 4.44 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:40:50 PM PDT 24
Peak memory 201332 kb
Host smart-887055fa-dd36-4a3b-a489-cf4a4d57b7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409670079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2409670079
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1565455254
Short name T94
Test name
Test status
Simulation time 174624773683 ps
CPU time 190.93 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:43:59 PM PDT 24
Peak memory 201416 kb
Host smart-aa98f4a5-3883-4440-9614-16376d69d65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565455254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1565455254
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4174847112
Short name T119
Test name
Test status
Simulation time 12866327187 ps
CPU time 32.46 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:41:22 PM PDT 24
Peak memory 210208 kb
Host smart-c870da63-bbed-4bc0-b369-13d962c9c4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174847112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4174847112
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.177218828
Short name T758
Test name
Test status
Simulation time 437671358 ps
CPU time 1.08 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:40:52 PM PDT 24
Peak memory 201212 kb
Host smart-ee1fb460-94bf-4225-b2aa-875b8decca1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177218828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.177218828
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4287795977
Short name T346
Test name
Test status
Simulation time 514822557751 ps
CPU time 312.06 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:46:03 PM PDT 24
Peak memory 201448 kb
Host smart-afe2cb21-021a-42ef-a674-9c998058ec62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287795977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4287795977
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2561519727
Short name T347
Test name
Test status
Simulation time 158552761850 ps
CPU time 91.15 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:42:21 PM PDT 24
Peak memory 201420 kb
Host smart-5c5232a4-47ff-477a-a967-83c86923fb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561519727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2561519727
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2803081475
Short name T480
Test name
Test status
Simulation time 166226951422 ps
CPU time 190.76 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:44:03 PM PDT 24
Peak memory 201448 kb
Host smart-1c4c7329-e648-487b-bcb9-eb51a798aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803081475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2803081475
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.70742259
Short name T502
Test name
Test status
Simulation time 491048638798 ps
CPU time 305.51 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:45:51 PM PDT 24
Peak memory 201428 kb
Host smart-1efb6312-4930-4b58-81e0-56ab75fb8a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70742259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.70742259
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1638492631
Short name T785
Test name
Test status
Simulation time 164423110446 ps
CPU time 380.49 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 201352 kb
Host smart-e8d01c68-bfb1-445f-966e-38b7ce464edb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638492631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1638492631
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.221814259
Short name T50
Test name
Test status
Simulation time 208969838150 ps
CPU time 470.32 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:48:39 PM PDT 24
Peak memory 201404 kb
Host smart-3de02896-2e40-4ad5-89bc-785d6c77bd99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221814259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.221814259
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1447374269
Short name T730
Test name
Test status
Simulation time 81337405170 ps
CPU time 394.89 seconds
Started Aug 11 06:40:42 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 201760 kb
Host smart-dd37c806-0897-46b9-b47f-66f98b7619df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447374269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1447374269
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1688678819
Short name T554
Test name
Test status
Simulation time 33229503879 ps
CPU time 70.42 seconds
Started Aug 11 06:40:44 PM PDT 24
Finished Aug 11 06:41:55 PM PDT 24
Peak memory 201280 kb
Host smart-40df87a4-9f87-4f21-8a83-991d21f748aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688678819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1688678819
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4053189988
Short name T451
Test name
Test status
Simulation time 4819328389 ps
CPU time 1.51 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:40:52 PM PDT 24
Peak memory 201304 kb
Host smart-5560cd2c-92a0-4cc4-84ce-e7f9e7f7e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053189988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4053189988
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.323653886
Short name T4
Test name
Test status
Simulation time 4637306648 ps
CPU time 7.63 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:40:58 PM PDT 24
Peak memory 217160 kb
Host smart-76b29f29-b5eb-4e4a-8e76-01dffb62e018
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323653886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.323653886
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.882562331
Short name T200
Test name
Test status
Simulation time 5611600908 ps
CPU time 11.82 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:41:00 PM PDT 24
Peak memory 201320 kb
Host smart-cc7b8a1b-d692-4316-ac59-808a0c3ca678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882562331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.882562331
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2550286653
Short name T40
Test name
Test status
Simulation time 48828470707 ps
CPU time 57.34 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 209796 kb
Host smart-9a08b92c-63f6-4bdc-a5c9-48ee15b85945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550286653 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2550286653
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1135252466
Short name T729
Test name
Test status
Simulation time 373276163 ps
CPU time 0.83 seconds
Started Aug 11 06:41:03 PM PDT 24
Finished Aug 11 06:41:04 PM PDT 24
Peak memory 201216 kb
Host smart-b115a266-aca6-4a70-bb9c-f236029ba6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135252466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1135252466
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.675157038
Short name T280
Test name
Test status
Simulation time 176544915920 ps
CPU time 209.5 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:44:29 PM PDT 24
Peak memory 201444 kb
Host smart-d912cbb7-0ce9-4af6-b12b-656c55dfc704
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675157038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.675157038
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4084677329
Short name T645
Test name
Test status
Simulation time 339382969824 ps
CPU time 117.91 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:42:59 PM PDT 24
Peak memory 201456 kb
Host smart-6628aeff-8d9f-4bee-84dd-88098dec7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084677329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4084677329
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4196231458
Short name T441
Test name
Test status
Simulation time 164408856934 ps
CPU time 374.14 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:47:15 PM PDT 24
Peak memory 201424 kb
Host smart-9729e305-712b-4e47-a30f-460b271632a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196231458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4196231458
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2096435376
Short name T767
Test name
Test status
Simulation time 483447285208 ps
CPU time 602.33 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 201436 kb
Host smart-042a1b9f-95ae-48bf-bd85-2d1f53c9665b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096435376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2096435376
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1590825246
Short name T578
Test name
Test status
Simulation time 321423247538 ps
CPU time 191.64 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:44:11 PM PDT 24
Peak memory 201484 kb
Host smart-029734af-3da2-4ea6-86ec-80c017fc15fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590825246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1590825246
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.662028375
Short name T764
Test name
Test status
Simulation time 335077651926 ps
CPU time 212.36 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 201424 kb
Host smart-5a9c1ac3-616b-48cb-86cc-db0a4150bada
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=662028375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.662028375
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.493303494
Short name T386
Test name
Test status
Simulation time 216568248852 ps
CPU time 169.07 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:43:50 PM PDT 24
Peak memory 201428 kb
Host smart-10c70f84-2572-4b29-a55d-d9cb6714e290
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493303494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.493303494
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1282524328
Short name T703
Test name
Test status
Simulation time 97337316798 ps
CPU time 389 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:47:29 PM PDT 24
Peak memory 201852 kb
Host smart-0e0246ca-800d-45a4-93e4-4fd1ecd12cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282524328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1282524328
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.943176426
Short name T199
Test name
Test status
Simulation time 35102485836 ps
CPU time 21.13 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:41:20 PM PDT 24
Peak memory 201328 kb
Host smart-b7550103-bc0d-4d51-acfa-bcd756d50dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943176426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.943176426
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4273737137
Short name T398
Test name
Test status
Simulation time 2987456989 ps
CPU time 7.49 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:41:07 PM PDT 24
Peak memory 201324 kb
Host smart-936230fb-729d-4acd-994f-42d582bf5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273737137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4273737137
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1697228253
Short name T543
Test name
Test status
Simulation time 5791453493 ps
CPU time 2.91 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:41:04 PM PDT 24
Peak memory 201352 kb
Host smart-9c035af4-ef99-456e-8d64-be32d875974b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697228253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1697228253
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4169122357
Short name T727
Test name
Test status
Simulation time 1363160061242 ps
CPU time 2060.21 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 212148 kb
Host smart-3917e116-9c2a-4832-bc9e-3b2f23e7f113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169122357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4169122357
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2617542454
Short name T18
Test name
Test status
Simulation time 20716753079 ps
CPU time 48.91 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 211044 kb
Host smart-7c14573a-f900-4c2a-a689-c57907f1c990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617542454 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2617542454
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2690018351
Short name T463
Test name
Test status
Simulation time 444562277 ps
CPU time 0.9 seconds
Started Aug 11 06:41:04 PM PDT 24
Finished Aug 11 06:41:05 PM PDT 24
Peak memory 201192 kb
Host smart-21d5b29a-9165-4ec9-bd60-a36f0d56e1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690018351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2690018351
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3538093256
Short name T258
Test name
Test status
Simulation time 167890787046 ps
CPU time 134.74 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:43:17 PM PDT 24
Peak memory 201544 kb
Host smart-7b9e7ad2-8743-4c52-82cc-2ad68b1251f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538093256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3538093256
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1177616168
Short name T660
Test name
Test status
Simulation time 326628184611 ps
CPU time 205.82 seconds
Started Aug 11 06:41:05 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 201416 kb
Host smart-186cd829-e5b6-4c65-9b7f-62c8d8c0a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177616168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1177616168
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3420185441
Short name T576
Test name
Test status
Simulation time 492715865039 ps
CPU time 1106.71 seconds
Started Aug 11 06:41:03 PM PDT 24
Finished Aug 11 06:59:30 PM PDT 24
Peak memory 201480 kb
Host smart-e7dbe471-2f2b-443a-b055-4c788bdb329a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420185441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3420185441
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1118616499
Short name T112
Test name
Test status
Simulation time 162799027689 ps
CPU time 37.48 seconds
Started Aug 11 06:41:04 PM PDT 24
Finished Aug 11 06:41:42 PM PDT 24
Peak memory 201224 kb
Host smart-2ef64889-8755-4774-8050-bfdaa113d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118616499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1118616499
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2441688932
Short name T486
Test name
Test status
Simulation time 333862679193 ps
CPU time 787.18 seconds
Started Aug 11 06:41:07 PM PDT 24
Finished Aug 11 06:54:14 PM PDT 24
Peak memory 201348 kb
Host smart-36b020cb-dd35-46d8-a76b-cc6e23bfa25a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441688932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2441688932
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1547374292
Short name T565
Test name
Test status
Simulation time 524181549196 ps
CPU time 616.66 seconds
Started Aug 11 06:41:07 PM PDT 24
Finished Aug 11 06:51:24 PM PDT 24
Peak memory 201340 kb
Host smart-7bb92f7a-3d9c-4a1f-a8ef-90e6ac214e9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547374292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1547374292
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3065391794
Short name T403
Test name
Test status
Simulation time 395842436364 ps
CPU time 924.22 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:56:26 PM PDT 24
Peak memory 201456 kb
Host smart-8d208bf5-a465-4df7-b6a8-1d110872c435
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065391794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3065391794
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2358519443
Short name T650
Test name
Test status
Simulation time 109994344850 ps
CPU time 547.85 seconds
Started Aug 11 06:41:03 PM PDT 24
Finished Aug 11 06:50:11 PM PDT 24
Peak memory 201816 kb
Host smart-8d188013-42ea-49da-9337-604d31f56c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358519443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2358519443
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.387078418
Short name T413
Test name
Test status
Simulation time 25251719222 ps
CPU time 57.48 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:42:00 PM PDT 24
Peak memory 201368 kb
Host smart-6b1a627b-9623-40f3-adb7-7af3e06b8be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387078418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.387078418
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2627372700
Short name T574
Test name
Test status
Simulation time 3966559721 ps
CPU time 5.62 seconds
Started Aug 11 06:41:04 PM PDT 24
Finished Aug 11 06:41:10 PM PDT 24
Peak memory 201060 kb
Host smart-092afb3a-06ff-46e9-b857-7fbec9aabcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627372700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2627372700
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1287618495
Short name T437
Test name
Test status
Simulation time 5788490868 ps
CPU time 13.78 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:41:16 PM PDT 24
Peak memory 201320 kb
Host smart-aa6b3d2d-0412-4e80-89d8-602904d4f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287618495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1287618495
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.315697261
Short name T220
Test name
Test status
Simulation time 167801953311 ps
CPU time 378.7 seconds
Started Aug 11 06:41:07 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 201360 kb
Host smart-cb2da269-a5eb-4ef8-b72e-ad87d01125fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315697261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
315697261
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4017347282
Short name T19
Test name
Test status
Simulation time 157130908316 ps
CPU time 99.99 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:42:43 PM PDT 24
Peak memory 217376 kb
Host smart-bcddff33-c4b2-4225-b29e-89562e134c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017347282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4017347282
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1636434518
Short name T596
Test name
Test status
Simulation time 514182360 ps
CPU time 1.7 seconds
Started Aug 11 06:41:14 PM PDT 24
Finished Aug 11 06:41:15 PM PDT 24
Peak memory 201264 kb
Host smart-a6b73c65-e2ae-44e4-9e65-04bcc01586d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636434518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1636434518
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3854020460
Short name T276
Test name
Test status
Simulation time 167197400934 ps
CPU time 369.49 seconds
Started Aug 11 06:41:12 PM PDT 24
Finished Aug 11 06:47:22 PM PDT 24
Peak memory 201476 kb
Host smart-934714df-ec38-4e7d-aaa6-d24f62644f5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854020460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3854020460
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4120392533
Short name T105
Test name
Test status
Simulation time 166327526539 ps
CPU time 125.36 seconds
Started Aug 11 06:41:13 PM PDT 24
Finished Aug 11 06:43:18 PM PDT 24
Peak memory 201444 kb
Host smart-eb8f9b30-bc37-4804-8c4e-b14469166a49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120392533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4120392533
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3008679708
Short name T656
Test name
Test status
Simulation time 169129780190 ps
CPU time 376.28 seconds
Started Aug 11 06:41:16 PM PDT 24
Finished Aug 11 06:47:33 PM PDT 24
Peak memory 201412 kb
Host smart-297c80bc-d214-4258-ad65-d242b939090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008679708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3008679708
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1125743766
Short name T427
Test name
Test status
Simulation time 329971250645 ps
CPU time 395.32 seconds
Started Aug 11 06:41:14 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 201460 kb
Host smart-3049ca63-5351-43d1-9968-71bb04b9ad0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125743766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1125743766
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1451655783
Short name T401
Test name
Test status
Simulation time 404914662506 ps
CPU time 478.13 seconds
Started Aug 11 06:41:25 PM PDT 24
Finished Aug 11 06:49:23 PM PDT 24
Peak memory 201344 kb
Host smart-d35bbb3d-2001-415c-8433-b0fa8fa8055f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451655783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1451655783
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2291399266
Short name T236
Test name
Test status
Simulation time 91429301914 ps
CPU time 521.53 seconds
Started Aug 11 06:41:17 PM PDT 24
Finished Aug 11 06:49:59 PM PDT 24
Peak memory 201688 kb
Host smart-9d3188bf-a138-4f39-83de-5763bccf33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291399266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2291399266
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.687791610
Short name T646
Test name
Test status
Simulation time 46205553872 ps
CPU time 15.72 seconds
Started Aug 11 06:41:21 PM PDT 24
Finished Aug 11 06:41:37 PM PDT 24
Peak memory 201188 kb
Host smart-33e8f1fc-5a54-4d62-bbb2-cab91a949951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687791610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.687791610
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2845619818
Short name T389
Test name
Test status
Simulation time 4537088796 ps
CPU time 1.38 seconds
Started Aug 11 06:41:08 PM PDT 24
Finished Aug 11 06:41:10 PM PDT 24
Peak memory 201352 kb
Host smart-1c22e724-94c3-4259-ad60-29abbce66a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845619818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2845619818
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3711177796
Short name T115
Test name
Test status
Simulation time 6048982944 ps
CPU time 7.9 seconds
Started Aug 11 06:41:29 PM PDT 24
Finished Aug 11 06:41:37 PM PDT 24
Peak memory 201324 kb
Host smart-bbbac95f-d59c-48aa-b5e0-eb9630181b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711177796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3711177796
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2190714073
Short name T282
Test name
Test status
Simulation time 172438850747 ps
CPU time 393.76 seconds
Started Aug 11 06:41:15 PM PDT 24
Finished Aug 11 06:47:49 PM PDT 24
Peak memory 201532 kb
Host smart-7d60dc35-7590-4db6-b0cb-02d5c94aaed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190714073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2190714073
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1335307523
Short name T651
Test name
Test status
Simulation time 296557059603 ps
CPU time 139.47 seconds
Started Aug 11 06:41:16 PM PDT 24
Finished Aug 11 06:43:35 PM PDT 24
Peak memory 209744 kb
Host smart-b5c045df-3742-409d-91e3-f8204e718073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335307523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1335307523
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1584249103
Short name T723
Test name
Test status
Simulation time 515078652 ps
CPU time 1.73 seconds
Started Aug 11 06:41:13 PM PDT 24
Finished Aug 11 06:41:15 PM PDT 24
Peak memory 201244 kb
Host smart-cb66a902-72bd-4939-a7aa-50541ea77bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584249103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1584249103
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3079289125
Short name T443
Test name
Test status
Simulation time 488954440463 ps
CPU time 185.02 seconds
Started Aug 11 06:41:25 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 201524 kb
Host smart-6e9e888e-ddaf-4941-b5c0-dec9b88e0094
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079289125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3079289125
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.209414309
Short name T96
Test name
Test status
Simulation time 322747102053 ps
CPU time 142.16 seconds
Started Aug 11 06:41:12 PM PDT 24
Finished Aug 11 06:43:35 PM PDT 24
Peak memory 201452 kb
Host smart-5d6ec6aa-17cb-4228-873f-7ea39970edcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209414309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.209414309
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.559922474
Short name T408
Test name
Test status
Simulation time 486084904849 ps
CPU time 555.72 seconds
Started Aug 11 06:41:10 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 201368 kb
Host smart-7a815bd1-b508-468d-9568-210813eb085e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=559922474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.559922474
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2644768538
Short name T548
Test name
Test status
Simulation time 181377513394 ps
CPU time 252.41 seconds
Started Aug 11 06:41:21 PM PDT 24
Finished Aug 11 06:45:33 PM PDT 24
Peak memory 201420 kb
Host smart-8eac05f1-8262-4b00-a5a4-431d20e47622
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644768538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2644768538
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1430856436
Short name T721
Test name
Test status
Simulation time 601024078057 ps
CPU time 634.23 seconds
Started Aug 11 06:41:18 PM PDT 24
Finished Aug 11 06:51:53 PM PDT 24
Peak memory 201492 kb
Host smart-dbeb3c29-568b-4908-82a9-193acfd71345
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430856436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1430856436
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4082695336
Short name T665
Test name
Test status
Simulation time 26461544625 ps
CPU time 17.4 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:41:49 PM PDT 24
Peak memory 201388 kb
Host smart-b1be2d21-f1ce-4ee6-855d-b10eb1eae807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082695336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4082695336
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3842319041
Short name T768
Test name
Test status
Simulation time 3478297507 ps
CPU time 8.71 seconds
Started Aug 11 06:41:29 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 201496 kb
Host smart-ccd4b355-6c8c-4359-b0a0-6a5a38f38858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842319041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3842319041
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2295781121
Short name T468
Test name
Test status
Simulation time 6066783136 ps
CPU time 8.06 seconds
Started Aug 11 06:41:14 PM PDT 24
Finished Aug 11 06:41:22 PM PDT 24
Peak memory 201504 kb
Host smart-7cd669da-8419-4bff-afca-595b20786e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295781121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2295781121
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3584488635
Short name T52
Test name
Test status
Simulation time 136869529836 ps
CPU time 154.17 seconds
Started Aug 11 06:41:19 PM PDT 24
Finished Aug 11 06:43:54 PM PDT 24
Peak memory 210136 kb
Host smart-07807db6-c99d-4fc3-8822-805d3400bb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584488635 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3584488635
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1851295599
Short name T488
Test name
Test status
Simulation time 296086541 ps
CPU time 1.34 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:41:26 PM PDT 24
Peak memory 201240 kb
Host smart-18b6d4f0-248e-48f6-9b5c-15f134e8fa7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851295599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1851295599
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4270695567
Short name T296
Test name
Test status
Simulation time 501855652167 ps
CPU time 262.16 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:45:46 PM PDT 24
Peak memory 201372 kb
Host smart-7c459710-6888-4872-b1a8-b9874003cbcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270695567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4270695567
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1854907712
Short name T362
Test name
Test status
Simulation time 183631569598 ps
CPU time 111.58 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 06:43:27 PM PDT 24
Peak memory 201440 kb
Host smart-8332f5bb-7063-4fc1-8347-933911a584fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854907712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1854907712
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3475807449
Short name T331
Test name
Test status
Simulation time 491586886057 ps
CPU time 1026.47 seconds
Started Aug 11 06:41:18 PM PDT 24
Finished Aug 11 06:58:25 PM PDT 24
Peak memory 201424 kb
Host smart-610c124d-ca66-4066-bc00-f3d0eb285e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475807449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3475807449
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2331614719
Short name T524
Test name
Test status
Simulation time 493575484775 ps
CPU time 289.07 seconds
Started Aug 11 06:41:25 PM PDT 24
Finished Aug 11 06:46:14 PM PDT 24
Peak memory 201448 kb
Host smart-6b420e3c-16bb-4470-abfd-93f71fe625a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331614719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2331614719
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3820706148
Short name T246
Test name
Test status
Simulation time 162526980365 ps
CPU time 96.61 seconds
Started Aug 11 06:41:13 PM PDT 24
Finished Aug 11 06:42:50 PM PDT 24
Peak memory 201412 kb
Host smart-9336f63d-de8a-4aa4-b16c-07fdca226cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820706148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3820706148
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.365587091
Short name T734
Test name
Test status
Simulation time 500764187327 ps
CPU time 1088.72 seconds
Started Aug 11 06:41:21 PM PDT 24
Finished Aug 11 06:59:30 PM PDT 24
Peak memory 201388 kb
Host smart-002ff6f9-9a65-4bbe-9cbf-2b5929c39d9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=365587091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.365587091
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1381210712
Short name T557
Test name
Test status
Simulation time 197040873587 ps
CPU time 233.88 seconds
Started Aug 11 06:41:26 PM PDT 24
Finished Aug 11 06:45:20 PM PDT 24
Peak memory 201460 kb
Host smart-b7127e7d-5408-46d8-8036-4c6ba8f613a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381210712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1381210712
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.879828958
Short name T217
Test name
Test status
Simulation time 613045090074 ps
CPU time 317.7 seconds
Started Aug 11 06:41:27 PM PDT 24
Finished Aug 11 06:46:44 PM PDT 24
Peak memory 201504 kb
Host smart-36d0f8dd-ebb9-4511-af42-0964b77aa8d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879828958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.879828958
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1305503243
Short name T754
Test name
Test status
Simulation time 92184137483 ps
CPU time 257.32 seconds
Started Aug 11 06:41:22 PM PDT 24
Finished Aug 11 06:45:40 PM PDT 24
Peak memory 201992 kb
Host smart-81356803-1f31-429b-9d19-abf033892aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305503243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1305503243
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.598241829
Short name T752
Test name
Test status
Simulation time 26619981692 ps
CPU time 16.97 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:41:41 PM PDT 24
Peak memory 201336 kb
Host smart-84045085-bca9-4758-8c91-cf3bfe6e9421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598241829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.598241829
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1787670605
Short name T522
Test name
Test status
Simulation time 4504538573 ps
CPU time 3.31 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:41:28 PM PDT 24
Peak memory 201376 kb
Host smart-7604cc55-19fd-4a73-99c8-0db2c0c0071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787670605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1787670605
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4192248812
Short name T702
Test name
Test status
Simulation time 6039220200 ps
CPU time 4.7 seconds
Started Aug 11 06:41:18 PM PDT 24
Finished Aug 11 06:41:22 PM PDT 24
Peak memory 201364 kb
Host smart-f4314176-e2ab-4df6-ab5c-098d02df427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192248812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4192248812
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.345701662
Short name T357
Test name
Test status
Simulation time 654735758292 ps
CPU time 360.76 seconds
Started Aug 11 06:41:21 PM PDT 24
Finished Aug 11 06:47:22 PM PDT 24
Peak memory 201436 kb
Host smart-1d8a3139-334d-4d24-b7e6-651ff9eaf537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345701662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
345701662
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.881252864
Short name T234
Test name
Test status
Simulation time 275601034909 ps
CPU time 237.37 seconds
Started Aug 11 06:41:29 PM PDT 24
Finished Aug 11 06:45:26 PM PDT 24
Peak memory 217408 kb
Host smart-82817498-1ffc-479c-af9d-0008702f9ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881252864 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.881252864
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2842195935
Short name T261
Test name
Test status
Simulation time 333819671949 ps
CPU time 190.78 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:44:51 PM PDT 24
Peak memory 201524 kb
Host smart-d4e4e0ff-be0c-49ff-90b4-8fba240d0621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842195935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2842195935
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1261970998
Short name T422
Test name
Test status
Simulation time 167057253486 ps
CPU time 102.08 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:43:06 PM PDT 24
Peak memory 201412 kb
Host smart-378c5d83-0816-4d9b-a1ce-2a900e932958
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261970998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1261970998
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1391953656
Short name T202
Test name
Test status
Simulation time 320637477357 ps
CPU time 51.75 seconds
Started Aug 11 06:41:23 PM PDT 24
Finished Aug 11 06:42:14 PM PDT 24
Peak memory 201452 kb
Host smart-e7285415-4785-44c0-aac1-41ee55599ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391953656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1391953656
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1703872304
Short name T435
Test name
Test status
Simulation time 487696143771 ps
CPU time 267.25 seconds
Started Aug 11 06:41:26 PM PDT 24
Finished Aug 11 06:45:54 PM PDT 24
Peak memory 201252 kb
Host smart-670bdabc-5849-45c7-872c-f43f3404fa34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703872304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1703872304
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.822904970
Short name T318
Test name
Test status
Simulation time 200597654593 ps
CPU time 252.9 seconds
Started Aug 11 06:41:23 PM PDT 24
Finished Aug 11 06:45:36 PM PDT 24
Peak memory 201396 kb
Host smart-5dc3634f-bb70-4612-9585-9a4ba75f6f21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822904970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.822904970
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1079863876
Short name T533
Test name
Test status
Simulation time 593565591765 ps
CPU time 313.46 seconds
Started Aug 11 06:41:30 PM PDT 24
Finished Aug 11 06:46:44 PM PDT 24
Peak memory 201444 kb
Host smart-a6157b56-167c-4a19-8452-296e30f75a92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079863876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1079863876
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2717680011
Short name T501
Test name
Test status
Simulation time 125731976033 ps
CPU time 393.94 seconds
Started Aug 11 06:41:27 PM PDT 24
Finished Aug 11 06:48:01 PM PDT 24
Peak memory 201840 kb
Host smart-f014eeb1-1bac-4c79-ade3-b89398d6bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717680011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2717680011
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.789338118
Short name T739
Test name
Test status
Simulation time 23233135080 ps
CPU time 14.18 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:41:45 PM PDT 24
Peak memory 201196 kb
Host smart-66129ab6-ba69-4f64-88f6-6e820af4bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789338118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.789338118
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3463576038
Short name T9
Test name
Test status
Simulation time 3458198654 ps
CPU time 5.16 seconds
Started Aug 11 06:41:26 PM PDT 24
Finished Aug 11 06:41:31 PM PDT 24
Peak memory 201288 kb
Host smart-0e1479d1-4173-4b4e-bc5b-0c2eccd8636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463576038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3463576038
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.528246278
Short name T481
Test name
Test status
Simulation time 5601029610 ps
CPU time 2.79 seconds
Started Aug 11 06:41:23 PM PDT 24
Finished Aug 11 06:41:26 PM PDT 24
Peak memory 201312 kb
Host smart-4dc57a91-e9b2-4604-96ed-507c10d7b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528246278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.528246278
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.841334128
Short name T597
Test name
Test status
Simulation time 322980859478 ps
CPU time 767.39 seconds
Started Aug 11 06:41:22 PM PDT 24
Finished Aug 11 06:54:09 PM PDT 24
Peak memory 201528 kb
Host smart-880ba7d9-ac20-4f46-82cb-35e1cff75493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841334128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
841334128
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.487354469
Short name T341
Test name
Test status
Simulation time 22283120272 ps
CPU time 50.04 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:42:23 PM PDT 24
Peak memory 210092 kb
Host smart-5814a845-4825-48ed-ab62-f9479e2c6d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487354469 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.487354469
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.89437041
Short name T566
Test name
Test status
Simulation time 524680149 ps
CPU time 1.24 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 06:41:36 PM PDT 24
Peak memory 201224 kb
Host smart-153a598b-ac1f-41cd-a3ba-80d719e29f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89437041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.89437041
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2777836332
Short name T177
Test name
Test status
Simulation time 159201109163 ps
CPU time 36.1 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:42:13 PM PDT 24
Peak memory 201424 kb
Host smart-f1296f52-fb98-4505-84c7-8b4f788b6107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777836332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2777836332
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1818932148
Short name T310
Test name
Test status
Simulation time 165254325182 ps
CPU time 202.88 seconds
Started Aug 11 06:41:27 PM PDT 24
Finished Aug 11 06:44:50 PM PDT 24
Peak memory 201408 kb
Host smart-033ba59b-04a0-4cb5-924e-9671d48c8fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818932148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1818932148
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.128081247
Short name T746
Test name
Test status
Simulation time 496259921894 ps
CPU time 292.58 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:46:25 PM PDT 24
Peak memory 201456 kb
Host smart-14eb427e-b4ee-411c-9c2b-f49b07c385d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128081247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.128081247
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4189517864
Short name T573
Test name
Test status
Simulation time 328862253706 ps
CPU time 271.57 seconds
Started Aug 11 06:41:26 PM PDT 24
Finished Aug 11 06:45:57 PM PDT 24
Peak memory 201528 kb
Host smart-6d468594-c2eb-4471-b932-f48171bafa29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189517864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4189517864
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3281430913
Short name T373
Test name
Test status
Simulation time 342681909507 ps
CPU time 775.87 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:54:28 PM PDT 24
Peak memory 201500 kb
Host smart-be758e29-4ead-4a3d-a3f0-7d6c8b5ed13a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281430913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3281430913
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.529778087
Short name T628
Test name
Test status
Simulation time 202232223916 ps
CPU time 468.71 seconds
Started Aug 11 06:41:30 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 201468 kb
Host smart-43618306-f43e-4b04-a880-af3647960815
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529778087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.529778087
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2575880716
Short name T432
Test name
Test status
Simulation time 135752986128 ps
CPU time 714.95 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:53:27 PM PDT 24
Peak memory 201820 kb
Host smart-f979f5ac-ffb3-4ea4-8d3f-4fb6343f98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575880716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2575880716
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2516632803
Short name T710
Test name
Test status
Simulation time 42818376069 ps
CPU time 88.34 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:43:12 PM PDT 24
Peak memory 201376 kb
Host smart-ee769745-2c01-4bac-b54e-0a48023bfbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516632803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2516632803
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1577568211
Short name T790
Test name
Test status
Simulation time 2770626079 ps
CPU time 6.76 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 201336 kb
Host smart-17b90fc6-620a-4817-b318-493949b933cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577568211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1577568211
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1887187891
Short name T551
Test name
Test status
Simulation time 5774747953 ps
CPU time 4.04 seconds
Started Aug 11 06:41:24 PM PDT 24
Finished Aug 11 06:41:28 PM PDT 24
Peak memory 201192 kb
Host smart-b6737f4a-c36d-4555-a303-471b55378ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887187891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1887187891
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2896664416
Short name T725
Test name
Test status
Simulation time 330807938940 ps
CPU time 96.26 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:43:08 PM PDT 24
Peak memory 201360 kb
Host smart-c3b1e80a-2c9a-4e24-af41-0fd1397f183c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896664416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2896664416
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2995346371
Short name T39
Test name
Test status
Simulation time 145471871316 ps
CPU time 305.22 seconds
Started Aug 11 06:41:29 PM PDT 24
Finished Aug 11 06:46:35 PM PDT 24
Peak memory 209880 kb
Host smart-e639324f-2b17-4c1f-a875-d065eb2e28be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995346371 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2995346371
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1148325055
Short name T526
Test name
Test status
Simulation time 440290540 ps
CPU time 0.78 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:41:32 PM PDT 24
Peak memory 201252 kb
Host smart-eef2b589-7e03-4e95-a1b2-cb294a834c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148325055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1148325055
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.788231778
Short name T152
Test name
Test status
Simulation time 182179097751 ps
CPU time 442.04 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:49:05 PM PDT 24
Peak memory 201288 kb
Host smart-4b5af314-4594-4219-a03c-dbe288c5eb26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788231778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.788231778
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3044843597
Short name T46
Test name
Test status
Simulation time 163923966173 ps
CPU time 299.35 seconds
Started Aug 11 06:41:25 PM PDT 24
Finished Aug 11 06:46:24 PM PDT 24
Peak memory 201492 kb
Host smart-5fc9a05a-66bb-4f90-8bbd-7df2d46214e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044843597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3044843597
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.751764710
Short name T365
Test name
Test status
Simulation time 488110934583 ps
CPU time 1145.19 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 07:00:39 PM PDT 24
Peak memory 201448 kb
Host smart-57290f6f-fca5-4f08-8478-987c363eddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751764710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.751764710
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2114748880
Short name T433
Test name
Test status
Simulation time 327447532733 ps
CPU time 191.74 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:44:52 PM PDT 24
Peak memory 201516 kb
Host smart-50bbbdfc-c36d-4eaf-9c1e-772256a44a60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114748880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2114748880
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3067236979
Short name T179
Test name
Test status
Simulation time 170045242500 ps
CPU time 194.59 seconds
Started Aug 11 06:41:30 PM PDT 24
Finished Aug 11 06:44:45 PM PDT 24
Peak memory 201440 kb
Host smart-320f6efc-ed83-4daa-b3c3-7bd46e9418c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067236979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3067236979
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3927567337
Short name T563
Test name
Test status
Simulation time 166904742776 ps
CPU time 32.16 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 06:42:07 PM PDT 24
Peak memory 201440 kb
Host smart-0f9a0b14-adc7-4dc7-95db-2fec66892609
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927567337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3927567337
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2695621193
Short name T352
Test name
Test status
Simulation time 571487741395 ps
CPU time 843.55 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:55:38 PM PDT 24
Peak memory 201492 kb
Host smart-cb5be27e-7765-4c85-8f7b-d26648c222bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695621193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2695621193
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2964450111
Short name T104
Test name
Test status
Simulation time 606642832342 ps
CPU time 1237.1 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 201472 kb
Host smart-1d6d1b70-f6ef-4dbd-907f-417a16b6b767
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964450111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2964450111
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1501638514
Short name T211
Test name
Test status
Simulation time 101519904574 ps
CPU time 347.31 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:47:20 PM PDT 24
Peak memory 201832 kb
Host smart-cc0d0c2c-d2a1-4b27-add9-4fdf8192cf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501638514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1501638514
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1764222931
Short name T719
Test name
Test status
Simulation time 27372401627 ps
CPU time 6.06 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:41:39 PM PDT 24
Peak memory 201320 kb
Host smart-c7f0a8da-98f5-4ad3-a4d0-5ef8b3383978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764222931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1764222931
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3574227902
Short name T506
Test name
Test status
Simulation time 4986880151 ps
CPU time 3.28 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:41:46 PM PDT 24
Peak memory 201316 kb
Host smart-654445ae-2657-4fdc-b4bb-022d08daed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574227902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3574227902
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.929841344
Short name T585
Test name
Test status
Simulation time 5804280086 ps
CPU time 10.27 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:41:45 PM PDT 24
Peak memory 201376 kb
Host smart-a44054b1-3a4e-4d20-a3db-0811e0da2c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929841344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.929841344
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1407980901
Short name T370
Test name
Test status
Simulation time 163336561376 ps
CPU time 342.28 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:47:18 PM PDT 24
Peak memory 201444 kb
Host smart-6fadf1c2-4ce2-42dd-8f3b-2bfe9f52edfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407980901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1407980901
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3791790637
Short name T571
Test name
Test status
Simulation time 182557523592 ps
CPU time 283.28 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:46:15 PM PDT 24
Peak memory 218264 kb
Host smart-9f7857f0-300e-4c03-88b7-510770e8d4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791790637 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3791790637
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1827085143
Short name T461
Test name
Test status
Simulation time 486009019 ps
CPU time 1.77 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:43 PM PDT 24
Peak memory 201228 kb
Host smart-c1cfd77b-f200-4f51-84c8-389a1500f521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827085143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1827085143
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3086141594
Short name T609
Test name
Test status
Simulation time 172865421477 ps
CPU time 379.2 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:47:56 PM PDT 24
Peak memory 201484 kb
Host smart-d34cd61b-11c8-4d61-94fd-896c7a410315
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086141594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3086141594
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4083977900
Short name T504
Test name
Test status
Simulation time 159362909442 ps
CPU time 115.35 seconds
Started Aug 11 06:41:30 PM PDT 24
Finished Aug 11 06:43:26 PM PDT 24
Peak memory 201552 kb
Host smart-267cde1d-ea08-4e57-a674-96b8f859e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083977900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4083977900
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.35115069
Short name T749
Test name
Test status
Simulation time 165309844689 ps
CPU time 98.05 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:43:10 PM PDT 24
Peak memory 201504 kb
Host smart-bcfefd7a-deb5-4a43-87c1-3d6bbb8ca889
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt
_fixed.35115069
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1230031888
Short name T170
Test name
Test status
Simulation time 163641575413 ps
CPU time 197.34 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:44:49 PM PDT 24
Peak memory 201512 kb
Host smart-57656238-623b-4826-821d-f80e9766fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230031888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1230031888
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2265615425
Short name T697
Test name
Test status
Simulation time 164627978527 ps
CPU time 102.35 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:43:14 PM PDT 24
Peak memory 201424 kb
Host smart-c3d30825-8900-4f9d-b0d1-78588ae8902b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265615425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2265615425
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1041363404
Short name T655
Test name
Test status
Simulation time 198504037954 ps
CPU time 163.7 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:44:21 PM PDT 24
Peak memory 201464 kb
Host smart-4029a57f-7816-4f64-875c-abc90d6517d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041363404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1041363404
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3102850678
Short name T500
Test name
Test status
Simulation time 70487251566 ps
CPU time 285.16 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:46:25 PM PDT 24
Peak memory 202052 kb
Host smart-05fe7c40-82d4-4950-b2fc-6d6113317471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102850678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3102850678
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.427769272
Short name T678
Test name
Test status
Simulation time 42691757333 ps
CPU time 24.86 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:42:09 PM PDT 24
Peak memory 201340 kb
Host smart-72ea3e50-b1c0-419f-939b-117bace0b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427769272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.427769272
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2235544953
Short name T510
Test name
Test status
Simulation time 2743796789 ps
CPU time 2.14 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 201324 kb
Host smart-84e86448-7607-4b34-91e6-1c50b70812e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235544953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2235544953
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1422981359
Short name T707
Test name
Test status
Simulation time 5975296028 ps
CPU time 7.37 seconds
Started Aug 11 06:41:26 PM PDT 24
Finished Aug 11 06:41:34 PM PDT 24
Peak memory 201396 kb
Host smart-bd119214-d955-4b4b-a685-8a610ade3506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422981359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1422981359
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2404419698
Short name T47
Test name
Test status
Simulation time 389995585294 ps
CPU time 1316.46 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 07:03:35 PM PDT 24
Peak memory 210052 kb
Host smart-addb0a18-59aa-45dd-9d7a-79f5d1792456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404419698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2404419698
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.737444309
Short name T103
Test name
Test status
Simulation time 431363393233 ps
CPU time 374.58 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:47:53 PM PDT 24
Peak memory 210144 kb
Host smart-b574cbff-0a37-41b1-8fd4-0842dbe7bab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737444309 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.737444309
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.150400984
Short name T476
Test name
Test status
Simulation time 328848682 ps
CPU time 1.34 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:41:44 PM PDT 24
Peak memory 201264 kb
Host smart-19b16c3f-43d1-4977-8350-e4ae342bc0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150400984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.150400984
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1723427835
Short name T49
Test name
Test status
Simulation time 166476255837 ps
CPU time 396.22 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:48:20 PM PDT 24
Peak memory 201440 kb
Host smart-985ccdb1-192a-4337-a546-4b2cf06541fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723427835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1723427835
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2609021421
Short name T148
Test name
Test status
Simulation time 492203696293 ps
CPU time 843.69 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:55:46 PM PDT 24
Peak memory 201424 kb
Host smart-5fb8ba85-f4c1-4333-8f1d-116b63f2f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609021421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2609021421
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3094142993
Short name T397
Test name
Test status
Simulation time 490620785356 ps
CPU time 572.88 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 201388 kb
Host smart-9298970e-d090-49f6-a93e-9cae6433f843
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094142993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3094142993
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3864727301
Short name T448
Test name
Test status
Simulation time 161664898918 ps
CPU time 90.69 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 06:43:06 PM PDT 24
Peak memory 201388 kb
Host smart-6d9530b9-ca2c-4c97-a2d0-dd7ff342bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864727301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3864727301
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2549686130
Short name T536
Test name
Test status
Simulation time 159836324498 ps
CPU time 327.02 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:47:04 PM PDT 24
Peak memory 201472 kb
Host smart-78713f2e-3e10-40b5-b39d-badc061e45fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549686130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2549686130
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3189457668
Short name T284
Test name
Test status
Simulation time 389617690855 ps
CPU time 801.13 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:54:59 PM PDT 24
Peak memory 201440 kb
Host smart-11765ef0-d259-4337-9a84-04751d30257f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189457668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3189457668
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3920220162
Short name T428
Test name
Test status
Simulation time 397553052410 ps
CPU time 478.87 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:49:39 PM PDT 24
Peak memory 201444 kb
Host smart-7fcadd01-5f17-40d4-ab12-e8a77e68ef01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920220162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3920220162
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1280630051
Short name T519
Test name
Test status
Simulation time 31622460722 ps
CPU time 15.57 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:41:50 PM PDT 24
Peak memory 201340 kb
Host smart-86040a00-a8a1-4497-ac46-4313414fe10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280630051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1280630051
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3592431585
Short name T141
Test name
Test status
Simulation time 3923321368 ps
CPU time 2.97 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:41:42 PM PDT 24
Peak memory 201340 kb
Host smart-38e53832-b320-46f4-9d64-afd1f401eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592431585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3592431585
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3250552068
Short name T499
Test name
Test status
Simulation time 6021200149 ps
CPU time 8.56 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:41:46 PM PDT 24
Peak memory 201316 kb
Host smart-43b33da0-7ff8-4385-b57a-2797433f6201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250552068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3250552068
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.689524892
Short name T290
Test name
Test status
Simulation time 182904739675 ps
CPU time 226.85 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:45:31 PM PDT 24
Peak memory 201480 kb
Host smart-1d8dd506-5f19-4d02-b8b1-ea7fac84612c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689524892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
689524892
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.621484067
Short name T24
Test name
Test status
Simulation time 212714733884 ps
CPU time 34.93 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:42:12 PM PDT 24
Peak memory 209876 kb
Host smart-fd738c8d-6dac-4b65-a39a-9bff508b55ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621484067 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.621484067
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3415178943
Short name T713
Test name
Test status
Simulation time 362778658 ps
CPU time 1.4 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:40:52 PM PDT 24
Peak memory 201152 kb
Host smart-395b79a3-253a-47e1-89ae-8a793c05d8e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415178943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3415178943
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2189528780
Short name T316
Test name
Test status
Simulation time 325522769584 ps
CPU time 179.87 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:44:00 PM PDT 24
Peak memory 201456 kb
Host smart-2ef46a43-f9ad-4194-bd48-44fb4aefa9d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189528780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2189528780
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3969691426
Short name T303
Test name
Test status
Simulation time 533699011816 ps
CPU time 613.23 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 201452 kb
Host smart-dc8cbd87-a091-47b9-9c63-f6869e280354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969691426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3969691426
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4132032596
Short name T726
Test name
Test status
Simulation time 165009714601 ps
CPU time 96.29 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:42:25 PM PDT 24
Peak memory 201476 kb
Host smart-9637fe2d-ed41-4e84-9d9d-0f9aa14c861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132032596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4132032596
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2960499905
Short name T698
Test name
Test status
Simulation time 329865577737 ps
CPU time 204.45 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:44:16 PM PDT 24
Peak memory 201432 kb
Host smart-a6bc51be-920b-47de-86a3-6c4c78cdd056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960499905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2960499905
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.730887218
Short name T191
Test name
Test status
Simulation time 494465830241 ps
CPU time 301.79 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:45:51 PM PDT 24
Peak memory 201416 kb
Host smart-0e8d4444-7f3b-439a-b7bb-b950eee8e04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730887218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.730887218
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2850643688
Short name T531
Test name
Test status
Simulation time 162571934623 ps
CPU time 91.18 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:42:16 PM PDT 24
Peak memory 201484 kb
Host smart-75212581-92c1-465c-9719-42a2f744e5da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850643688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2850643688
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.535795499
Short name T654
Test name
Test status
Simulation time 350392500859 ps
CPU time 215.34 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:44:26 PM PDT 24
Peak memory 201380 kb
Host smart-f9b8dc8f-d23e-44af-8b01-38892e4e7729
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535795499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.535795499
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2891075982
Short name T423
Test name
Test status
Simulation time 405068042968 ps
CPU time 178.54 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:43:51 PM PDT 24
Peak memory 201488 kb
Host smart-679aeddf-ecc0-46eb-bc19-79368ddfd272
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891075982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2891075982
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3658502843
Short name T472
Test name
Test status
Simulation time 102597820239 ps
CPU time 378.84 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 201876 kb
Host smart-30af3490-44a8-4067-ae78-b63b5d10a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658502843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3658502843
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.963388484
Short name T775
Test name
Test status
Simulation time 27271004919 ps
CPU time 18.04 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:41:11 PM PDT 24
Peak memory 201500 kb
Host smart-4172538a-293f-4a16-9714-10a15564d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963388484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.963388484
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2742851510
Short name T778
Test name
Test status
Simulation time 4039498859 ps
CPU time 1.47 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:40:50 PM PDT 24
Peak memory 201324 kb
Host smart-3421033c-c909-4661-9cff-d2f316a5cf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742851510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2742851510
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.532715210
Short name T75
Test name
Test status
Simulation time 7868877977 ps
CPU time 3.24 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:40:57 PM PDT 24
Peak memory 217096 kb
Host smart-7e601e37-e50e-457e-a19e-aa1481450dd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532715210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.532715210
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1213761596
Short name T426
Test name
Test status
Simulation time 5855380394 ps
CPU time 15.25 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:41:04 PM PDT 24
Peak memory 201332 kb
Host smart-8ca4663c-fd0d-4898-903f-cf74133497db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213761596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1213761596
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1061846698
Short name T384
Test name
Test status
Simulation time 334201790123 ps
CPU time 1134.11 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:59:53 PM PDT 24
Peak memory 212064 kb
Host smart-a627b90d-4c1b-4ae5-99e5-48b952aa9d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061846698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1061846698
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1546083392
Short name T770
Test name
Test status
Simulation time 296097010915 ps
CPU time 223.82 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:44:42 PM PDT 24
Peak memory 210356 kb
Host smart-7b175f1f-0596-4221-9c9a-8932f01de887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546083392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1546083392
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.172291787
Short name T400
Test name
Test status
Simulation time 509353872 ps
CPU time 0.89 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:41:44 PM PDT 24
Peak memory 201256 kb
Host smart-2b9afc72-4349-4023-a0d1-954389190c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172291787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.172291787
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3735192954
Short name T168
Test name
Test status
Simulation time 162850885948 ps
CPU time 62.01 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:42:44 PM PDT 24
Peak memory 201428 kb
Host smart-33b0e841-cf7c-418b-8dac-daa30127965c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735192954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3735192954
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2535529960
Short name T600
Test name
Test status
Simulation time 359197471433 ps
CPU time 74.79 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:42:54 PM PDT 24
Peak memory 201620 kb
Host smart-8f85eb16-0113-48ff-a076-16447ccb6951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535529960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2535529960
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.468371299
Short name T484
Test name
Test status
Simulation time 164843904551 ps
CPU time 201.14 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:45:03 PM PDT 24
Peak memory 201428 kb
Host smart-8e1e0604-8842-41dc-a871-7a674d6703f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=468371299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.468371299
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2779382631
Short name T265
Test name
Test status
Simulation time 166601625835 ps
CPU time 387.66 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 201404 kb
Host smart-e389186d-6cf0-4498-b7e3-26cf09fe04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779382631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2779382631
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2511729063
Short name T741
Test name
Test status
Simulation time 494730075456 ps
CPU time 288.9 seconds
Started Aug 11 06:41:35 PM PDT 24
Finished Aug 11 06:46:24 PM PDT 24
Peak memory 201408 kb
Host smart-bf9bb35b-56aa-439c-9620-7b0c378f9801
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511729063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2511729063
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3824664598
Short name T607
Test name
Test status
Simulation time 419395143225 ps
CPU time 500.86 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 201428 kb
Host smart-f4efd91b-2701-421e-a045-c3af20fa7244
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824664598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3824664598
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1385360586
Short name T630
Test name
Test status
Simulation time 36204302389 ps
CPU time 26.71 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:42:02 PM PDT 24
Peak memory 201388 kb
Host smart-3141bd09-b5f0-437b-ae20-d1d0a58f3a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385360586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1385360586
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1660479328
Short name T111
Test name
Test status
Simulation time 4643477446 ps
CPU time 5.78 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 201312 kb
Host smart-d0b048be-f325-41ea-a01d-a78f105e2937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660479328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1660479328
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4085109610
Short name T668
Test name
Test status
Simulation time 6065852523 ps
CPU time 5.67 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 201380 kb
Host smart-affc11b3-a903-40c8-b3da-4e08a200653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085109610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4085109610
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2760085056
Short name T255
Test name
Test status
Simulation time 399753278256 ps
CPU time 1150.5 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 07:00:52 PM PDT 24
Peak memory 210044 kb
Host smart-c7aff029-892b-495d-83f3-968aee042ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760085056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2760085056
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.277985657
Short name T473
Test name
Test status
Simulation time 236341658271 ps
CPU time 112.39 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:35 PM PDT 24
Peak memory 209788 kb
Host smart-c5de59d4-0a4f-4448-90a4-a6554f528ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277985657 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.277985657
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1841662523
Short name T634
Test name
Test status
Simulation time 382689496 ps
CPU time 1.49 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:41:42 PM PDT 24
Peak memory 201256 kb
Host smart-0a55f3b4-9e25-4c2e-ab79-3fdcdf214116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841662523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1841662523
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.530889180
Short name T218
Test name
Test status
Simulation time 165560966789 ps
CPU time 82.47 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:43:00 PM PDT 24
Peak memory 201552 kb
Host smart-3d86d04c-82a8-4667-9145-51cbdb0204ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530889180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.530889180
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1505010825
Short name T358
Test name
Test status
Simulation time 160826654414 ps
CPU time 349.08 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:47:26 PM PDT 24
Peak memory 201404 kb
Host smart-72a832aa-4414-41ae-aec4-2393354a91de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505010825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1505010825
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4125793762
Short name T530
Test name
Test status
Simulation time 166932338806 ps
CPU time 38.51 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:42:19 PM PDT 24
Peak memory 201420 kb
Host smart-048aaf72-c255-4fc8-a7bd-e1e25d828e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125793762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4125793762
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.524655563
Short name T388
Test name
Test status
Simulation time 325686469247 ps
CPU time 385.84 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 201452 kb
Host smart-cdb3461e-2fc9-4e81-bda4-32236d5f17fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=524655563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.524655563
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.36679915
Short name T516
Test name
Test status
Simulation time 161024924231 ps
CPU time 86.7 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:09 PM PDT 24
Peak memory 201388 kb
Host smart-c0531134-cf6f-4cba-8141-2e05732a5f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36679915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.36679915
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2514060567
Short name T166
Test name
Test status
Simulation time 167634636657 ps
CPU time 384.67 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 201436 kb
Host smart-619db6c3-bf7c-417d-a88d-6c8e2aa3cc42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514060567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2514060567
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3715155134
Short name T342
Test name
Test status
Simulation time 199274252231 ps
CPU time 117.26 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:43:33 PM PDT 24
Peak memory 201396 kb
Host smart-d9565a3d-769e-4644-88b0-d19aed4cd2c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715155134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3715155134
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3611951642
Short name T561
Test name
Test status
Simulation time 197029213245 ps
CPU time 434.19 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:48:47 PM PDT 24
Peak memory 201512 kb
Host smart-e34de1c5-23a5-40ab-9881-1645aba0449c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611951642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3611951642
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4098232178
Short name T33
Test name
Test status
Simulation time 88709524546 ps
CPU time 280.29 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:46:25 PM PDT 24
Peak memory 201824 kb
Host smart-15aa7ffe-8fb2-4faa-a3cb-e03da13e6673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098232178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4098232178
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2673016116
Short name T756
Test name
Test status
Simulation time 29482846328 ps
CPU time 19.81 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 06:41:53 PM PDT 24
Peak memory 201340 kb
Host smart-3bb6d6c7-aaa5-4b09-8695-fa81103eedda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673016116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2673016116
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1748523220
Short name T649
Test name
Test status
Simulation time 3521190054 ps
CPU time 4.79 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:41:45 PM PDT 24
Peak memory 201296 kb
Host smart-57d1a54c-6145-44fb-aa2e-44b577734e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748523220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1748523220
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.852341133
Short name T718
Test name
Test status
Simulation time 5776014535 ps
CPU time 4.12 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:45 PM PDT 24
Peak memory 201376 kb
Host smart-558c99a7-49a3-4020-b072-434d869e9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852341133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.852341133
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.17446599
Short name T714
Test name
Test status
Simulation time 552255931 ps
CPU time 0.92 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:41:40 PM PDT 24
Peak memory 201264 kb
Host smart-07b7c05e-65d5-4604-9b8a-9a68f8b1864f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17446599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.17446599
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2515304316
Short name T271
Test name
Test status
Simulation time 533405024767 ps
CPU time 473.8 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:49:31 PM PDT 24
Peak memory 201496 kb
Host smart-b79b9df0-0f92-4749-9495-42a13b5de8d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515304316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2515304316
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2133034893
Short name T747
Test name
Test status
Simulation time 510811291368 ps
CPU time 596.17 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:51:28 PM PDT 24
Peak memory 201476 kb
Host smart-336d23d4-64e5-406f-8d11-4212825a372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133034893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2133034893
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.511711538
Short name T110
Test name
Test status
Simulation time 324527830636 ps
CPU time 733.99 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:53:55 PM PDT 24
Peak memory 201484 kb
Host smart-0e876e7c-6239-4042-bcfa-cbe921afa1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511711538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.511711538
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2773908550
Short name T1
Test name
Test status
Simulation time 158679113602 ps
CPU time 384.74 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:47:57 PM PDT 24
Peak memory 201436 kb
Host smart-533f4686-19f9-42dd-a292-2abad8bef0b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773908550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2773908550
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1640588597
Short name T207
Test name
Test status
Simulation time 499812459723 ps
CPU time 287.38 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:46:27 PM PDT 24
Peak memory 201464 kb
Host smart-37e41ad5-6707-4672-9216-16433956d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640588597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1640588597
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.4279897085
Short name T198
Test name
Test status
Simulation time 159484800794 ps
CPU time 93.78 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:43:15 PM PDT 24
Peak memory 201432 kb
Host smart-53f84623-029c-411e-8d2d-ef3d24af5467
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279897085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.4279897085
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1178693369
Short name T483
Test name
Test status
Simulation time 390487180002 ps
CPU time 229.17 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:45:30 PM PDT 24
Peak memory 201488 kb
Host smart-03f74c43-f9b5-41f6-9e96-feff29a3ef77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178693369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1178693369
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.491992976
Short name T640
Test name
Test status
Simulation time 35516965189 ps
CPU time 38.14 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:42:18 PM PDT 24
Peak memory 201360 kb
Host smart-ae7f6cbe-ccea-4ab8-a065-66eab99d572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491992976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.491992976
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2270286924
Short name T711
Test name
Test status
Simulation time 3814273326 ps
CPU time 5.22 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:41:36 PM PDT 24
Peak memory 201340 kb
Host smart-87bf53bd-1487-4a48-817e-4359dd6f7806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270286924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2270286924
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2176622695
Short name T90
Test name
Test status
Simulation time 5777308794 ps
CPU time 7.68 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:41:50 PM PDT 24
Peak memory 201372 kb
Host smart-05e5dc23-0c23-48ba-80ad-1aa3c612858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176622695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2176622695
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.744665479
Short name T523
Test name
Test status
Simulation time 5444251367 ps
CPU time 14.03 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:41:50 PM PDT 24
Peak memory 201288 kb
Host smart-804b8dd3-1677-41c5-9a3d-da19e4778b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744665479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
744665479
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1759321140
Short name T709
Test name
Test status
Simulation time 451360884 ps
CPU time 1.62 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:43 PM PDT 24
Peak memory 201244 kb
Host smart-1c6bfc00-c374-4006-9a18-614d8ff0af32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759321140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1759321140
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1055311881
Short name T157
Test name
Test status
Simulation time 331081515160 ps
CPU time 199.7 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:44:59 PM PDT 24
Peak memory 201400 kb
Host smart-0c060171-b0db-45e6-ac8f-b23d25f24be3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055311881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1055311881
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1314930018
Short name T306
Test name
Test status
Simulation time 159319607728 ps
CPU time 97.43 seconds
Started Aug 11 06:41:46 PM PDT 24
Finished Aug 11 06:43:24 PM PDT 24
Peak memory 201408 kb
Host smart-44a55e58-3f0a-48d5-9d0b-a0ff33358cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314930018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1314930018
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1912051665
Short name T497
Test name
Test status
Simulation time 158897343102 ps
CPU time 279.9 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:46:18 PM PDT 24
Peak memory 201468 kb
Host smart-4628790c-f472-4d22-b4f2-7a76aae4c792
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912051665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1912051665
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.793539361
Short name T122
Test name
Test status
Simulation time 338318695764 ps
CPU time 199.64 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:44:58 PM PDT 24
Peak memory 201360 kb
Host smart-7903cc5b-e9ef-4246-922a-f68cedc817ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793539361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.793539361
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2018912986
Short name T547
Test name
Test status
Simulation time 490487955271 ps
CPU time 602.51 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:51:42 PM PDT 24
Peak memory 201444 kb
Host smart-a4b00412-3509-41d0-941e-bda841812720
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018912986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2018912986
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.876561348
Short name T185
Test name
Test status
Simulation time 382630506101 ps
CPU time 234.27 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:45:36 PM PDT 24
Peak memory 201452 kb
Host smart-83115954-0e6a-477e-98d0-39b4aded2714
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876561348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.876561348
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1601622290
Short name T773
Test name
Test status
Simulation time 593782752448 ps
CPU time 1355.56 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 07:04:15 PM PDT 24
Peak memory 201404 kb
Host smart-73e39ee0-369e-421f-ad77-bcb166a6835e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601622290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1601622290
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.547573283
Short name T420
Test name
Test status
Simulation time 129364521929 ps
CPU time 473.66 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 201800 kb
Host smart-3365c060-801f-4c73-b288-88c45642bb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547573283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.547573283
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3649117831
Short name T496
Test name
Test status
Simulation time 26447586200 ps
CPU time 64.08 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:42:44 PM PDT 24
Peak memory 201320 kb
Host smart-02c4171f-0998-4081-8551-1491016d7353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649117831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3649117831
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3464300002
Short name T431
Test name
Test status
Simulation time 5154809535 ps
CPU time 2.72 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:44 PM PDT 24
Peak memory 201324 kb
Host smart-a606f4e6-4265-46b8-9086-75aa674c843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464300002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3464300002
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4050083851
Short name T467
Test name
Test status
Simulation time 5914028867 ps
CPU time 6.37 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:41:50 PM PDT 24
Peak memory 201320 kb
Host smart-cf7fb028-e62c-4684-bed1-c0a31e9653c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050083851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4050083851
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1180313343
Short name T684
Test name
Test status
Simulation time 328307013526 ps
CPU time 716.72 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:53:38 PM PDT 24
Peak memory 201412 kb
Host smart-619bd370-9635-4e04-b782-a72ca38b35c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180313343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1180313343
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2061709198
Short name T38
Test name
Test status
Simulation time 41653054078 ps
CPU time 88.82 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:11 PM PDT 24
Peak memory 209752 kb
Host smart-bf917042-e382-45c6-8191-a80c243222c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061709198 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2061709198
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4144567415
Short name T599
Test name
Test status
Simulation time 447067770 ps
CPU time 1.61 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:41:39 PM PDT 24
Peak memory 201216 kb
Host smart-98cfa0a3-e700-45d9-8a59-543c3e9be5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144567415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4144567415
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3519265705
Short name T776
Test name
Test status
Simulation time 179702371617 ps
CPU time 79.93 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:42:59 PM PDT 24
Peak memory 201512 kb
Host smart-9cbaedd9-9934-4645-a6c7-39d8abf76205
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519265705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3519265705
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2980377036
Short name T491
Test name
Test status
Simulation time 156223968611 ps
CPU time 357.31 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 201404 kb
Host smart-40c4e3a2-a79a-4c09-84b4-5c3eb34f54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980377036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2980377036
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1945102530
Short name T164
Test name
Test status
Simulation time 169167024992 ps
CPU time 71.27 seconds
Started Aug 11 06:41:31 PM PDT 24
Finished Aug 11 06:42:43 PM PDT 24
Peak memory 201456 kb
Host smart-63216adf-a952-4004-bf07-f077b2dff5c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945102530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1945102530
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1873991772
Short name T7
Test name
Test status
Simulation time 162032215569 ps
CPU time 68.94 seconds
Started Aug 11 06:41:34 PM PDT 24
Finished Aug 11 06:42:43 PM PDT 24
Peak memory 201440 kb
Host smart-900a8e47-cccb-4da4-ab8e-d71b0fb5896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873991772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1873991772
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1956028723
Short name T696
Test name
Test status
Simulation time 329970862082 ps
CPU time 391.08 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:48:09 PM PDT 24
Peak memory 201460 kb
Host smart-853d9889-b285-41ac-8f33-8d468ea96913
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956028723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1956028723
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4038870623
Short name T392
Test name
Test status
Simulation time 393105163228 ps
CPU time 954.96 seconds
Started Aug 11 06:41:32 PM PDT 24
Finished Aug 11 06:57:27 PM PDT 24
Peak memory 201448 kb
Host smart-580eb925-eca8-451a-a368-298dad1e2565
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038870623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4038870623
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3018023483
Short name T187
Test name
Test status
Simulation time 88999337370 ps
CPU time 328.95 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:47:06 PM PDT 24
Peak memory 201860 kb
Host smart-8098eb0b-a8c6-4110-bac2-eb55bcb8eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018023483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3018023483
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4199064535
Short name T98
Test name
Test status
Simulation time 32845005274 ps
CPU time 78.82 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:42:57 PM PDT 24
Peak memory 201288 kb
Host smart-f74e309e-7c05-44b7-b08d-2032df57315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199064535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4199064535
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1667259030
Short name T503
Test name
Test status
Simulation time 4075340960 ps
CPU time 5.04 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:41:46 PM PDT 24
Peak memory 201348 kb
Host smart-30d51e6d-3b0c-4802-ab12-6c85db20f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667259030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1667259030
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3186401419
Short name T106
Test name
Test status
Simulation time 6073000126 ps
CPU time 7.69 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:48 PM PDT 24
Peak memory 201328 kb
Host smart-033175bf-7253-43bb-9f65-66d190c43c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186401419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3186401419
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4038590048
Short name T59
Test name
Test status
Simulation time 505927564533 ps
CPU time 1561.33 seconds
Started Aug 11 06:41:33 PM PDT 24
Finished Aug 11 07:07:35 PM PDT 24
Peak memory 201788 kb
Host smart-ac51907b-3877-47c2-bc0e-745cb2cca7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038590048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4038590048
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2049683876
Short name T289
Test name
Test status
Simulation time 207384306237 ps
CPU time 332.43 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 210128 kb
Host smart-62e3b023-64b3-416b-b719-9fa39c12d505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049683876 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2049683876
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2057848776
Short name T610
Test name
Test status
Simulation time 339808303 ps
CPU time 0.78 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:41:43 PM PDT 24
Peak memory 201200 kb
Host smart-7109d48a-2cac-4c8f-8ba9-46e4386d0484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057848776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2057848776
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.441999312
Short name T120
Test name
Test status
Simulation time 367847617244 ps
CPU time 451.92 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 201424 kb
Host smart-e5986e0a-8821-43b2-9729-9d48de528ef3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441999312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.441999312
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4098688166
Short name T788
Test name
Test status
Simulation time 163820292109 ps
CPU time 375.12 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:47:56 PM PDT 24
Peak memory 201484 kb
Host smart-b49c9a7e-d642-4e9b-8479-9b3d35bb4951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098688166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4098688166
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1965941842
Short name T223
Test name
Test status
Simulation time 168185882044 ps
CPU time 117.35 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:43:42 PM PDT 24
Peak memory 201524 kb
Host smart-c847a9e7-0356-4d08-b356-d40d8a56e9ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965941842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1965941842
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.9479193
Short name T322
Test name
Test status
Simulation time 332818637128 ps
CPU time 384.73 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 201472 kb
Host smart-91fc81b1-57f7-464d-aead-8717336421e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9479193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.9479193
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2082091500
Short name T545
Test name
Test status
Simulation time 488320594914 ps
CPU time 372.26 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:47:54 PM PDT 24
Peak memory 201420 kb
Host smart-9464aa3c-78ef-41eb-8576-a7d6e5057806
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082091500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2082091500
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3015809233
Short name T31
Test name
Test status
Simulation time 392233243321 ps
CPU time 944.7 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:57:21 PM PDT 24
Peak memory 201468 kb
Host smart-bcbc422d-7dc9-489e-b17c-831e82e3ff87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015809233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3015809233
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3691206256
Short name T227
Test name
Test status
Simulation time 93329706569 ps
CPU time 432.9 seconds
Started Aug 11 06:41:39 PM PDT 24
Finished Aug 11 06:48:52 PM PDT 24
Peak memory 201836 kb
Host smart-68ea6497-91cb-40ca-8d32-a02beb428bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691206256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3691206256
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1732276608
Short name T174
Test name
Test status
Simulation time 36794280112 ps
CPU time 86.09 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:43:08 PM PDT 24
Peak memory 201304 kb
Host smart-2ab85e5f-6534-4ddc-b2cc-21650125b201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732276608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1732276608
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2008060683
Short name T529
Test name
Test status
Simulation time 4078819308 ps
CPU time 9.78 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:41:53 PM PDT 24
Peak memory 201296 kb
Host smart-a19abba8-79f1-43e3-a84a-4eb48e875afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008060683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2008060683
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3297458134
Short name T615
Test name
Test status
Simulation time 5968820963 ps
CPU time 4.45 seconds
Started Aug 11 06:41:37 PM PDT 24
Finished Aug 11 06:41:42 PM PDT 24
Peak memory 201312 kb
Host smart-75cafdc1-13d3-4bb1-82b3-dd0793e5830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297458134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3297458134
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.153192785
Short name T23
Test name
Test status
Simulation time 12812292893 ps
CPU time 50.81 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:42:33 PM PDT 24
Peak memory 201820 kb
Host smart-134bed83-0c58-4647-b394-9e3465035f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153192785 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.153192785
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4061900008
Short name T627
Test name
Test status
Simulation time 439466750 ps
CPU time 1.02 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:42 PM PDT 24
Peak memory 201148 kb
Host smart-7de9a859-7aba-47f0-8a21-b400b8a2cf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061900008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4061900008
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.175855517
Short name T101
Test name
Test status
Simulation time 170345817675 ps
CPU time 67.18 seconds
Started Aug 11 06:41:38 PM PDT 24
Finished Aug 11 06:42:45 PM PDT 24
Peak memory 201516 kb
Host smart-30ed7c69-3d33-417e-988b-89ec620d206b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175855517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.175855517
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3601905090
Short name T184
Test name
Test status
Simulation time 504411814521 ps
CPU time 324.58 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 201448 kb
Host smart-d97f8b3b-4210-4190-a5e3-534e21e48079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601905090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3601905090
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2679113811
Short name T602
Test name
Test status
Simulation time 156840739878 ps
CPU time 169.84 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:44:32 PM PDT 24
Peak memory 201420 kb
Host smart-4f66f896-d1a0-450a-bd64-a3a129606118
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679113811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2679113811
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.888864223
Short name T143
Test name
Test status
Simulation time 325164292045 ps
CPU time 128.31 seconds
Started Aug 11 06:41:36 PM PDT 24
Finished Aug 11 06:43:44 PM PDT 24
Peak memory 201516 kb
Host smart-7305efce-240a-48cc-8f6f-cb3122ac709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888864223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.888864223
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3421692402
Short name T777
Test name
Test status
Simulation time 322319814110 ps
CPU time 158.67 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:44:20 PM PDT 24
Peak memory 201416 kb
Host smart-ad9b219e-7685-4895-9ef7-2f87b7030801
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421692402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3421692402
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3661339208
Short name T205
Test name
Test status
Simulation time 642249630062 ps
CPU time 393.29 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:48:17 PM PDT 24
Peak memory 201460 kb
Host smart-59da4b41-2935-4e40-939c-aec3af02f6a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661339208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3661339208
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.100621235
Short name T724
Test name
Test status
Simulation time 193398505334 ps
CPU time 158.12 seconds
Started Aug 11 06:41:43 PM PDT 24
Finished Aug 11 06:44:21 PM PDT 24
Peak memory 201440 kb
Host smart-de6ab0ee-f43d-4d3f-886e-587550d7afe6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100621235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.100621235
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3911945074
Short name T606
Test name
Test status
Simulation time 122920030131 ps
CPU time 647.57 seconds
Started Aug 11 06:41:45 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 201820 kb
Host smart-bc17591c-ae6c-468b-8b93-a49d22ddfac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911945074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3911945074
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2234170490
Short name T505
Test name
Test status
Simulation time 42003155694 ps
CPU time 49.9 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:42:30 PM PDT 24
Peak memory 201272 kb
Host smart-74094731-e907-4d41-bf9a-561fd0356927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234170490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2234170490
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1448606443
Short name T639
Test name
Test status
Simulation time 3224874722 ps
CPU time 8.84 seconds
Started Aug 11 06:41:49 PM PDT 24
Finished Aug 11 06:41:58 PM PDT 24
Peak memory 201304 kb
Host smart-4495deb9-6c02-48dd-9c18-0d274b755a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448606443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1448606443
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3851218857
Short name T631
Test name
Test status
Simulation time 5913621205 ps
CPU time 4.63 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:41:45 PM PDT 24
Peak memory 201376 kb
Host smart-9f3063b6-14b6-481d-8825-cfc42984ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851218857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3851218857
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2773762357
Short name T25
Test name
Test status
Simulation time 119329304054 ps
CPU time 276.62 seconds
Started Aug 11 06:41:41 PM PDT 24
Finished Aug 11 06:46:18 PM PDT 24
Peak memory 201808 kb
Host smart-5f526d20-bc53-4166-8e4d-7085f2d675a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773762357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2773762357
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3623821659
Short name T679
Test name
Test status
Simulation time 360771869 ps
CPU time 1.01 seconds
Started Aug 11 06:41:53 PM PDT 24
Finished Aug 11 06:41:54 PM PDT 24
Peak memory 201236 kb
Host smart-8d136902-5d16-4789-9175-3e1726797e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623821659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3623821659
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3211603574
Short name T275
Test name
Test status
Simulation time 164414493074 ps
CPU time 395.79 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:48:20 PM PDT 24
Peak memory 201464 kb
Host smart-fe1d9ba0-932e-4002-9052-9f3736f50c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211603574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3211603574
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.335178563
Short name T349
Test name
Test status
Simulation time 158679447897 ps
CPU time 92.46 seconds
Started Aug 11 06:41:45 PM PDT 24
Finished Aug 11 06:43:18 PM PDT 24
Peak memory 201396 kb
Host smart-be2c4701-55d2-4fd0-a844-f8ae3aad8561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335178563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.335178563
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2598896754
Short name T414
Test name
Test status
Simulation time 166012112280 ps
CPU time 27.34 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:42:12 PM PDT 24
Peak memory 201496 kb
Host smart-9000972b-dba1-4006-96c2-fb13d1054bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598896754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2598896754
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3858753322
Short name T330
Test name
Test status
Simulation time 338592260428 ps
CPU time 186.38 seconds
Started Aug 11 06:41:42 PM PDT 24
Finished Aug 11 06:44:49 PM PDT 24
Peak memory 201360 kb
Host smart-5354bd59-7080-41bb-b056-6616ae4b282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858753322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3858753322
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3593451512
Short name T558
Test name
Test status
Simulation time 478381553733 ps
CPU time 287.93 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:46:32 PM PDT 24
Peak memory 201392 kb
Host smart-c5e7932d-355a-406e-add9-e4ff22e9bceb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593451512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3593451512
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3310564765
Short name T263
Test name
Test status
Simulation time 183339870914 ps
CPU time 405.59 seconds
Started Aug 11 06:41:46 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 201416 kb
Host smart-92167c11-99c2-4f1a-a3e8-daf82380e283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310564765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3310564765
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4292544786
Short name T208
Test name
Test status
Simulation time 386607103960 ps
CPU time 870.12 seconds
Started Aug 11 06:41:45 PM PDT 24
Finished Aug 11 06:56:16 PM PDT 24
Peak memory 201448 kb
Host smart-1b8511c7-286c-42a7-a4eb-55db48f000fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292544786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4292544786
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1749026156
Short name T765
Test name
Test status
Simulation time 85494772297 ps
CPU time 428.76 seconds
Started Aug 11 06:41:46 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 201816 kb
Host smart-a7af2d74-1f7a-4211-9fc1-39a25c8de3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749026156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1749026156
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.61707355
Short name T662
Test name
Test status
Simulation time 36559961735 ps
CPU time 44.46 seconds
Started Aug 11 06:41:44 PM PDT 24
Finished Aug 11 06:42:28 PM PDT 24
Peak memory 201356 kb
Host smart-3887f2d4-a0f8-4ca5-84ac-bf843b6f84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61707355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.61707355
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2679227436
Short name T460
Test name
Test status
Simulation time 5113646202 ps
CPU time 3.42 seconds
Started Aug 11 06:41:45 PM PDT 24
Finished Aug 11 06:41:48 PM PDT 24
Peak memory 201312 kb
Host smart-c43902fe-27ee-414f-9617-6f39e6592e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679227436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2679227436
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.83241407
Short name T525
Test name
Test status
Simulation time 5899041839 ps
CPU time 7.47 seconds
Started Aug 11 06:41:40 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 201348 kb
Host smart-c9a6d0e8-64cd-4dd5-8932-997abe968ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83241407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.83241407
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.867419739
Short name T693
Test name
Test status
Simulation time 67520780805 ps
CPU time 163.65 seconds
Started Aug 11 06:41:45 PM PDT 24
Finished Aug 11 06:44:29 PM PDT 24
Peak memory 210188 kb
Host smart-c233249e-ed72-4334-9b8f-95baec2d60ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867419739 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.867419739
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1101125810
Short name T623
Test name
Test status
Simulation time 418514974 ps
CPU time 0.86 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 06:42:03 PM PDT 24
Peak memory 201268 kb
Host smart-40604160-3b21-4965-a5a2-ed3d5aa580f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101125810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1101125810
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3352764381
Short name T114
Test name
Test status
Simulation time 164775769293 ps
CPU time 11.75 seconds
Started Aug 11 06:42:01 PM PDT 24
Finished Aug 11 06:42:12 PM PDT 24
Peak memory 201452 kb
Host smart-2df36463-bad5-4301-8c18-1b1a6dc5729c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352764381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3352764381
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3392529704
Short name T219
Test name
Test status
Simulation time 540005378839 ps
CPU time 1189.26 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 07:01:51 PM PDT 24
Peak memory 201404 kb
Host smart-bedebcd7-4b70-484f-9d28-e903c4702569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392529704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3392529704
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2555235922
Short name T247
Test name
Test status
Simulation time 326157146897 ps
CPU time 801.8 seconds
Started Aug 11 06:41:54 PM PDT 24
Finished Aug 11 06:55:16 PM PDT 24
Peak memory 201424 kb
Host smart-06848173-1f1f-44bc-a8bb-e4f4728ad4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555235922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2555235922
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1127552204
Short name T458
Test name
Test status
Simulation time 158828868031 ps
CPU time 110.79 seconds
Started Aug 11 06:42:08 PM PDT 24
Finished Aug 11 06:43:59 PM PDT 24
Peak memory 201484 kb
Host smart-f292519a-2c46-4b0a-a64f-abad882a0039
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127552204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1127552204
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2839195616
Short name T659
Test name
Test status
Simulation time 494223708627 ps
CPU time 230.43 seconds
Started Aug 11 06:41:53 PM PDT 24
Finished Aug 11 06:45:44 PM PDT 24
Peak memory 201404 kb
Host smart-4efa51a4-5a74-4cea-9a05-97b04a15dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839195616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2839195616
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1949408493
Short name T792
Test name
Test status
Simulation time 165515379629 ps
CPU time 376.61 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 06:48:19 PM PDT 24
Peak memory 201464 kb
Host smart-d748b383-6c1b-44cc-96d1-4f2dfc6953b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949408493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1949408493
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3598463902
Short name T344
Test name
Test status
Simulation time 175686400396 ps
CPU time 99.82 seconds
Started Aug 11 06:42:01 PM PDT 24
Finished Aug 11 06:43:41 PM PDT 24
Peak memory 201404 kb
Host smart-1f4e1b59-6761-4b2c-bb8d-77cf1f1ce111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598463902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3598463902
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2377397696
Short name T478
Test name
Test status
Simulation time 388801654891 ps
CPU time 910.54 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 06:57:13 PM PDT 24
Peak memory 201444 kb
Host smart-37455d16-9f8a-44c6-9a41-bcc9c91ebb16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377397696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2377397696
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3504439410
Short name T378
Test name
Test status
Simulation time 108940503015 ps
CPU time 402.6 seconds
Started Aug 11 06:42:03 PM PDT 24
Finished Aug 11 06:48:46 PM PDT 24
Peak memory 202048 kb
Host smart-a98e5862-09f9-4888-b76b-a9801773ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504439410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3504439410
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1437502583
Short name T469
Test name
Test status
Simulation time 40764721346 ps
CPU time 23.5 seconds
Started Aug 11 06:42:01 PM PDT 24
Finished Aug 11 06:42:24 PM PDT 24
Peak memory 201320 kb
Host smart-ee07262a-c6a6-4ed9-bb78-82bcf2d1dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437502583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1437502583
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2122846776
Short name T518
Test name
Test status
Simulation time 3279802531 ps
CPU time 2.49 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 06:42:05 PM PDT 24
Peak memory 201324 kb
Host smart-8a3a5842-b375-413e-ab1f-3e9983c9e50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122846776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2122846776
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2638829229
Short name T450
Test name
Test status
Simulation time 5807585063 ps
CPU time 2.9 seconds
Started Aug 11 06:41:51 PM PDT 24
Finished Aug 11 06:41:54 PM PDT 24
Peak memory 201288 kb
Host smart-20442610-ad78-43cd-837d-d28c73128d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638829229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2638829229
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.847663474
Short name T154
Test name
Test status
Simulation time 431978759715 ps
CPU time 521.68 seconds
Started Aug 11 06:42:01 PM PDT 24
Finished Aug 11 06:50:43 PM PDT 24
Peak memory 201416 kb
Host smart-c2236992-36dc-4049-9fa0-1d8f20ef203e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847663474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
847663474
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3315644147
Short name T641
Test name
Test status
Simulation time 378162376 ps
CPU time 1.49 seconds
Started Aug 11 06:42:17 PM PDT 24
Finished Aug 11 06:42:18 PM PDT 24
Peak memory 201236 kb
Host smart-ede003f4-00f8-4f65-9ed7-bc6aa3c230ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315644147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3315644147
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3385209411
Short name T209
Test name
Test status
Simulation time 322716368519 ps
CPU time 717.72 seconds
Started Aug 11 06:42:08 PM PDT 24
Finished Aug 11 06:54:06 PM PDT 24
Peak memory 201464 kb
Host smart-3ee1c82c-0166-4ce7-a47e-12381f482838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385209411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3385209411
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3902755673
Short name T603
Test name
Test status
Simulation time 489943488032 ps
CPU time 1150.16 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 07:01:12 PM PDT 24
Peak memory 201456 kb
Host smart-ba7618ff-50b5-4a7b-99f4-8ba64a07330b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902755673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3902755673
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2070950318
Short name T456
Test name
Test status
Simulation time 328129635777 ps
CPU time 158.22 seconds
Started Aug 11 06:42:08 PM PDT 24
Finished Aug 11 06:44:47 PM PDT 24
Peak memory 201452 kb
Host smart-84a6510c-589f-466f-9220-450b921a8bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070950318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2070950318
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2174373668
Short name T772
Test name
Test status
Simulation time 167620954544 ps
CPU time 377.12 seconds
Started Aug 11 06:42:04 PM PDT 24
Finished Aug 11 06:48:21 PM PDT 24
Peak memory 201432 kb
Host smart-e7d8d510-8e19-443b-afbf-da26bc0c27f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174373668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2174373668
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1495326249
Short name T738
Test name
Test status
Simulation time 595349828139 ps
CPU time 1287.76 seconds
Started Aug 11 06:42:09 PM PDT 24
Finished Aug 11 07:03:37 PM PDT 24
Peak memory 201340 kb
Host smart-d1858f60-7e9b-4cc2-9f6f-23578fdc0d00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495326249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1495326249
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3318626030
Short name T559
Test name
Test status
Simulation time 136876650795 ps
CPU time 643.13 seconds
Started Aug 11 06:42:10 PM PDT 24
Finished Aug 11 06:52:53 PM PDT 24
Peak memory 201812 kb
Host smart-e863d987-b5ff-438e-8e05-ac656b608b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318626030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3318626030
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.115617198
Short name T592
Test name
Test status
Simulation time 30756996231 ps
CPU time 66.2 seconds
Started Aug 11 06:42:07 PM PDT 24
Finished Aug 11 06:43:13 PM PDT 24
Peak memory 201288 kb
Host smart-8ba10916-0403-4742-81ca-e6b5e2ac55fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115617198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.115617198
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3797351426
Short name T680
Test name
Test status
Simulation time 2925318356 ps
CPU time 4.66 seconds
Started Aug 11 06:42:11 PM PDT 24
Finished Aug 11 06:42:16 PM PDT 24
Peak memory 201344 kb
Host smart-aafd283b-4a1a-456f-b112-df81a1ceadac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797351426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3797351426
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.225311638
Short name T555
Test name
Test status
Simulation time 6023816784 ps
CPU time 6.26 seconds
Started Aug 11 06:42:02 PM PDT 24
Finished Aug 11 06:42:08 PM PDT 24
Peak memory 201364 kb
Host smart-e7346ee4-186d-4886-b09f-ef3bfc75ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225311638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.225311638
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2746382755
Short name T21
Test name
Test status
Simulation time 120253795291 ps
CPU time 284.1 seconds
Started Aug 11 06:42:11 PM PDT 24
Finished Aug 11 06:46:55 PM PDT 24
Peak memory 211152 kb
Host smart-7088f0ca-1000-4c28-a70a-8fcd4159c8dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746382755 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2746382755
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1112035351
Short name T512
Test name
Test status
Simulation time 419095991 ps
CPU time 1.15 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:40:50 PM PDT 24
Peak memory 201232 kb
Host smart-25794b5f-8e84-4234-8e15-2113e3da0ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112035351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1112035351
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.708558925
Short name T354
Test name
Test status
Simulation time 347160809980 ps
CPU time 281.82 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:45:30 PM PDT 24
Peak memory 201468 kb
Host smart-ac1269a1-35ff-4c5d-a27c-d779f1355a25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708558925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.708558925
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.63994506
Short name T750
Test name
Test status
Simulation time 331411766946 ps
CPU time 189.53 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:44:07 PM PDT 24
Peak memory 201428 kb
Host smart-97c49a61-0e1f-4d44-a75d-e7ac3a5121cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63994506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.63994506
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.50130198
Short name T181
Test name
Test status
Simulation time 479693838166 ps
CPU time 1118.27 seconds
Started Aug 11 06:40:46 PM PDT 24
Finished Aug 11 06:59:24 PM PDT 24
Peak memory 201428 kb
Host smart-b1c78420-10f9-4f8d-8aca-96261e54e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50130198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.50130198
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2123818364
Short name T780
Test name
Test status
Simulation time 331488279290 ps
CPU time 722.15 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:52:54 PM PDT 24
Peak memory 201440 kb
Host smart-5f2ab958-3e7d-467c-bd52-de58052b74ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123818364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2123818364
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.355006218
Short name T736
Test name
Test status
Simulation time 165041924701 ps
CPU time 382.07 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:47:12 PM PDT 24
Peak memory 201404 kb
Host smart-4ce4ee7d-cae5-4bba-b467-f61521306c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355006218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.355006218
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2075630212
Short name T591
Test name
Test status
Simulation time 498565882800 ps
CPU time 1107.57 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:59:25 PM PDT 24
Peak memory 201172 kb
Host smart-8cb10846-d470-42b4-abd6-1e9ae28ab735
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075630212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2075630212
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3672174591
Short name T315
Test name
Test status
Simulation time 175350562092 ps
CPU time 24.74 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:41:17 PM PDT 24
Peak memory 201448 kb
Host smart-a2ab5f68-4226-4a9d-974e-85c722b9785b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672174591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3672174591
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3281971932
Short name T479
Test name
Test status
Simulation time 386906171369 ps
CPU time 909.97 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:56:01 PM PDT 24
Peak memory 201440 kb
Host smart-bd629c6c-8f63-4307-8db1-882c95841c36
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281971932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3281971932
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1793230835
Short name T383
Test name
Test status
Simulation time 103448907678 ps
CPU time 359.09 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:46:51 PM PDT 24
Peak memory 201788 kb
Host smart-b1d4df65-2db6-4ee7-b991-d767dc34d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793230835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1793230835
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3254856444
Short name T123
Test name
Test status
Simulation time 34828327885 ps
CPU time 13.66 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:41:02 PM PDT 24
Peak memory 201360 kb
Host smart-a8369167-2e78-444f-94ee-5ee471efb6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254856444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3254856444
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.724717794
Short name T675
Test name
Test status
Simulation time 3172965561 ps
CPU time 2.44 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:40:55 PM PDT 24
Peak memory 201368 kb
Host smart-f1119cdc-d2e6-4f25-bd27-7d3050819c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724717794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.724717794
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1572142607
Short name T88
Test name
Test status
Simulation time 4137974330 ps
CPU time 2.01 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:40:54 PM PDT 24
Peak memory 217144 kb
Host smart-6e09f588-c004-4b17-bafb-32bbfb9ad12d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572142607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1572142607
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1709466323
Short name T97
Test name
Test status
Simulation time 5707003991 ps
CPU time 4.23 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:40:55 PM PDT 24
Peak memory 201360 kb
Host smart-26d25da6-6a81-4710-b3b8-0b05c5ed852e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709466323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1709466323
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1320372544
Short name T118
Test name
Test status
Simulation time 337407771794 ps
CPU time 187.59 seconds
Started Aug 11 06:40:46 PM PDT 24
Finished Aug 11 06:43:53 PM PDT 24
Peak memory 201428 kb
Host smart-f675eb0f-2c6c-4626-82b8-42fcce853c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320372544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1320372544
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.605720546
Short name T552
Test name
Test status
Simulation time 528719140 ps
CPU time 1.78 seconds
Started Aug 11 06:42:11 PM PDT 24
Finished Aug 11 06:42:13 PM PDT 24
Peak memory 201192 kb
Host smart-4060a81a-c58e-4a8e-914e-851bcf173247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605720546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.605720546
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4173444859
Short name T462
Test name
Test status
Simulation time 177935899730 ps
CPU time 200.89 seconds
Started Aug 11 06:42:13 PM PDT 24
Finished Aug 11 06:45:34 PM PDT 24
Peak memory 201488 kb
Host smart-dd03d018-453e-48c3-aa5a-c79da3c810c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173444859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4173444859
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1497203435
Short name T212
Test name
Test status
Simulation time 324435989297 ps
CPU time 192.82 seconds
Started Aug 11 06:42:13 PM PDT 24
Finished Aug 11 06:45:26 PM PDT 24
Peak memory 201488 kb
Host smart-7c8fada4-1d4b-4d4f-873e-dbca0f0f2034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497203435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1497203435
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1180349366
Short name T449
Test name
Test status
Simulation time 323428510852 ps
CPU time 710.07 seconds
Started Aug 11 06:42:14 PM PDT 24
Finished Aug 11 06:54:04 PM PDT 24
Peak memory 201484 kb
Host smart-0578a097-4e7b-4060-bc03-bd379f9bc623
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180349366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1180349366
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2692417506
Short name T587
Test name
Test status
Simulation time 591145444865 ps
CPU time 352.76 seconds
Started Aug 11 06:42:12 PM PDT 24
Finished Aug 11 06:48:04 PM PDT 24
Peak memory 201396 kb
Host smart-484f80c7-a5f4-4f07-baba-d2db06a399da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692417506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2692417506
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1452885490
Short name T57
Test name
Test status
Simulation time 131300037530 ps
CPU time 652.35 seconds
Started Aug 11 06:42:14 PM PDT 24
Finished Aug 11 06:53:07 PM PDT 24
Peak memory 201684 kb
Host smart-46864688-90a8-464f-b53d-d21da44a34e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452885490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1452885490
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3842556767
Short name T91
Test name
Test status
Simulation time 29045717136 ps
CPU time 58.44 seconds
Started Aug 11 06:42:18 PM PDT 24
Finished Aug 11 06:43:16 PM PDT 24
Peak memory 201324 kb
Host smart-dc68252a-511f-475f-b00b-eddeccc11612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842556767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3842556767
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.830452471
Short name T681
Test name
Test status
Simulation time 4165560070 ps
CPU time 9.44 seconds
Started Aug 11 06:42:14 PM PDT 24
Finished Aug 11 06:42:23 PM PDT 24
Peak memory 201372 kb
Host smart-b019f9f1-c4ef-4938-94f5-053143a980d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830452471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.830452471
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4130661625
Short name T534
Test name
Test status
Simulation time 5666523147 ps
CPU time 13.41 seconds
Started Aug 11 06:42:11 PM PDT 24
Finished Aug 11 06:42:25 PM PDT 24
Peak memory 201380 kb
Host smart-cca84813-7d48-49ce-be0f-0b125148fee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130661625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4130661625
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3712495228
Short name T446
Test name
Test status
Simulation time 112202396870 ps
CPU time 265.76 seconds
Started Aug 11 06:42:12 PM PDT 24
Finished Aug 11 06:46:38 PM PDT 24
Peak memory 201824 kb
Host smart-ad15362b-bda2-4a02-9631-f858c735586b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712495228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3712495228
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3816646881
Short name T521
Test name
Test status
Simulation time 296113672 ps
CPU time 1.18 seconds
Started Aug 11 06:42:23 PM PDT 24
Finished Aug 11 06:42:24 PM PDT 24
Peak memory 201092 kb
Host smart-01b2b1d6-c1c2-446a-930b-a86772f2757f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816646881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3816646881
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1471214727
Short name T716
Test name
Test status
Simulation time 340044130353 ps
CPU time 347.96 seconds
Started Aug 11 06:42:18 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 201408 kb
Host smart-813fb9c8-c9ff-494a-8bda-200037989971
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471214727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1471214727
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.176697121
Short name T762
Test name
Test status
Simulation time 355186342939 ps
CPU time 139.43 seconds
Started Aug 11 06:42:16 PM PDT 24
Finished Aug 11 06:44:36 PM PDT 24
Peak memory 201380 kb
Host smart-4b2ade6f-ec9d-4d4b-9a9c-bd24f71b2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176697121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.176697121
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.200467683
Short name T312
Test name
Test status
Simulation time 329050661957 ps
CPU time 775.11 seconds
Started Aug 11 06:42:19 PM PDT 24
Finished Aug 11 06:55:14 PM PDT 24
Peak memory 201448 kb
Host smart-9d64e6ce-9065-4c87-ba97-1afc483f0036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200467683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.200467683
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1611369378
Short name T406
Test name
Test status
Simulation time 160608137652 ps
CPU time 203.14 seconds
Started Aug 11 06:42:24 PM PDT 24
Finished Aug 11 06:45:47 PM PDT 24
Peak memory 201504 kb
Host smart-2e7837c8-8b0a-4438-8e09-fddc9a9a7a5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611369378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1611369378
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3305294139
Short name T416
Test name
Test status
Simulation time 165944619182 ps
CPU time 371.54 seconds
Started Aug 11 06:42:17 PM PDT 24
Finished Aug 11 06:48:28 PM PDT 24
Peak memory 201460 kb
Host smart-15d1a754-6d8a-4a01-a8f9-70036e7bd433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305294139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3305294139
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2136658421
Short name T648
Test name
Test status
Simulation time 327197845580 ps
CPU time 198.14 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:45:39 PM PDT 24
Peak memory 201460 kb
Host smart-b9b25237-b450-4e01-9d3f-eff8bc6a43a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136658421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2136658421
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2136160912
Short name T222
Test name
Test status
Simulation time 540933611244 ps
CPU time 295.4 seconds
Started Aug 11 06:42:16 PM PDT 24
Finished Aug 11 06:47:12 PM PDT 24
Peak memory 201424 kb
Host smart-bb41e205-ca4d-402d-85db-c6a2316b0c3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136160912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2136160912
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1797944845
Short name T643
Test name
Test status
Simulation time 210287387369 ps
CPU time 65.51 seconds
Started Aug 11 06:42:24 PM PDT 24
Finished Aug 11 06:43:30 PM PDT 24
Peak memory 201496 kb
Host smart-3392a593-4d82-4883-b1a6-c5c2b68d4d24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797944845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1797944845
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.923920646
Short name T210
Test name
Test status
Simulation time 92283668100 ps
CPU time 315.05 seconds
Started Aug 11 06:42:24 PM PDT 24
Finished Aug 11 06:47:40 PM PDT 24
Peak memory 201844 kb
Host smart-1cd1a9d2-1cce-42b5-8c4a-a1f76b929e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923920646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.923920646
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3832570274
Short name T786
Test name
Test status
Simulation time 27093612845 ps
CPU time 30 seconds
Started Aug 11 06:42:16 PM PDT 24
Finished Aug 11 06:42:46 PM PDT 24
Peak memory 201372 kb
Host smart-55265d00-3592-43dd-9693-9a8e43e8dbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832570274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3832570274
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1743712816
Short name T733
Test name
Test status
Simulation time 3543745435 ps
CPU time 2.62 seconds
Started Aug 11 06:42:17 PM PDT 24
Finished Aug 11 06:42:20 PM PDT 24
Peak memory 201316 kb
Host smart-a6a35965-61c3-4268-8739-04d5ea71f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743712816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1743712816
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1926695968
Short name T594
Test name
Test status
Simulation time 5807715499 ps
CPU time 6.79 seconds
Started Aug 11 06:42:24 PM PDT 24
Finished Aug 11 06:42:32 PM PDT 24
Peak memory 201376 kb
Host smart-b61ef6c3-edf9-42aa-9dbf-1539008c87c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926695968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1926695968
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1198793623
Short name T589
Test name
Test status
Simulation time 48466344332 ps
CPU time 59.33 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:43:20 PM PDT 24
Peak memory 201628 kb
Host smart-2494cc53-6f5f-4bdd-a889-b9845bcfe69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198793623 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1198793623
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1813539168
Short name T493
Test name
Test status
Simulation time 459668654 ps
CPU time 1.07 seconds
Started Aug 11 06:42:22 PM PDT 24
Finished Aug 11 06:42:23 PM PDT 24
Peak memory 201248 kb
Host smart-d30e749b-d83f-4aca-a9f7-0f70a760a304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813539168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1813539168
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1851525360
Short name T175
Test name
Test status
Simulation time 338143067373 ps
CPU time 649.59 seconds
Started Aug 11 06:42:23 PM PDT 24
Finished Aug 11 06:53:13 PM PDT 24
Peak memory 201464 kb
Host smart-90c43e4b-876d-439b-81de-c3c4a8c56600
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851525360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1851525360
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4108386688
Short name T325
Test name
Test status
Simulation time 163833783105 ps
CPU time 205.02 seconds
Started Aug 11 06:42:22 PM PDT 24
Finished Aug 11 06:45:47 PM PDT 24
Peak memory 201468 kb
Host smart-595d7325-8c10-406d-9790-e6257f8d56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108386688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4108386688
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1525963925
Short name T748
Test name
Test status
Simulation time 324569407911 ps
CPU time 144.19 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:44:45 PM PDT 24
Peak memory 201412 kb
Host smart-ea7c9cea-ded8-4e36-8103-ba0d56066f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525963925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1525963925
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2130612299
Short name T409
Test name
Test status
Simulation time 481980997695 ps
CPU time 889.23 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:57:11 PM PDT 24
Peak memory 201464 kb
Host smart-baf2ad4a-78e2-4740-8da8-e9350985b015
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130612299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2130612299
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3872884920
Short name T360
Test name
Test status
Simulation time 159221077245 ps
CPU time 382.61 seconds
Started Aug 11 06:42:24 PM PDT 24
Finished Aug 11 06:48:47 PM PDT 24
Peak memory 201428 kb
Host smart-438d961e-ad49-46db-a1cb-ea0ca35010ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872884920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3872884920
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1845506454
Short name T410
Test name
Test status
Simulation time 161677217904 ps
CPU time 310.86 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:47:32 PM PDT 24
Peak memory 201436 kb
Host smart-207ab220-c06a-48f8-b6fb-340efdede4e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845506454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1845506454
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1027613310
Short name T511
Test name
Test status
Simulation time 189232171924 ps
CPU time 237.61 seconds
Started Aug 11 06:42:22 PM PDT 24
Finished Aug 11 06:46:20 PM PDT 24
Peak memory 201472 kb
Host smart-49f4833b-8a41-4a31-8f6d-6564dd28eef8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027613310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1027613310
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2276673182
Short name T666
Test name
Test status
Simulation time 113067646325 ps
CPU time 640.36 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:53:02 PM PDT 24
Peak memory 201732 kb
Host smart-980853dd-b2d0-417a-8822-c076e4c688f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276673182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2276673182
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3911466564
Short name T744
Test name
Test status
Simulation time 45338623050 ps
CPU time 53.36 seconds
Started Aug 11 06:42:23 PM PDT 24
Finished Aug 11 06:43:16 PM PDT 24
Peak memory 201336 kb
Host smart-d7d556ba-111e-4129-8db2-e10c85c4f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911466564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3911466564
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1433390625
Short name T731
Test name
Test status
Simulation time 3336622456 ps
CPU time 2.14 seconds
Started Aug 11 06:42:20 PM PDT 24
Finished Aug 11 06:42:22 PM PDT 24
Peak memory 201284 kb
Host smart-d053fb03-21a1-4a30-b670-8c6452ad329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433390625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1433390625
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3869364599
Short name T87
Test name
Test status
Simulation time 5895639965 ps
CPU time 3.88 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:42:24 PM PDT 24
Peak memory 201304 kb
Host smart-3b09617f-f159-448c-a537-29b97bbc4bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869364599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3869364599
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3737572734
Short name T720
Test name
Test status
Simulation time 118415614437 ps
CPU time 43.61 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:43:05 PM PDT 24
Peak memory 209772 kb
Host smart-96c695c3-aabe-4deb-a1da-cd9b4abbd139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737572734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3737572734
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2150753502
Short name T584
Test name
Test status
Simulation time 489606398 ps
CPU time 1.69 seconds
Started Aug 11 06:42:32 PM PDT 24
Finished Aug 11 06:42:33 PM PDT 24
Peak memory 201236 kb
Host smart-523bc3b5-fcb5-488b-8d75-ffb323623be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150753502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2150753502
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.578599207
Short name T611
Test name
Test status
Simulation time 501460262462 ps
CPU time 328.22 seconds
Started Aug 11 06:42:25 PM PDT 24
Finished Aug 11 06:47:53 PM PDT 24
Peak memory 201428 kb
Host smart-e35c66ea-7da9-4933-9007-8b8acbd16533
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578599207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.578599207
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1314740480
Short name T274
Test name
Test status
Simulation time 355123248095 ps
CPU time 370.66 seconds
Started Aug 11 06:42:26 PM PDT 24
Finished Aug 11 06:48:37 PM PDT 24
Peak memory 201408 kb
Host smart-85da1887-4e6f-4aa8-9bcd-1ebb88adacf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314740480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1314740480
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2351841631
Short name T144
Test name
Test status
Simulation time 323598540020 ps
CPU time 343.43 seconds
Started Aug 11 06:42:27 PM PDT 24
Finished Aug 11 06:48:11 PM PDT 24
Peak memory 201464 kb
Host smart-f84a22c6-e0a9-4821-94dd-278fa4f1d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351841631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2351841631
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.434535941
Short name T766
Test name
Test status
Simulation time 331090922986 ps
CPU time 488.25 seconds
Started Aug 11 06:42:26 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 201444 kb
Host smart-ee1c8f05-997a-4634-938a-c77603202632
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=434535941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.434535941
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1476427723
Short name T706
Test name
Test status
Simulation time 500492298803 ps
CPU time 576.1 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:51:58 PM PDT 24
Peak memory 201444 kb
Host smart-cb3738e6-b5e5-4390-bb3c-b9779f0db05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476427723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1476427723
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2944488178
Short name T637
Test name
Test status
Simulation time 165673086763 ps
CPU time 386.68 seconds
Started Aug 11 06:42:23 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 201448 kb
Host smart-dc13dcf3-3e72-4a6b-968d-ed1a3cbc6436
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944488178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2944488178
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2985068237
Short name T633
Test name
Test status
Simulation time 530004157741 ps
CPU time 601.95 seconds
Started Aug 11 06:42:26 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 201384 kb
Host smart-efbb489c-8ee4-4aca-919f-950dd3ad9dae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985068237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2985068237
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.449681849
Short name T542
Test name
Test status
Simulation time 604500582066 ps
CPU time 434.3 seconds
Started Aug 11 06:42:27 PM PDT 24
Finished Aug 11 06:49:42 PM PDT 24
Peak memory 201528 kb
Host smart-38e77ce6-279f-4200-a187-71e5415de45b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449681849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.449681849
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2058196326
Short name T647
Test name
Test status
Simulation time 144490213904 ps
CPU time 738.94 seconds
Started Aug 11 06:42:28 PM PDT 24
Finished Aug 11 06:54:47 PM PDT 24
Peak memory 201812 kb
Host smart-730f9b79-40a3-4d63-a249-8890dfba496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058196326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2058196326
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2567601641
Short name T700
Test name
Test status
Simulation time 36330554518 ps
CPU time 47.38 seconds
Started Aug 11 06:42:28 PM PDT 24
Finished Aug 11 06:43:15 PM PDT 24
Peak memory 201316 kb
Host smart-fbcbc7db-4fbd-4af9-b373-86f2142aff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567601641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2567601641
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4203197850
Short name T783
Test name
Test status
Simulation time 3811717073 ps
CPU time 8.84 seconds
Started Aug 11 06:42:26 PM PDT 24
Finished Aug 11 06:42:35 PM PDT 24
Peak memory 201340 kb
Host smart-90e97a2c-8132-49cb-bdab-dc36663d5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203197850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4203197850
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3430082283
Short name T417
Test name
Test status
Simulation time 5558504969 ps
CPU time 3.09 seconds
Started Aug 11 06:42:21 PM PDT 24
Finished Aug 11 06:42:24 PM PDT 24
Peak memory 201376 kb
Host smart-8081bed2-150e-46fa-b4d0-847136d6f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430082283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3430082283
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3633452013
Short name T371
Test name
Test status
Simulation time 384046110797 ps
CPU time 398.05 seconds
Started Aug 11 06:42:31 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 201496 kb
Host smart-f0401f13-68fa-4eca-9713-21d7bc6d03b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633452013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3633452013
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3114240891
Short name T562
Test name
Test status
Simulation time 18459931579 ps
CPU time 22.96 seconds
Started Aug 11 06:42:31 PM PDT 24
Finished Aug 11 06:42:54 PM PDT 24
Peak memory 209812 kb
Host smart-d4a393ad-d96f-402c-8815-4a30af83f150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114240891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3114240891
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3931449763
Short name T638
Test name
Test status
Simulation time 534785497 ps
CPU time 0.93 seconds
Started Aug 11 06:42:43 PM PDT 24
Finished Aug 11 06:42:45 PM PDT 24
Peak memory 201224 kb
Host smart-46eb9ff6-cb46-4a15-91a2-ed8a0ea4381a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931449763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3931449763
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.722548842
Short name T361
Test name
Test status
Simulation time 509883005404 ps
CPU time 1186.73 seconds
Started Aug 11 06:42:39 PM PDT 24
Finished Aug 11 07:02:26 PM PDT 24
Peak memory 201504 kb
Host smart-12877a03-be56-41fd-8fae-d73f4469e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722548842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.722548842
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2031808922
Short name T286
Test name
Test status
Simulation time 326504033303 ps
CPU time 792.61 seconds
Started Aug 11 06:42:37 PM PDT 24
Finished Aug 11 06:55:50 PM PDT 24
Peak memory 201472 kb
Host smart-434b8c6a-86c0-47d0-bdf7-27c84e7bcf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031808922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2031808922
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3943535549
Short name T487
Test name
Test status
Simulation time 163948559288 ps
CPU time 350.43 seconds
Started Aug 11 06:42:36 PM PDT 24
Finished Aug 11 06:48:27 PM PDT 24
Peak memory 201496 kb
Host smart-b19da44e-d16c-4182-9774-88c258171e23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943535549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3943535549
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1849600869
Short name T626
Test name
Test status
Simulation time 336269366328 ps
CPU time 392.56 seconds
Started Aug 11 06:42:31 PM PDT 24
Finished Aug 11 06:49:04 PM PDT 24
Peak memory 201388 kb
Host smart-a4093f9c-c4da-43b9-99d4-ec97c38f9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849600869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1849600869
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1274291193
Short name T593
Test name
Test status
Simulation time 491263717994 ps
CPU time 868.28 seconds
Started Aug 11 06:42:34 PM PDT 24
Finished Aug 11 06:57:03 PM PDT 24
Peak memory 201408 kb
Host smart-3d188d70-d7e0-41ac-836a-257c158e262d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274291193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1274291193
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.4140555997
Short name T351
Test name
Test status
Simulation time 211426841083 ps
CPU time 486.48 seconds
Started Aug 11 06:42:37 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 201388 kb
Host smart-87367c0b-af4d-4b1e-b4e4-ebaf4cc86053
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140555997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.4140555997
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.891203021
Short name T619
Test name
Test status
Simulation time 209525416559 ps
CPU time 127.22 seconds
Started Aug 11 06:42:34 PM PDT 24
Finished Aug 11 06:44:41 PM PDT 24
Peak memory 201436 kb
Host smart-01610f0a-cd3d-4059-9ef5-6002dc94d4fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891203021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.891203021
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.447312639
Short name T415
Test name
Test status
Simulation time 100721822684 ps
CPU time 397.39 seconds
Started Aug 11 06:42:40 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 201844 kb
Host smart-f1ea50b3-bd9d-4598-ba92-02844990e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447312639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.447312639
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.553768345
Short name T712
Test name
Test status
Simulation time 25310335650 ps
CPU time 13.5 seconds
Started Aug 11 06:42:39 PM PDT 24
Finished Aug 11 06:42:53 PM PDT 24
Peak memory 201376 kb
Host smart-2e46479f-90f6-472c-85f7-f38d182ea3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553768345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.553768345
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3380763747
Short name T492
Test name
Test status
Simulation time 5321799898 ps
CPU time 7.44 seconds
Started Aug 11 06:42:39 PM PDT 24
Finished Aug 11 06:42:46 PM PDT 24
Peak memory 201324 kb
Host smart-d4b00b8e-8a0d-41c8-862a-75648f4730de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380763747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3380763747
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3900377887
Short name T390
Test name
Test status
Simulation time 5915487821 ps
CPU time 7.52 seconds
Started Aug 11 06:42:32 PM PDT 24
Finished Aug 11 06:42:40 PM PDT 24
Peak memory 201356 kb
Host smart-0b9490ee-391a-43a8-ad32-6b1a4fc630d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900377887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3900377887
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2300273664
Short name T793
Test name
Test status
Simulation time 613500434393 ps
CPU time 703.8 seconds
Started Aug 11 06:42:43 PM PDT 24
Finished Aug 11 06:54:27 PM PDT 24
Peak memory 210032 kb
Host smart-a215ba3a-0c50-442e-87d5-ec1c89809e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300273664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2300273664
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3468681274
Short name T233
Test name
Test status
Simulation time 573149076518 ps
CPU time 367.26 seconds
Started Aug 11 06:42:47 PM PDT 24
Finished Aug 11 06:48:54 PM PDT 24
Peak memory 210188 kb
Host smart-54e1c2f5-0600-43e2-b302-0c5912506fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468681274 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3468681274
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2064492976
Short name T540
Test name
Test status
Simulation time 300806958 ps
CPU time 0.89 seconds
Started Aug 11 06:42:52 PM PDT 24
Finished Aug 11 06:42:53 PM PDT 24
Peak memory 201256 kb
Host smart-41c43f5e-4416-4137-9637-57fb99c8e37d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064492976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2064492976
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1214861509
Short name T337
Test name
Test status
Simulation time 487230163570 ps
CPU time 1134.5 seconds
Started Aug 11 06:42:43 PM PDT 24
Finished Aug 11 07:01:38 PM PDT 24
Peak memory 201444 kb
Host smart-919638f6-4c4b-4f39-b614-7b6e8a91218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214861509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1214861509
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3178778171
Short name T442
Test name
Test status
Simulation time 162551801007 ps
CPU time 93.37 seconds
Started Aug 11 06:42:44 PM PDT 24
Finished Aug 11 06:44:17 PM PDT 24
Peak memory 201476 kb
Host smart-ff9a5cbe-feb8-434f-b935-8222cd3f3521
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178778171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3178778171
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1621792981
Short name T335
Test name
Test status
Simulation time 487070047416 ps
CPU time 552.84 seconds
Started Aug 11 06:42:45 PM PDT 24
Finished Aug 11 06:51:58 PM PDT 24
Peak memory 201468 kb
Host smart-91ce6be3-c534-4f5f-8eab-b331d98d12a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621792981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1621792981
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3920474312
Short name T197
Test name
Test status
Simulation time 493542408533 ps
CPU time 523.06 seconds
Started Aug 11 06:42:44 PM PDT 24
Finished Aug 11 06:51:27 PM PDT 24
Peak memory 201436 kb
Host smart-6b35317c-c0ee-498d-a355-01639f0a65a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920474312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3920474312
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3567459484
Short name T100
Test name
Test status
Simulation time 599099549006 ps
CPU time 607.16 seconds
Started Aug 11 06:42:50 PM PDT 24
Finished Aug 11 06:52:57 PM PDT 24
Peak memory 201472 kb
Host smart-9bf184a1-c342-43da-822b-d5b34e23ea92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567459484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3567459484
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3149284813
Short name T657
Test name
Test status
Simulation time 79043909765 ps
CPU time 431.39 seconds
Started Aug 11 06:42:50 PM PDT 24
Finished Aug 11 06:50:01 PM PDT 24
Peak memory 201868 kb
Host smart-2e0a8095-a996-4184-b0ae-76d4a36aca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149284813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3149284813
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4093145053
Short name T661
Test name
Test status
Simulation time 24904592344 ps
CPU time 15.65 seconds
Started Aug 11 06:42:50 PM PDT 24
Finished Aug 11 06:43:05 PM PDT 24
Peak memory 201324 kb
Host smart-83568b6b-76a3-48cd-a34d-c702c170dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093145053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4093145053
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3330310777
Short name T567
Test name
Test status
Simulation time 4095482999 ps
CPU time 5.84 seconds
Started Aug 11 06:42:47 PM PDT 24
Finished Aug 11 06:42:53 PM PDT 24
Peak memory 201344 kb
Host smart-38ccd6f6-ad3e-443c-a02e-1f3eae46fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330310777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3330310777
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.377201816
Short name T757
Test name
Test status
Simulation time 6001848064 ps
CPU time 1.98 seconds
Started Aug 11 06:42:44 PM PDT 24
Finished Aug 11 06:42:46 PM PDT 24
Peak memory 201384 kb
Host smart-17816665-e1b5-4492-8822-4ce7126f54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377201816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.377201816
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.189551983
Short name T172
Test name
Test status
Simulation time 326598281897 ps
CPU time 100.81 seconds
Started Aug 11 06:42:48 PM PDT 24
Finished Aug 11 06:44:29 PM PDT 24
Peak memory 201436 kb
Host smart-e2688734-d856-43b4-afbc-017564bdb444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189551983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
189551983
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2672590053
Short name T781
Test name
Test status
Simulation time 279758489768 ps
CPU time 107.87 seconds
Started Aug 11 06:42:49 PM PDT 24
Finished Aug 11 06:44:37 PM PDT 24
Peak memory 210088 kb
Host smart-4e414cd5-bc37-42e7-9ff8-b105b426c82c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672590053 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2672590053
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3892384369
Short name T29
Test name
Test status
Simulation time 369830198 ps
CPU time 0.89 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:43:00 PM PDT 24
Peak memory 201204 kb
Host smart-1b6ecb7a-5a48-4d60-9694-5d6f9601025c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892384369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3892384369
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2063985366
Short name T737
Test name
Test status
Simulation time 169315281260 ps
CPU time 369.56 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 201480 kb
Host smart-31dc86c5-44ad-4012-b52e-8123ed2be78c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063985366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2063985366
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4055230898
Short name T582
Test name
Test status
Simulation time 164810398838 ps
CPU time 386.14 seconds
Started Aug 11 06:43:00 PM PDT 24
Finished Aug 11 06:49:27 PM PDT 24
Peak memory 201460 kb
Host smart-a51abf13-db9e-493f-8841-ecb2d478c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055230898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4055230898
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1534762679
Short name T644
Test name
Test status
Simulation time 172614104085 ps
CPU time 415.27 seconds
Started Aug 11 06:42:53 PM PDT 24
Finished Aug 11 06:49:48 PM PDT 24
Peak memory 201424 kb
Host smart-55fc831c-b174-4c65-9013-04978848aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534762679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1534762679
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4115355307
Short name T753
Test name
Test status
Simulation time 162353837970 ps
CPU time 376.21 seconds
Started Aug 11 06:42:53 PM PDT 24
Finished Aug 11 06:49:10 PM PDT 24
Peak memory 201476 kb
Host smart-f50b613e-8c98-4ee1-a25e-e83f10a6a248
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115355307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4115355307
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.704477062
Short name T763
Test name
Test status
Simulation time 485507203740 ps
CPU time 289.77 seconds
Started Aug 11 06:42:54 PM PDT 24
Finished Aug 11 06:47:43 PM PDT 24
Peak memory 201444 kb
Host smart-66a179ac-1b56-4e14-a003-a543670a12dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704477062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.704477062
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3959793834
Short name T445
Test name
Test status
Simulation time 492429061018 ps
CPU time 1135.61 seconds
Started Aug 11 06:42:53 PM PDT 24
Finished Aug 11 07:01:49 PM PDT 24
Peak memory 201440 kb
Host smart-a4f06280-d355-47eb-8c62-2ea9f99ac23f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959793834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3959793834
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.183369836
Short name T12
Test name
Test status
Simulation time 586462824579 ps
CPU time 1338.82 seconds
Started Aug 11 06:42:58 PM PDT 24
Finished Aug 11 07:05:17 PM PDT 24
Peak memory 201448 kb
Host smart-8ee8bffa-41c3-4a6a-b875-82d94074ae3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183369836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.183369836
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2910425154
Short name T95
Test name
Test status
Simulation time 407861378187 ps
CPU time 83.36 seconds
Started Aug 11 06:42:58 PM PDT 24
Finished Aug 11 06:44:21 PM PDT 24
Peak memory 201420 kb
Host smart-6fb185f1-079b-4606-abe8-24db5d00ed96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910425154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2910425154
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2046375998
Short name T699
Test name
Test status
Simulation time 91618324182 ps
CPU time 320.5 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:48:19 PM PDT 24
Peak memory 201828 kb
Host smart-26627feb-00ba-46fe-9abb-59a4a58b06b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046375998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2046375998
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3757268920
Short name T546
Test name
Test status
Simulation time 39991939467 ps
CPU time 89.97 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:44:29 PM PDT 24
Peak memory 201272 kb
Host smart-5229883a-0983-456a-9f9d-4bed65e81ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757268920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3757268920
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.282627591
Short name T532
Test name
Test status
Simulation time 4695289055 ps
CPU time 6.59 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:43:06 PM PDT 24
Peak memory 201336 kb
Host smart-8b891b1e-f26f-4c8b-97a1-406d89d2ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282627591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.282627591
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.686142054
Short name T121
Test name
Test status
Simulation time 6047338138 ps
CPU time 7.73 seconds
Started Aug 11 06:42:58 PM PDT 24
Finished Aug 11 06:43:06 PM PDT 24
Peak memory 201396 kb
Host smart-2ab79eff-bd7d-4ac3-848e-538aa47ad18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686142054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.686142054
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3976159258
Short name T308
Test name
Test status
Simulation time 571340225021 ps
CPU time 741.53 seconds
Started Aug 11 06:42:59 PM PDT 24
Finished Aug 11 06:55:21 PM PDT 24
Peak memory 210008 kb
Host smart-eee26c01-b082-4f87-8b5f-504d1c201d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976159258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3976159258
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1789038181
Short name T612
Test name
Test status
Simulation time 68594596137 ps
CPU time 148.29 seconds
Started Aug 11 06:42:58 PM PDT 24
Finished Aug 11 06:45:27 PM PDT 24
Peak memory 209800 kb
Host smart-47f332ad-5968-45fc-888b-20a752a7101b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789038181 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1789038181
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.941938252
Short name T489
Test name
Test status
Simulation time 354904674 ps
CPU time 0.8 seconds
Started Aug 11 06:43:13 PM PDT 24
Finished Aug 11 06:43:13 PM PDT 24
Peak memory 201220 kb
Host smart-23cb0516-f164-4148-8754-8c4259dbff90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941938252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.941938252
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2420232329
Short name T671
Test name
Test status
Simulation time 368308515946 ps
CPU time 407.91 seconds
Started Aug 11 06:43:04 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 201456 kb
Host smart-1a36dca8-f2c9-438e-ac99-665bf6d5eda3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420232329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2420232329
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3704624080
Short name T26
Test name
Test status
Simulation time 479669584308 ps
CPU time 316.9 seconds
Started Aug 11 06:43:03 PM PDT 24
Finished Aug 11 06:48:20 PM PDT 24
Peak memory 201396 kb
Host smart-d6f26541-bc5b-440f-b1a8-f8a3c8fc9d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704624080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3704624080
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1505212760
Short name T539
Test name
Test status
Simulation time 489077385308 ps
CPU time 138.02 seconds
Started Aug 11 06:43:05 PM PDT 24
Finished Aug 11 06:45:23 PM PDT 24
Peak memory 201432 kb
Host smart-8d0aee78-d805-41be-aea3-3404d513a16c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505212760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1505212760
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1181319876
Short name T194
Test name
Test status
Simulation time 331574144319 ps
CPU time 736.47 seconds
Started Aug 11 06:43:04 PM PDT 24
Finished Aug 11 06:55:20 PM PDT 24
Peak memory 201472 kb
Host smart-e0c6b87b-fc4f-477f-ae3a-6d67c00baf1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181319876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1181319876
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1866455127
Short name T549
Test name
Test status
Simulation time 201284819703 ps
CPU time 264.1 seconds
Started Aug 11 06:43:03 PM PDT 24
Finished Aug 11 06:47:27 PM PDT 24
Peak memory 201436 kb
Host smart-bec5bdee-2acc-4767-beba-216d39e974db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866455127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1866455127
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2025749911
Short name T572
Test name
Test status
Simulation time 131152306622 ps
CPU time 666.35 seconds
Started Aug 11 06:43:10 PM PDT 24
Finished Aug 11 06:54:17 PM PDT 24
Peak memory 201812 kb
Host smart-1e1fde95-2dd4-4808-8757-9a99b4e37af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025749911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2025749911
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2491037131
Short name T690
Test name
Test status
Simulation time 36016698577 ps
CPU time 85.25 seconds
Started Aug 11 06:43:07 PM PDT 24
Finished Aug 11 06:44:32 PM PDT 24
Peak memory 201320 kb
Host smart-2ac7ee22-e028-4051-a8bd-5cfdb59432ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491037131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2491037131
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3691179555
Short name T575
Test name
Test status
Simulation time 3286277129 ps
CPU time 7.75 seconds
Started Aug 11 06:43:06 PM PDT 24
Finished Aug 11 06:43:14 PM PDT 24
Peak memory 201284 kb
Host smart-d262cc2d-f0b3-4d86-aa69-81608fb61032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691179555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3691179555
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1093794734
Short name T455
Test name
Test status
Simulation time 5965646811 ps
CPU time 15.15 seconds
Started Aug 11 06:43:00 PM PDT 24
Finished Aug 11 06:43:15 PM PDT 24
Peak memory 201352 kb
Host smart-c5468619-c8b1-49bd-9672-ae3a9e6cbdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093794734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1093794734
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2251500526
Short name T740
Test name
Test status
Simulation time 175501013659 ps
CPU time 202.05 seconds
Started Aug 11 06:43:15 PM PDT 24
Finished Aug 11 06:46:37 PM PDT 24
Peak memory 201476 kb
Host smart-93d100eb-f00d-45d7-9ac9-0f33389e9c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251500526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2251500526
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3438722921
Short name T80
Test name
Test status
Simulation time 505822467 ps
CPU time 1.86 seconds
Started Aug 11 06:43:20 PM PDT 24
Finished Aug 11 06:43:22 PM PDT 24
Peak memory 201248 kb
Host smart-496f0904-aa7d-4b89-bc35-dd0417c5df79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438722921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3438722921
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2030083551
Short name T292
Test name
Test status
Simulation time 514244273142 ps
CPU time 284.03 seconds
Started Aug 11 06:43:22 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 201436 kb
Host smart-3719cdc6-69dd-4b47-8aa8-825dcfd64d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030083551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2030083551
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4010399025
Short name T577
Test name
Test status
Simulation time 487916373325 ps
CPU time 568.29 seconds
Started Aug 11 06:43:15 PM PDT 24
Finished Aug 11 06:52:44 PM PDT 24
Peak memory 201448 kb
Host smart-3e7626c7-6dae-425b-836e-2e97215f387a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010399025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4010399025
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.456134736
Short name T160
Test name
Test status
Simulation time 330418792934 ps
CPU time 341.83 seconds
Started Aug 11 06:43:13 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 201400 kb
Host smart-ff3d5df9-1212-457c-92e1-8f7c972a10bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456134736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.456134736
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3151283257
Short name T434
Test name
Test status
Simulation time 167430760229 ps
CPU time 104.48 seconds
Started Aug 11 06:43:17 PM PDT 24
Finished Aug 11 06:45:02 PM PDT 24
Peak memory 201332 kb
Host smart-e960cc32-a431-465e-8649-95f43aabbe61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151283257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3151283257
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.767775746
Short name T178
Test name
Test status
Simulation time 456363644705 ps
CPU time 250.16 seconds
Started Aug 11 06:43:21 PM PDT 24
Finished Aug 11 06:47:31 PM PDT 24
Peak memory 201436 kb
Host smart-d4b5729f-12e3-489c-be07-bfc74fdb3fda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767775746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.767775746
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.301691360
Short name T452
Test name
Test status
Simulation time 400794539289 ps
CPU time 884.04 seconds
Started Aug 11 06:43:15 PM PDT 24
Finished Aug 11 06:57:59 PM PDT 24
Peak memory 201592 kb
Host smart-463acb4b-7b26-4858-b047-72e09c0393cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301691360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.301691360
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2882602985
Short name T58
Test name
Test status
Simulation time 93079273290 ps
CPU time 315.1 seconds
Started Aug 11 06:43:22 PM PDT 24
Finished Aug 11 06:48:37 PM PDT 24
Peak memory 201816 kb
Host smart-6ba6c0b5-5ca1-4de9-a263-87f21513bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882602985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2882602985
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.130533198
Short name T595
Test name
Test status
Simulation time 45680774650 ps
CPU time 26.54 seconds
Started Aug 11 06:43:18 PM PDT 24
Finished Aug 11 06:43:45 PM PDT 24
Peak memory 201340 kb
Host smart-fe892dc7-bbfe-4e8d-8a10-24c0827a35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130533198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.130533198
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1762725587
Short name T402
Test name
Test status
Simulation time 2771100249 ps
CPU time 2.14 seconds
Started Aug 11 06:43:17 PM PDT 24
Finished Aug 11 06:43:19 PM PDT 24
Peak memory 201344 kb
Host smart-e24799a3-e6fe-4c7c-9a30-326ccf1af5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762725587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1762725587
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4226869131
Short name T629
Test name
Test status
Simulation time 5999649985 ps
CPU time 13.64 seconds
Started Aug 11 06:43:12 PM PDT 24
Finished Aug 11 06:43:26 PM PDT 24
Peak memory 201364 kb
Host smart-7670e19d-a46a-4b8a-b791-319fa90ded86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226869131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4226869131
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.281065164
Short name T252
Test name
Test status
Simulation time 517434171729 ps
CPU time 1246.09 seconds
Started Aug 11 06:43:22 PM PDT 24
Finished Aug 11 07:04:08 PM PDT 24
Peak memory 201396 kb
Host smart-9e6186b5-a626-4fa4-8c57-60b51c70f0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281065164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
281065164
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1016758814
Short name T22
Test name
Test status
Simulation time 109514513423 ps
CPU time 85.4 seconds
Started Aug 11 06:43:21 PM PDT 24
Finished Aug 11 06:44:47 PM PDT 24
Peak memory 210108 kb
Host smart-dfeb2a88-98fe-4c81-90d9-809ce473df1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016758814 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1016758814
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.943534149
Short name T685
Test name
Test status
Simulation time 520714114 ps
CPU time 1.42 seconds
Started Aug 11 06:43:35 PM PDT 24
Finished Aug 11 06:43:36 PM PDT 24
Peak memory 201192 kb
Host smart-0ff98511-eaea-4b6b-93fe-5fa1cbff289a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943534149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.943534149
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2875851644
Short name T314
Test name
Test status
Simulation time 175453763873 ps
CPU time 115.16 seconds
Started Aug 11 06:43:30 PM PDT 24
Finished Aug 11 06:45:25 PM PDT 24
Peak memory 201380 kb
Host smart-7d066685-8d46-4809-8a8e-bab6f3d38133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875851644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2875851644
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1750426612
Short name T556
Test name
Test status
Simulation time 323582061894 ps
CPU time 183.78 seconds
Started Aug 11 06:43:27 PM PDT 24
Finished Aug 11 06:46:32 PM PDT 24
Peak memory 201432 kb
Host smart-615cda2d-cf2c-44d3-bc78-ea1c3a163926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750426612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1750426612
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2590323411
Short name T774
Test name
Test status
Simulation time 334905519920 ps
CPU time 220.25 seconds
Started Aug 11 06:43:25 PM PDT 24
Finished Aug 11 06:47:06 PM PDT 24
Peak memory 201472 kb
Host smart-03a15ba2-4507-44a1-897b-c37a623b553d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590323411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2590323411
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1912425063
Short name T297
Test name
Test status
Simulation time 511357474489 ps
CPU time 1183.35 seconds
Started Aug 11 06:43:22 PM PDT 24
Finished Aug 11 07:03:06 PM PDT 24
Peak memory 201464 kb
Host smart-55d641e1-4a1e-4364-9f42-873149875e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912425063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1912425063
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3313869051
Short name T670
Test name
Test status
Simulation time 159746106790 ps
CPU time 382.18 seconds
Started Aug 11 06:43:25 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 201456 kb
Host smart-05fcf3d7-ebca-4e34-9235-9c05a3d53588
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313869051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3313869051
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1127708394
Short name T695
Test name
Test status
Simulation time 185148440372 ps
CPU time 27.83 seconds
Started Aug 11 06:43:25 PM PDT 24
Finished Aug 11 06:43:52 PM PDT 24
Peak memory 201444 kb
Host smart-ccfa7a1a-da89-43fd-bfc0-6d0455783bcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127708394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1127708394
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2140727867
Short name T490
Test name
Test status
Simulation time 205585367537 ps
CPU time 241 seconds
Started Aug 11 06:43:25 PM PDT 24
Finished Aug 11 06:47:26 PM PDT 24
Peak memory 201472 kb
Host smart-732404a2-0ff1-4e9f-a0bf-b7d128ddf3df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140727867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2140727867
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3378629547
Short name T787
Test name
Test status
Simulation time 109437120404 ps
CPU time 577.76 seconds
Started Aug 11 06:43:34 PM PDT 24
Finished Aug 11 06:53:12 PM PDT 24
Peak memory 201824 kb
Host smart-34f418f6-d647-4b31-92f6-cff9ad68e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378629547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3378629547
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2267918873
Short name T580
Test name
Test status
Simulation time 31663171767 ps
CPU time 68.54 seconds
Started Aug 11 06:43:30 PM PDT 24
Finished Aug 11 06:44:39 PM PDT 24
Peak memory 201396 kb
Host smart-f2272690-57a2-41a4-9256-13b1a128af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267918873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2267918873
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1918002024
Short name T735
Test name
Test status
Simulation time 2749334212 ps
CPU time 3.58 seconds
Started Aug 11 06:43:29 PM PDT 24
Finished Aug 11 06:43:33 PM PDT 24
Peak memory 201292 kb
Host smart-56784ba7-5d40-48d8-a521-5b61e6867c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918002024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1918002024
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3516211161
Short name T396
Test name
Test status
Simulation time 5780960305 ps
CPU time 6.71 seconds
Started Aug 11 06:43:22 PM PDT 24
Finished Aug 11 06:43:28 PM PDT 24
Peak memory 201324 kb
Host smart-c833ce44-fe58-4283-8c9e-dfd03c727d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516211161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3516211161
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1424878965
Short name T760
Test name
Test status
Simulation time 343625770995 ps
CPU time 433.72 seconds
Started Aug 11 06:43:35 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 201472 kb
Host smart-915ec203-60fc-4d82-b4c8-61e4c7a2d2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424878965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1424878965
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3198007931
Short name T771
Test name
Test status
Simulation time 425528212 ps
CPU time 1.54 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:40:47 PM PDT 24
Peak memory 201272 kb
Host smart-1a6deb46-1237-41ee-9217-1f8079dc8eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198007931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3198007931
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3989555960
Short name T326
Test name
Test status
Simulation time 497234438519 ps
CPU time 568.03 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:50:16 PM PDT 24
Peak memory 201460 kb
Host smart-19cb622f-6d2d-46df-b3ee-4d0097e85c8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989555960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3989555960
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3104172244
Short name T664
Test name
Test status
Simulation time 175169341041 ps
CPU time 412.51 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:47:45 PM PDT 24
Peak memory 201476 kb
Host smart-eb2ff7d3-395b-47b4-97d7-57b2629d6ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104172244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3104172244
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3808142086
Short name T677
Test name
Test status
Simulation time 491155027424 ps
CPU time 1046.34 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:58:15 PM PDT 24
Peak memory 201436 kb
Host smart-a5fcd3a4-1bfa-4b6d-bce6-c0f5f3cde3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808142086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3808142086
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4192359928
Short name T459
Test name
Test status
Simulation time 160225159934 ps
CPU time 377.78 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:47:11 PM PDT 24
Peak memory 201448 kb
Host smart-eefe2544-e8b8-4c70-a402-82ecb02b864b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192359928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4192359928
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2323693550
Short name T107
Test name
Test status
Simulation time 165203335800 ps
CPU time 31.22 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:41:24 PM PDT 24
Peak memory 201444 kb
Host smart-d20b30b5-2e28-4989-8f4b-1d3d84eac974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323693550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2323693550
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2404387636
Short name T14
Test name
Test status
Simulation time 162867598663 ps
CPU time 186.52 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:43:55 PM PDT 24
Peak memory 201396 kb
Host smart-d3a26d98-d4e0-48f6-bce1-24b18a4a0311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404387636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2404387636
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4021950548
Short name T317
Test name
Test status
Simulation time 171640470846 ps
CPU time 102.65 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:42:34 PM PDT 24
Peak memory 201436 kb
Host smart-63356eab-41ee-4c50-b610-5d87dd2bb0cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021950548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4021950548
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4060697174
Short name T527
Test name
Test status
Simulation time 389248196641 ps
CPU time 860.61 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:55:14 PM PDT 24
Peak memory 201592 kb
Host smart-f7d067b2-b5a2-41be-b49c-5d3cfc811541
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060697174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4060697174
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4234371249
Short name T759
Test name
Test status
Simulation time 135667047555 ps
CPU time 410.37 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:47:37 PM PDT 24
Peak memory 201860 kb
Host smart-4a1797b7-33db-41a3-851d-d22e2c9379b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234371249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4234371249
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1330993678
Short name T63
Test name
Test status
Simulation time 42875387751 ps
CPU time 22.62 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:41:13 PM PDT 24
Peak memory 201524 kb
Host smart-694af7bb-02ce-46a5-9064-cbb9ec31acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330993678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1330993678
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3128990294
Short name T743
Test name
Test status
Simulation time 2875408938 ps
CPU time 7.65 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:40:59 PM PDT 24
Peak memory 201344 kb
Host smart-178d3ae3-74c9-413d-a18a-20b75ab8d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128990294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3128990294
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1218525811
Short name T89
Test name
Test status
Simulation time 8748015168 ps
CPU time 2.26 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:40:50 PM PDT 24
Peak memory 218192 kb
Host smart-673064ad-9487-4d7b-91ac-f673beb1c50e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218525811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1218525811
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.702850714
Short name T625
Test name
Test status
Simulation time 5676592152 ps
CPU time 11.65 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:41:03 PM PDT 24
Peak memory 201348 kb
Host smart-826052a4-d43e-4d59-aed4-a14ee88b7799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702850714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.702850714
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1798584327
Short name T224
Test name
Test status
Simulation time 180154146523 ps
CPU time 132.58 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:43:04 PM PDT 24
Peak memory 210128 kb
Host smart-47dbf6a3-3c96-402f-ac67-44a79bf8aa97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798584327 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1798584327
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1925893849
Short name T535
Test name
Test status
Simulation time 306371466 ps
CPU time 1.32 seconds
Started Aug 11 06:43:39 PM PDT 24
Finished Aug 11 06:43:40 PM PDT 24
Peak memory 201256 kb
Host smart-5a66d3db-4501-4efc-bb7b-173114559377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925893849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1925893849
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3383645145
Short name T348
Test name
Test status
Simulation time 161684418223 ps
CPU time 91.22 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:45:12 PM PDT 24
Peak memory 201604 kb
Host smart-224b02b9-4939-432f-ad88-b6d4f7bbf49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383645145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3383645145
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.684464022
Short name T453
Test name
Test status
Simulation time 327357795705 ps
CPU time 394.81 seconds
Started Aug 11 06:43:37 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 201472 kb
Host smart-fc495b17-c8e2-4698-b234-baeb5bc0ee04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684464022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.684464022
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.636798881
Short name T761
Test name
Test status
Simulation time 325253522542 ps
CPU time 755.75 seconds
Started Aug 11 06:43:35 PM PDT 24
Finished Aug 11 06:56:10 PM PDT 24
Peak memory 201452 kb
Host smart-ac11c2b9-3359-4638-8b27-3b1b08be24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636798881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.636798881
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4133684756
Short name T418
Test name
Test status
Simulation time 498538573692 ps
CPU time 1174.19 seconds
Started Aug 11 06:43:35 PM PDT 24
Finished Aug 11 07:03:09 PM PDT 24
Peak memory 201456 kb
Host smart-e1f618b4-f04c-47fe-b718-607da4744e15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133684756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4133684756
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1572996488
Short name T704
Test name
Test status
Simulation time 345619262217 ps
CPU time 758.24 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:56:19 PM PDT 24
Peak memory 201412 kb
Host smart-8beed48a-cef3-4471-b4c0-ab230cf9b6f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572996488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1572996488
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.639283772
Short name T769
Test name
Test status
Simulation time 197875571573 ps
CPU time 238.22 seconds
Started Aug 11 06:43:39 PM PDT 24
Finished Aug 11 06:47:37 PM PDT 24
Peak memory 201412 kb
Host smart-9f96ffc3-2257-4b53-a4c8-2586c871a5e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639283772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.639283772
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2031825338
Short name T617
Test name
Test status
Simulation time 117116974767 ps
CPU time 586.9 seconds
Started Aug 11 06:43:41 PM PDT 24
Finished Aug 11 06:53:28 PM PDT 24
Peak memory 201992 kb
Host smart-bc9d4600-2689-4e01-aef3-b6cdbd6393c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031825338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2031825338
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1321149214
Short name T751
Test name
Test status
Simulation time 43309979495 ps
CPU time 26.45 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:44:07 PM PDT 24
Peak memory 201528 kb
Host smart-aec013a4-aa01-4897-a85f-42111e16d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321149214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1321149214
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2588238240
Short name T614
Test name
Test status
Simulation time 5564063076 ps
CPU time 2.35 seconds
Started Aug 11 06:43:39 PM PDT 24
Finished Aug 11 06:43:42 PM PDT 24
Peak memory 201348 kb
Host smart-a91b2882-67cb-4082-a041-fdcfbbfb4137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588238240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2588238240
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2671889116
Short name T196
Test name
Test status
Simulation time 5907101111 ps
CPU time 3.44 seconds
Started Aug 11 06:43:36 PM PDT 24
Finished Aug 11 06:43:39 PM PDT 24
Peak memory 201348 kb
Host smart-1da13231-8d98-4a0e-b5d0-55386574d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671889116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2671889116
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.820926814
Short name T30
Test name
Test status
Simulation time 330177298353 ps
CPU time 114.98 seconds
Started Aug 11 06:43:40 PM PDT 24
Finished Aug 11 06:45:35 PM PDT 24
Peak memory 201392 kb
Host smart-0450e0a2-e6be-4e79-acde-54b3ae5a2561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820926814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
820926814
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.858332996
Short name T404
Test name
Test status
Simulation time 318196966 ps
CPU time 0.96 seconds
Started Aug 11 06:43:49 PM PDT 24
Finished Aug 11 06:43:50 PM PDT 24
Peak memory 201092 kb
Host smart-60d08483-1b97-48c1-9725-f270bbf6ae5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858332996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.858332996
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1328961243
Short name T674
Test name
Test status
Simulation time 532724825205 ps
CPU time 1176.34 seconds
Started Aug 11 06:43:50 PM PDT 24
Finished Aug 11 07:03:27 PM PDT 24
Peak memory 201248 kb
Host smart-fa8df22d-d468-4b51-98cc-866df26fb344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328961243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1328961243
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2203424313
Short name T206
Test name
Test status
Simulation time 493568363917 ps
CPU time 125.88 seconds
Started Aug 11 06:43:43 PM PDT 24
Finished Aug 11 06:45:49 PM PDT 24
Peak memory 201372 kb
Host smart-73ed578f-94e7-4f19-b83f-17283763326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203424313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2203424313
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.270325394
Short name T407
Test name
Test status
Simulation time 496542499443 ps
CPU time 559.83 seconds
Started Aug 11 06:43:45 PM PDT 24
Finished Aug 11 06:53:05 PM PDT 24
Peak memory 201460 kb
Host smart-9bc8e5b7-d398-4e72-b3d5-4a3532f2cace
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270325394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.270325394
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3173695899
Short name T732
Test name
Test status
Simulation time 164596233052 ps
CPU time 92.98 seconds
Started Aug 11 06:43:43 PM PDT 24
Finished Aug 11 06:45:16 PM PDT 24
Peak memory 201460 kb
Host smart-b529e507-d3d6-4c9e-be00-a5239af4f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173695899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3173695899
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3982875703
Short name T520
Test name
Test status
Simulation time 485963811080 ps
CPU time 1101.58 seconds
Started Aug 11 06:43:44 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 201392 kb
Host smart-d5a3143b-b3a5-4bff-b065-532ec0fb3347
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982875703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3982875703
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1605652320
Short name T116
Test name
Test status
Simulation time 621162963113 ps
CPU time 389.07 seconds
Started Aug 11 06:43:43 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 201432 kb
Host smart-cc5aeb91-4cd5-488c-ba01-481d1d729476
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605652320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1605652320
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1384084325
Short name T27
Test name
Test status
Simulation time 201300137518 ps
CPU time 241.81 seconds
Started Aug 11 06:43:44 PM PDT 24
Finished Aug 11 06:47:46 PM PDT 24
Peak memory 201468 kb
Host smart-9340b34b-c862-460d-96c3-bd587e7711ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384084325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1384084325
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.804706671
Short name T385
Test name
Test status
Simulation time 144385629625 ps
CPU time 470.75 seconds
Started Aug 11 06:43:50 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 201664 kb
Host smart-31ca3b36-b3a9-4565-bb19-441cb1974757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804706671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.804706671
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2703287509
Short name T624
Test name
Test status
Simulation time 28105499228 ps
CPU time 60.47 seconds
Started Aug 11 06:43:48 PM PDT 24
Finished Aug 11 06:44:49 PM PDT 24
Peak memory 201372 kb
Host smart-d01c4076-48ed-4f37-9f01-b6f49a98f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703287509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2703287509
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1540845639
Short name T454
Test name
Test status
Simulation time 3361764361 ps
CPU time 2.56 seconds
Started Aug 11 06:43:47 PM PDT 24
Finished Aug 11 06:43:50 PM PDT 24
Peak memory 201296 kb
Host smart-882debda-78e2-4725-8031-e9c61cf7b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540845639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1540845639
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4096940684
Short name T447
Test name
Test status
Simulation time 5925477121 ps
CPU time 7.8 seconds
Started Aug 11 06:43:43 PM PDT 24
Finished Aug 11 06:43:51 PM PDT 24
Peak memory 201356 kb
Host smart-76d57d90-d639-4a10-9129-7f7407b65145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096940684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4096940684
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1597875469
Short name T363
Test name
Test status
Simulation time 344138895291 ps
CPU time 521.63 seconds
Started Aug 11 06:43:47 PM PDT 24
Finished Aug 11 06:52:29 PM PDT 24
Peak memory 211848 kb
Host smart-0beaa1f6-b07a-4067-aa2a-94a77ecc39e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597875469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1597875469
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3869235304
Short name T343
Test name
Test status
Simulation time 142943782595 ps
CPU time 86.12 seconds
Started Aug 11 06:43:49 PM PDT 24
Finished Aug 11 06:45:15 PM PDT 24
Peak memory 209760 kb
Host smart-c5f627a9-ed79-4048-97ce-ca780236a868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869235304 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3869235304
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3580719771
Short name T457
Test name
Test status
Simulation time 310709632 ps
CPU time 1.01 seconds
Started Aug 11 06:44:02 PM PDT 24
Finished Aug 11 06:44:03 PM PDT 24
Peak memory 201232 kb
Host smart-6d4da609-b001-4e3f-b215-7972701abd07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580719771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3580719771
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1265465870
Short name T158
Test name
Test status
Simulation time 164689326604 ps
CPU time 90.57 seconds
Started Aug 11 06:43:57 PM PDT 24
Finished Aug 11 06:45:28 PM PDT 24
Peak memory 201408 kb
Host smart-a6437474-66e1-4b75-9688-b34c59f3af11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265465870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1265465870
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.381091509
Short name T214
Test name
Test status
Simulation time 329058937059 ps
CPU time 142.22 seconds
Started Aug 11 06:43:56 PM PDT 24
Finished Aug 11 06:46:19 PM PDT 24
Peak memory 201448 kb
Host smart-330d34ed-53ee-4996-8e31-b1d84857d64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381091509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.381091509
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.285251644
Short name T425
Test name
Test status
Simulation time 498832318837 ps
CPU time 1140.74 seconds
Started Aug 11 06:43:53 PM PDT 24
Finished Aug 11 07:02:54 PM PDT 24
Peak memory 201448 kb
Host smart-199333c7-0e3f-4a36-8b9a-78ec526164d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=285251644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.285251644
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1819505573
Short name T192
Test name
Test status
Simulation time 487380993705 ps
CPU time 81.12 seconds
Started Aug 11 06:43:49 PM PDT 24
Finished Aug 11 06:45:10 PM PDT 24
Peak memory 201424 kb
Host smart-fa52cd3f-e636-43dd-b818-5ef4423f3ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819505573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1819505573
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3255205693
Short name T514
Test name
Test status
Simulation time 162201497603 ps
CPU time 329.43 seconds
Started Aug 11 06:43:49 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 201272 kb
Host smart-6ac0f109-5f8b-44e4-ab30-3105b68691e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255205693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3255205693
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3459147241
Short name T304
Test name
Test status
Simulation time 187319000571 ps
CPU time 106.06 seconds
Started Aug 11 06:43:52 PM PDT 24
Finished Aug 11 06:45:38 PM PDT 24
Peak memory 201448 kb
Host smart-b55e5a8e-de02-4668-abef-8ae45a9ca8a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459147241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3459147241
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.129934526
Short name T32
Test name
Test status
Simulation time 602926897681 ps
CPU time 1398.39 seconds
Started Aug 11 06:43:51 PM PDT 24
Finished Aug 11 07:07:10 PM PDT 24
Peak memory 201508 kb
Host smart-3b281620-3c1b-4583-91b5-456f73d91f84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129934526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.129934526
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1149338555
Short name T226
Test name
Test status
Simulation time 90230794259 ps
CPU time 340.18 seconds
Started Aug 11 06:44:03 PM PDT 24
Finished Aug 11 06:49:43 PM PDT 24
Peak memory 201816 kb
Host smart-ed3fc671-e238-4736-86a1-b63711381507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149338555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1149338555
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2412770634
Short name T495
Test name
Test status
Simulation time 32175683333 ps
CPU time 70.92 seconds
Started Aug 11 06:43:58 PM PDT 24
Finished Aug 11 06:45:09 PM PDT 24
Peak memory 201344 kb
Host smart-fcbcc4f2-06e9-4b3a-a955-96043293d8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412770634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2412770634
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1335924781
Short name T444
Test name
Test status
Simulation time 2910248099 ps
CPU time 4.41 seconds
Started Aug 11 06:43:58 PM PDT 24
Finished Aug 11 06:44:03 PM PDT 24
Peak memory 201368 kb
Host smart-6e265c67-6bf8-482d-8018-882fa548eba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335924781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1335924781
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.806376355
Short name T436
Test name
Test status
Simulation time 5684457730 ps
CPU time 7.82 seconds
Started Aug 11 06:43:49 PM PDT 24
Finished Aug 11 06:43:57 PM PDT 24
Peak memory 201372 kb
Host smart-f21e1315-c5ff-4024-bd05-486744f0b3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806376355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.806376355
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1314781371
Short name T176
Test name
Test status
Simulation time 339973257899 ps
CPU time 599.8 seconds
Started Aug 11 06:44:01 PM PDT 24
Finished Aug 11 06:54:02 PM PDT 24
Peak memory 201472 kb
Host smart-8d09c999-574c-4198-bce1-879bfecafd6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314781371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1314781371
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.104069417
Short name T667
Test name
Test status
Simulation time 45953087470 ps
CPU time 130.74 seconds
Started Aug 11 06:44:02 PM PDT 24
Finished Aug 11 06:46:13 PM PDT 24
Peak memory 217616 kb
Host smart-e0006d1a-b67b-4014-ac3f-ce1081150d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104069417 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.104069417
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3791293245
Short name T475
Test name
Test status
Simulation time 443558208 ps
CPU time 1.12 seconds
Started Aug 11 06:44:12 PM PDT 24
Finished Aug 11 06:44:13 PM PDT 24
Peak memory 201248 kb
Host smart-65c008bb-b763-4050-9b3d-2e62b36bafc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791293245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3791293245
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3414094180
Short name T244
Test name
Test status
Simulation time 259871881068 ps
CPU time 489.28 seconds
Started Aug 11 06:44:07 PM PDT 24
Finished Aug 11 06:52:16 PM PDT 24
Peak memory 201456 kb
Host smart-215009cc-0ec3-4862-bf6c-f90fe7fb2048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414094180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3414094180
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.517773860
Short name T663
Test name
Test status
Simulation time 326199101037 ps
CPU time 216.42 seconds
Started Aug 11 06:44:06 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 201448 kb
Host smart-5209c26f-e913-416f-863f-50be6bcde8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517773860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.517773860
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.898526541
Short name T620
Test name
Test status
Simulation time 496167335847 ps
CPU time 1150.67 seconds
Started Aug 11 06:44:06 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 201440 kb
Host smart-644d41f3-74eb-42b1-8b0d-0b340a7048af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898526541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.898526541
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1054752868
Short name T570
Test name
Test status
Simulation time 163020958128 ps
CPU time 80.16 seconds
Started Aug 11 06:44:07 PM PDT 24
Finished Aug 11 06:45:28 PM PDT 24
Peak memory 201464 kb
Host smart-0ea1e423-41b9-4a05-8083-c995c6b9e185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054752868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1054752868
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.982053828
Short name T239
Test name
Test status
Simulation time 333022767347 ps
CPU time 796.21 seconds
Started Aug 11 06:44:02 PM PDT 24
Finished Aug 11 06:57:18 PM PDT 24
Peak memory 201456 kb
Host smart-5574d33c-79de-49c3-8ef3-20739ee31ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982053828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.982053828
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1589396862
Short name T742
Test name
Test status
Simulation time 490066813163 ps
CPU time 1086.88 seconds
Started Aug 11 06:44:01 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 201444 kb
Host smart-1288df16-9ca4-426b-84cd-0f6c1f3a3f0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589396862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1589396862
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.887428511
Short name T327
Test name
Test status
Simulation time 168768770318 ps
CPU time 198.57 seconds
Started Aug 11 06:44:06 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 201376 kb
Host smart-44b3784a-1d94-4eab-805b-ea5c7543f646
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887428511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.887428511
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3192889416
Short name T465
Test name
Test status
Simulation time 201892019240 ps
CPU time 429.87 seconds
Started Aug 11 06:44:07 PM PDT 24
Finished Aug 11 06:51:17 PM PDT 24
Peak memory 201444 kb
Host smart-5b58916e-fe9b-4c39-9da7-28df2d642d02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192889416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3192889416
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3612435785
Short name T381
Test name
Test status
Simulation time 123782963231 ps
CPU time 429.44 seconds
Started Aug 11 06:44:12 PM PDT 24
Finished Aug 11 06:51:21 PM PDT 24
Peak memory 201840 kb
Host smart-9e1caa53-8b5d-4951-854f-9a21f02744e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612435785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3612435785
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3618657835
Short name T482
Test name
Test status
Simulation time 41562481772 ps
CPU time 23.03 seconds
Started Aug 11 06:44:11 PM PDT 24
Finished Aug 11 06:44:34 PM PDT 24
Peak memory 201288 kb
Host smart-fe01b6c6-842c-4f51-b217-e2a879d0f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618657835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3618657835
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1769149418
Short name T538
Test name
Test status
Simulation time 5045922625 ps
CPU time 12.74 seconds
Started Aug 11 06:44:07 PM PDT 24
Finished Aug 11 06:44:20 PM PDT 24
Peak memory 201320 kb
Host smart-d3ce06e0-ecc7-4837-830f-9f22eb53ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769149418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1769149418
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2258293416
Short name T553
Test name
Test status
Simulation time 5603070861 ps
CPU time 2.68 seconds
Started Aug 11 06:44:02 PM PDT 24
Finished Aug 11 06:44:05 PM PDT 24
Peak memory 201324 kb
Host smart-28a7ab39-6aa3-4643-a137-c6055390d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258293416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2258293416
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3938436442
Short name T601
Test name
Test status
Simulation time 195749491912 ps
CPU time 109.49 seconds
Started Aug 11 06:44:12 PM PDT 24
Finished Aug 11 06:46:01 PM PDT 24
Peak memory 201404 kb
Host smart-b80784c6-acd2-4d88-84e4-1e1c9d7a5e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938436442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3938436442
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2462753773
Short name T288
Test name
Test status
Simulation time 24753364829 ps
CPU time 16.54 seconds
Started Aug 11 06:44:11 PM PDT 24
Finished Aug 11 06:44:27 PM PDT 24
Peak memory 211112 kb
Host smart-3bf94078-38e2-48a0-8756-f45b6e410efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462753773 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2462753773
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.273810002
Short name T430
Test name
Test status
Simulation time 447878234 ps
CPU time 1.61 seconds
Started Aug 11 06:44:26 PM PDT 24
Finished Aug 11 06:44:27 PM PDT 24
Peak memory 201384 kb
Host smart-3061608f-a7d6-4feb-a2e6-2044e6276119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273810002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.273810002
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1407476223
Short name T149
Test name
Test status
Simulation time 512936907969 ps
CPU time 1191.18 seconds
Started Aug 11 06:44:15 PM PDT 24
Finished Aug 11 07:04:06 PM PDT 24
Peak memory 201476 kb
Host smart-85505ef9-203a-4483-954a-a53c1cbe6b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407476223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1407476223
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.900879018
Short name T676
Test name
Test status
Simulation time 485439748839 ps
CPU time 1158.07 seconds
Started Aug 11 06:44:16 PM PDT 24
Finished Aug 11 07:03:35 PM PDT 24
Peak memory 201524 kb
Host smart-f7b5ae2b-6d1e-4244-b937-e56ffeb42975
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=900879018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.900879018
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2357337758
Short name T238
Test name
Test status
Simulation time 322067113168 ps
CPU time 264.18 seconds
Started Aug 11 06:44:14 PM PDT 24
Finished Aug 11 06:48:39 PM PDT 24
Peak memory 201420 kb
Host smart-f844f394-5a2a-4009-9c80-993858181c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357337758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2357337758
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.139404272
Short name T722
Test name
Test status
Simulation time 481892426615 ps
CPU time 516.47 seconds
Started Aug 11 06:44:20 PM PDT 24
Finished Aug 11 06:52:57 PM PDT 24
Peak memory 201460 kb
Host smart-6d7a9a18-8405-40e8-8048-e77674bf9b30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=139404272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.139404272
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2660801740
Short name T183
Test name
Test status
Simulation time 532223468322 ps
CPU time 64.46 seconds
Started Aug 11 06:44:16 PM PDT 24
Finished Aug 11 06:45:20 PM PDT 24
Peak memory 201436 kb
Host smart-eb5957e0-ac33-4e35-ba70-a3667f7715e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660801740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2660801740
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3104094979
Short name T586
Test name
Test status
Simulation time 606029817242 ps
CPU time 381.85 seconds
Started Aug 11 06:44:20 PM PDT 24
Finished Aug 11 06:50:42 PM PDT 24
Peak memory 201488 kb
Host smart-1cf15e79-54c2-4292-bf07-4b905f0c6f04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104094979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3104094979
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.94864534
Short name T377
Test name
Test status
Simulation time 95467024457 ps
CPU time 411.91 seconds
Started Aug 11 06:44:25 PM PDT 24
Finished Aug 11 06:51:17 PM PDT 24
Peak memory 201912 kb
Host smart-18da15db-da0c-4b3d-a187-868fd19019b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94864534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.94864534
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.474666742
Short name T429
Test name
Test status
Simulation time 40493153379 ps
CPU time 90.53 seconds
Started Aug 11 06:44:20 PM PDT 24
Finished Aug 11 06:45:51 PM PDT 24
Peak memory 201360 kb
Host smart-4689044e-6bd7-43c1-ac7f-b454526b66e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474666742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.474666742
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3426571234
Short name T590
Test name
Test status
Simulation time 3883251008 ps
CPU time 5.11 seconds
Started Aug 11 06:44:20 PM PDT 24
Finished Aug 11 06:44:25 PM PDT 24
Peak memory 201268 kb
Host smart-6919c6d8-9924-43be-a4e2-e2b44a91dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426571234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3426571234
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2682004942
Short name T474
Test name
Test status
Simulation time 5929048757 ps
CPU time 14.24 seconds
Started Aug 11 06:44:16 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 201356 kb
Host smart-768b3ac5-3a9d-40aa-95a0-c2164b0d766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682004942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2682004942
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.42320938
Short name T494
Test name
Test status
Simulation time 197763889810 ps
CPU time 214.78 seconds
Started Aug 11 06:44:27 PM PDT 24
Finished Aug 11 06:48:02 PM PDT 24
Peak memory 201420 kb
Host smart-d555c7a6-b559-49e2-aacd-3bb71f720065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.42320938
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2406631242
Short name T82
Test name
Test status
Simulation time 445001526 ps
CPU time 1.49 seconds
Started Aug 11 06:44:35 PM PDT 24
Finished Aug 11 06:44:36 PM PDT 24
Peak memory 201168 kb
Host smart-16eea99b-b15c-4a37-9234-597d7e22dbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406631242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2406631242
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2448930394
Short name T269
Test name
Test status
Simulation time 328900503939 ps
CPU time 764.64 seconds
Started Aug 11 06:44:24 PM PDT 24
Finished Aug 11 06:57:09 PM PDT 24
Peak memory 201440 kb
Host smart-88eff146-00f9-497c-9b8a-2b57903d0eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448930394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2448930394
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.268061542
Short name T564
Test name
Test status
Simulation time 496192581673 ps
CPU time 576.57 seconds
Started Aug 11 06:44:27 PM PDT 24
Finished Aug 11 06:54:05 PM PDT 24
Peak memory 201424 kb
Host smart-8a1bf837-5681-43c2-8706-9968f25a2416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=268061542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.268061542
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1267528751
Short name T353
Test name
Test status
Simulation time 164822111613 ps
CPU time 93.07 seconds
Started Aug 11 06:44:24 PM PDT 24
Finished Aug 11 06:45:58 PM PDT 24
Peak memory 201440 kb
Host smart-33e237bf-e28a-4ede-851e-7df9c1f71d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267528751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1267528751
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4189978478
Short name T686
Test name
Test status
Simulation time 495729217306 ps
CPU time 296.61 seconds
Started Aug 11 06:44:24 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 201440 kb
Host smart-120044f5-d007-4c15-b5f4-1f44fbccc8ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189978478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4189978478
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3274959865
Short name T307
Test name
Test status
Simulation time 186970634298 ps
CPU time 399.24 seconds
Started Aug 11 06:44:24 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 201444 kb
Host smart-569bae3b-b332-4731-9b62-fd1b7c641010
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274959865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3274959865
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.751087355
Short name T48
Test name
Test status
Simulation time 408843594222 ps
CPU time 225.4 seconds
Started Aug 11 06:44:25 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 201592 kb
Host smart-363f99fb-a0ad-4f00-a1c2-bd93100a7781
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751087355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.751087355
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2377606914
Short name T188
Test name
Test status
Simulation time 77531540366 ps
CPU time 417.48 seconds
Started Aug 11 06:44:35 PM PDT 24
Finished Aug 11 06:51:32 PM PDT 24
Peak memory 201840 kb
Host smart-0b793f77-6925-49fc-9f0c-85104ea65c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377606914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2377606914
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3076231467
Short name T411
Test name
Test status
Simulation time 43933832238 ps
CPU time 103.07 seconds
Started Aug 11 06:44:29 PM PDT 24
Finished Aug 11 06:46:12 PM PDT 24
Peak memory 201376 kb
Host smart-248c2f70-c436-4182-a179-246807966155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076231467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3076231467
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1826311172
Short name T507
Test name
Test status
Simulation time 4268456256 ps
CPU time 3.1 seconds
Started Aug 11 06:44:29 PM PDT 24
Finished Aug 11 06:44:32 PM PDT 24
Peak memory 201316 kb
Host smart-7076e125-0b06-49f8-b56a-3a627702aa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826311172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1826311172
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2887351199
Short name T789
Test name
Test status
Simulation time 6045270528 ps
CPU time 6.84 seconds
Started Aug 11 06:44:27 PM PDT 24
Finished Aug 11 06:44:34 PM PDT 24
Peak memory 201332 kb
Host smart-15c501d4-0bef-437c-ae2c-b1227b431e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887351199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2887351199
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1323121872
Short name T11
Test name
Test status
Simulation time 385967753892 ps
CPU time 187.73 seconds
Started Aug 11 06:44:34 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 201484 kb
Host smart-6dc8f1f0-9a82-4a83-8b4b-c9dac80860c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323121872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1323121872
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2933460297
Short name T113
Test name
Test status
Simulation time 206193799548 ps
CPU time 120.36 seconds
Started Aug 11 06:44:35 PM PDT 24
Finished Aug 11 06:46:35 PM PDT 24
Peak memory 209724 kb
Host smart-f83167df-b1bc-416a-875a-5e1673b64c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933460297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2933460297
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4261216869
Short name T583
Test name
Test status
Simulation time 324061557 ps
CPU time 0.82 seconds
Started Aug 11 06:44:53 PM PDT 24
Finished Aug 11 06:44:54 PM PDT 24
Peak memory 201212 kb
Host smart-cd8d4de8-b1af-418e-b647-3ccf9a3fe988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261216869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4261216869
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.546601190
Short name T169
Test name
Test status
Simulation time 494224058795 ps
CPU time 289.01 seconds
Started Aug 11 06:44:42 PM PDT 24
Finished Aug 11 06:49:31 PM PDT 24
Peak memory 201456 kb
Host smart-9868a27e-be43-4c2a-bbfe-f53eddc61c35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546601190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.546601190
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3705250222
Short name T691
Test name
Test status
Simulation time 499150446119 ps
CPU time 300.22 seconds
Started Aug 11 06:44:37 PM PDT 24
Finished Aug 11 06:49:38 PM PDT 24
Peak memory 201444 kb
Host smart-0641c738-a139-4191-9186-3ed14fa3a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705250222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3705250222
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3272081812
Short name T687
Test name
Test status
Simulation time 161783036275 ps
CPU time 94.97 seconds
Started Aug 11 06:44:38 PM PDT 24
Finished Aug 11 06:46:13 PM PDT 24
Peak memory 201436 kb
Host smart-67ea99ce-d3db-420d-b2d8-8a46e36d1291
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272081812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3272081812
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2064032312
Short name T145
Test name
Test status
Simulation time 161886221721 ps
CPU time 169.97 seconds
Started Aug 11 06:44:33 PM PDT 24
Finished Aug 11 06:47:23 PM PDT 24
Peak memory 201280 kb
Host smart-c8ef28de-3571-4670-b0ee-c4e0e6ef5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064032312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2064032312
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1193294175
Short name T579
Test name
Test status
Simulation time 326243587983 ps
CPU time 221.38 seconds
Started Aug 11 06:44:33 PM PDT 24
Finished Aug 11 06:48:15 PM PDT 24
Peak memory 201352 kb
Host smart-9e80ade4-10ae-4c5c-8a48-96402c14096c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193294175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1193294175
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.171591240
Short name T550
Test name
Test status
Simulation time 413332961834 ps
CPU time 233.75 seconds
Started Aug 11 06:44:41 PM PDT 24
Finished Aug 11 06:48:35 PM PDT 24
Peak memory 201448 kb
Host smart-6341e96a-dbd3-4519-879c-78d04d1f44c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171591240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.171591240
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4102209479
Short name T613
Test name
Test status
Simulation time 28676255560 ps
CPU time 4.66 seconds
Started Aug 11 06:44:47 PM PDT 24
Finished Aug 11 06:44:52 PM PDT 24
Peak memory 201344 kb
Host smart-525edec6-39a3-498e-bb02-32f60807c66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102209479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4102209479
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2038139394
Short name T694
Test name
Test status
Simulation time 4632865566 ps
CPU time 12.05 seconds
Started Aug 11 06:44:48 PM PDT 24
Finished Aug 11 06:45:00 PM PDT 24
Peak memory 201340 kb
Host smart-6d858f88-0981-4ee3-a184-7f83b427025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038139394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2038139394
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4042483610
Short name T653
Test name
Test status
Simulation time 5884180332 ps
CPU time 13.54 seconds
Started Aug 11 06:44:33 PM PDT 24
Finished Aug 11 06:44:46 PM PDT 24
Peak memory 201352 kb
Host smart-da8367ff-928a-47e9-b640-5220657a5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042483610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4042483610
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1695684690
Short name T569
Test name
Test status
Simulation time 256134101599 ps
CPU time 361.55 seconds
Started Aug 11 06:44:52 PM PDT 24
Finished Aug 11 06:50:53 PM PDT 24
Peak memory 210044 kb
Host smart-19be4417-dc03-40cc-b29e-7c12e92555a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695684690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1695684690
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3264635594
Short name T515
Test name
Test status
Simulation time 149649197346 ps
CPU time 107.58 seconds
Started Aug 11 06:44:52 PM PDT 24
Finished Aug 11 06:46:40 PM PDT 24
Peak memory 210208 kb
Host smart-316bfea4-c40c-4ee0-8715-4cc63361a71c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264635594 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3264635594
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.956545058
Short name T99
Test name
Test status
Simulation time 623470953 ps
CPU time 0.75 seconds
Started Aug 11 06:45:02 PM PDT 24
Finished Aug 11 06:45:03 PM PDT 24
Peak memory 201224 kb
Host smart-d4aa19ca-92aa-4739-8aa7-d2a40dfc03e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956545058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.956545058
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1999488485
Short name T682
Test name
Test status
Simulation time 352060808061 ps
CPU time 722.78 seconds
Started Aug 11 06:44:56 PM PDT 24
Finished Aug 11 06:56:59 PM PDT 24
Peak memory 201428 kb
Host smart-f61b3459-f3b5-451c-a295-2f2d8686c942
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999488485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1999488485
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3979059845
Short name T537
Test name
Test status
Simulation time 267071519340 ps
CPU time 136.72 seconds
Started Aug 11 06:44:56 PM PDT 24
Finished Aug 11 06:47:13 PM PDT 24
Peak memory 201408 kb
Host smart-0a05085b-556a-42f8-9860-54681e04c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979059845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3979059845
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1990192987
Short name T237
Test name
Test status
Simulation time 493394285941 ps
CPU time 559.83 seconds
Started Aug 11 06:44:53 PM PDT 24
Finished Aug 11 06:54:13 PM PDT 24
Peak memory 201444 kb
Host smart-7a17b761-f2ad-4984-a3f7-86e360ddf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990192987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1990192987
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2468118455
Short name T399
Test name
Test status
Simulation time 163439142718 ps
CPU time 104.99 seconds
Started Aug 11 06:44:56 PM PDT 24
Finished Aug 11 06:46:41 PM PDT 24
Peak memory 201488 kb
Host smart-2b42f56f-eb1c-4be4-8d24-0faeba890017
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468118455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2468118455
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2435588196
Short name T471
Test name
Test status
Simulation time 325239734050 ps
CPU time 678.69 seconds
Started Aug 11 06:44:54 PM PDT 24
Finished Aug 11 06:56:13 PM PDT 24
Peak memory 201428 kb
Host smart-2e3fae4d-a09c-4ee0-99f7-17a9357a7815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435588196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2435588196
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1543995487
Short name T117
Test name
Test status
Simulation time 496145083249 ps
CPU time 1218.68 seconds
Started Aug 11 06:44:54 PM PDT 24
Finished Aug 11 07:05:13 PM PDT 24
Peak memory 201368 kb
Host smart-f3ccf1cf-6081-4af2-813a-5211830ae49b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543995487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1543995487
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1796389179
Short name T332
Test name
Test status
Simulation time 667830405586 ps
CPU time 731.98 seconds
Started Aug 11 06:44:57 PM PDT 24
Finished Aug 11 06:57:09 PM PDT 24
Peak memory 201416 kb
Host smart-a8e021ad-787e-4b54-95bf-24ecc9bab465
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796389179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1796389179
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3360484470
Short name T608
Test name
Test status
Simulation time 595352381450 ps
CPU time 1288.99 seconds
Started Aug 11 06:44:56 PM PDT 24
Finished Aug 11 07:06:26 PM PDT 24
Peak memory 201508 kb
Host smart-98e73fc5-5f14-43c2-b745-f8fa98f67d2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360484470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3360484470
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1829807661
Short name T225
Test name
Test status
Simulation time 66554186437 ps
CPU time 354.25 seconds
Started Aug 11 06:45:01 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 201732 kb
Host smart-de8a9db9-3ff0-410d-8ff9-e2ee2c5f3163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829807661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1829807661
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3575851102
Short name T779
Test name
Test status
Simulation time 32684121307 ps
CPU time 23.14 seconds
Started Aug 11 06:45:02 PM PDT 24
Finished Aug 11 06:45:25 PM PDT 24
Peak memory 201352 kb
Host smart-26456f32-b6ae-484d-8fe8-0fcec74dece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575851102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3575851102
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.189730926
Short name T517
Test name
Test status
Simulation time 3457082815 ps
CPU time 1.8 seconds
Started Aug 11 06:45:01 PM PDT 24
Finished Aug 11 06:45:03 PM PDT 24
Peak memory 201360 kb
Host smart-3fd9ad5b-dd06-4d8b-b3f5-6e889abde5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189730926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.189730926
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2172813013
Short name T616
Test name
Test status
Simulation time 5983141363 ps
CPU time 13.12 seconds
Started Aug 11 06:44:55 PM PDT 24
Finished Aug 11 06:45:08 PM PDT 24
Peak memory 201280 kb
Host smart-a751698b-4a93-49ff-b2e0-d2f666db213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172813013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2172813013
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1446614315
Short name T528
Test name
Test status
Simulation time 115369217883 ps
CPU time 519.48 seconds
Started Aug 11 06:45:00 PM PDT 24
Finished Aug 11 06:53:40 PM PDT 24
Peak memory 217764 kb
Host smart-5d6f06ec-4c2d-4945-869c-8d3cea36e121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446614315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1446614315
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1500711587
Short name T485
Test name
Test status
Simulation time 20561962459 ps
CPU time 46 seconds
Started Aug 11 06:45:01 PM PDT 24
Finished Aug 11 06:45:47 PM PDT 24
Peak memory 210160 kb
Host smart-4ce6733c-7d32-490e-8434-5e6d11f944c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500711587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1500711587
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1060929683
Short name T421
Test name
Test status
Simulation time 353058444 ps
CPU time 1.39 seconds
Started Aug 11 06:45:07 PM PDT 24
Finished Aug 11 06:45:09 PM PDT 24
Peak memory 201256 kb
Host smart-53eef90a-e468-4af2-a169-d658e154d867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060929683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1060929683
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1094305829
Short name T171
Test name
Test status
Simulation time 174132588069 ps
CPU time 180.56 seconds
Started Aug 11 06:45:06 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 201432 kb
Host smart-68c9a5ff-ac79-4b35-95a0-8d4eba7ab187
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094305829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1094305829
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1764249182
Short name T294
Test name
Test status
Simulation time 517031844732 ps
CPU time 1055.65 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 07:02:41 PM PDT 24
Peak memory 201468 kb
Host smart-c6571b0d-f25f-4446-95f2-8a22186275be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764249182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1764249182
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.563945982
Short name T652
Test name
Test status
Simulation time 493504740061 ps
CPU time 598.35 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:55:04 PM PDT 24
Peak memory 201480 kb
Host smart-b6d58131-acfb-41e5-807e-992fdc142b5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=563945982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.563945982
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2953065217
Short name T285
Test name
Test status
Simulation time 324528141132 ps
CPU time 769.48 seconds
Started Aug 11 06:45:02 PM PDT 24
Finished Aug 11 06:57:51 PM PDT 24
Peak memory 201420 kb
Host smart-cfe85d0a-e107-4abe-aeb4-acdd3a85375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953065217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2953065217
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2296249016
Short name T715
Test name
Test status
Simulation time 155014257183 ps
CPU time 67.1 seconds
Started Aug 11 06:45:00 PM PDT 24
Finished Aug 11 06:46:08 PM PDT 24
Peak memory 201612 kb
Host smart-140d93f4-7925-4be2-8ba6-36ecc7a4ffd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296249016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2296249016
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.298225062
Short name T356
Test name
Test status
Simulation time 397375276546 ps
CPU time 891.41 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:59:57 PM PDT 24
Peak memory 201360 kb
Host smart-2543ce02-1048-4fe4-b556-ed96dc9d8da7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298225062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.298225062
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1535166585
Short name T51
Test name
Test status
Simulation time 385887842151 ps
CPU time 236 seconds
Started Aug 11 06:45:06 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 201364 kb
Host smart-3faaf586-437f-415b-86a1-e7fdd2d00e10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535166585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1535166585
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2900092339
Short name T6
Test name
Test status
Simulation time 122334800380 ps
CPU time 418.04 seconds
Started Aug 11 06:45:07 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 201900 kb
Host smart-b29caa32-8317-4aed-8375-483c632d9e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900092339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2900092339
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3506058781
Short name T62
Test name
Test status
Simulation time 31394806477 ps
CPU time 16.6 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:45:22 PM PDT 24
Peak memory 201368 kb
Host smart-a10b1312-8ce7-4135-997e-e7f6897fda47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506058781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3506058781
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2447060108
Short name T598
Test name
Test status
Simulation time 3545239351 ps
CPU time 2.7 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:45:08 PM PDT 24
Peak memory 201312 kb
Host smart-d5fb24eb-5665-470b-9959-f79b782faacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447060108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2447060108
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4272129882
Short name T387
Test name
Test status
Simulation time 5957602971 ps
CPU time 7.76 seconds
Started Aug 11 06:45:01 PM PDT 24
Finished Aug 11 06:45:09 PM PDT 24
Peak memory 201376 kb
Host smart-9d87b9c0-2e79-45d0-8336-4b94452e7f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272129882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4272129882
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.829923081
Short name T35
Test name
Test status
Simulation time 367670703875 ps
CPU time 481.92 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:53:07 PM PDT 24
Peak memory 201376 kb
Host smart-41294c7b-7a01-4b7c-ab4f-4bf3af7e0670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829923081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
829923081
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.21091625
Short name T16
Test name
Test status
Simulation time 175157789209 ps
CPU time 301.83 seconds
Started Aug 11 06:45:06 PM PDT 24
Finished Aug 11 06:50:08 PM PDT 24
Peak memory 210152 kb
Host smart-21ff160f-dd90-437b-9485-c9e296bfba4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21091625 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.21091625
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1564409588
Short name T393
Test name
Test status
Simulation time 349851529 ps
CPU time 0.68 seconds
Started Aug 11 06:45:20 PM PDT 24
Finished Aug 11 06:45:21 PM PDT 24
Peak memory 201224 kb
Host smart-ec2f0b1a-1cc4-4b89-892d-f0bb4bd6d54a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564409588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1564409588
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3592522717
Short name T513
Test name
Test status
Simulation time 500248956781 ps
CPU time 250.03 seconds
Started Aug 11 06:45:14 PM PDT 24
Finished Aug 11 06:49:24 PM PDT 24
Peak memory 201496 kb
Host smart-31e3ee36-592f-427d-b8dc-21a5d845b251
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592522717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3592522717
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.176430811
Short name T295
Test name
Test status
Simulation time 517239043927 ps
CPU time 1269.89 seconds
Started Aug 11 06:45:15 PM PDT 24
Finished Aug 11 07:06:25 PM PDT 24
Peak memory 201380 kb
Host smart-72cb1341-d312-459b-badc-56f0b4a9e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176430811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.176430811
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1271329766
Short name T309
Test name
Test status
Simulation time 484624565482 ps
CPU time 1159.94 seconds
Started Aug 11 06:45:12 PM PDT 24
Finished Aug 11 07:04:32 PM PDT 24
Peak memory 201424 kb
Host smart-7562cb72-055c-40d3-a265-e4a7d349f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271329766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1271329766
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3708615957
Short name T173
Test name
Test status
Simulation time 492812264642 ps
CPU time 1032.74 seconds
Started Aug 11 06:45:11 PM PDT 24
Finished Aug 11 07:02:24 PM PDT 24
Peak memory 201436 kb
Host smart-5768d1ba-5836-446f-b1ee-43042a00dc90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708615957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3708615957
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2105677149
Short name T248
Test name
Test status
Simulation time 492180529354 ps
CPU time 541.3 seconds
Started Aug 11 06:45:11 PM PDT 24
Finished Aug 11 06:54:12 PM PDT 24
Peak memory 201432 kb
Host smart-486c0a98-d476-4f17-ac3b-73bdc54ba873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105677149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2105677149
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3683195335
Short name T508
Test name
Test status
Simulation time 166762044897 ps
CPU time 341.59 seconds
Started Aug 11 06:45:10 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 201392 kb
Host smart-f591bd23-6037-47ce-85f4-f247b225af99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683195335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3683195335
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4291665723
Short name T159
Test name
Test status
Simulation time 193385819669 ps
CPU time 304.9 seconds
Started Aug 11 06:45:10 PM PDT 24
Finished Aug 11 06:50:15 PM PDT 24
Peak memory 201376 kb
Host smart-f5521524-f9f9-4b81-93e9-03189ff484e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291665723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4291665723
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1648948262
Short name T784
Test name
Test status
Simulation time 595356647491 ps
CPU time 208.91 seconds
Started Aug 11 06:45:16 PM PDT 24
Finished Aug 11 06:48:45 PM PDT 24
Peak memory 201420 kb
Host smart-ff9dbac0-e5ec-4c8b-ba73-4828d4880148
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648948262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1648948262
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2262531541
Short name T440
Test name
Test status
Simulation time 125492449663 ps
CPU time 705.5 seconds
Started Aug 11 06:45:22 PM PDT 24
Finished Aug 11 06:57:07 PM PDT 24
Peak memory 201876 kb
Host smart-5011280c-63e7-49a0-bdc0-0dfce114d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262531541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2262531541
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3171019704
Short name T705
Test name
Test status
Simulation time 42756667190 ps
CPU time 85.73 seconds
Started Aug 11 06:45:21 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 201268 kb
Host smart-00b52040-0461-4f66-9a1b-fcb8ad00a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171019704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3171019704
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1787903653
Short name T439
Test name
Test status
Simulation time 4037282633 ps
CPU time 9.6 seconds
Started Aug 11 06:45:14 PM PDT 24
Finished Aug 11 06:45:23 PM PDT 24
Peak memory 201292 kb
Host smart-1aa11948-d226-4e58-b269-e343b8e4d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787903653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1787903653
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4179416134
Short name T142
Test name
Test status
Simulation time 6108919745 ps
CPU time 4.1 seconds
Started Aug 11 06:45:05 PM PDT 24
Finished Aug 11 06:45:09 PM PDT 24
Peak memory 201376 kb
Host smart-19ac73a9-65d9-4b1b-a37d-d836e774e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179416134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4179416134
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3895252014
Short name T279
Test name
Test status
Simulation time 266815842260 ps
CPU time 268.75 seconds
Started Aug 11 06:45:23 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 210160 kb
Host smart-d0061c1e-42d7-45ca-a355-23051c94470d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895252014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3895252014
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2074777084
Short name T708
Test name
Test status
Simulation time 373435579 ps
CPU time 1.48 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:40:55 PM PDT 24
Peak memory 201252 kb
Host smart-047b872b-b8bd-4c4b-90a0-8a0cd4f45e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074777084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2074777084
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3665608456
Short name T339
Test name
Test status
Simulation time 191856419264 ps
CPU time 11.95 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:41:03 PM PDT 24
Peak memory 201372 kb
Host smart-46308add-e495-45ec-b7aa-79b2ae6dee81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665608456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3665608456
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3085511819
Short name T364
Test name
Test status
Simulation time 322845971129 ps
CPU time 369.49 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:47:00 PM PDT 24
Peak memory 201440 kb
Host smart-4108ed4d-56a6-4314-9800-5aef4c87aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085511819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3085511819
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.445108557
Short name T405
Test name
Test status
Simulation time 490773248332 ps
CPU time 130.63 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:43:05 PM PDT 24
Peak memory 201456 kb
Host smart-f5afedf2-0c0a-49cb-aa17-56d566fc76a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=445108557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.445108557
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2698918601
Short name T669
Test name
Test status
Simulation time 336379495719 ps
CPU time 421.6 seconds
Started Aug 11 06:40:55 PM PDT 24
Finished Aug 11 06:47:56 PM PDT 24
Peak memory 201464 kb
Host smart-5e0350f3-d198-4236-be7b-16b6920e3653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698918601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2698918601
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3599283055
Short name T635
Test name
Test status
Simulation time 327537548980 ps
CPU time 592.44 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:50:38 PM PDT 24
Peak memory 201408 kb
Host smart-b5b614fb-769c-48cc-bda5-ae577d1df11d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599283055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3599283055
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3473126658
Short name T755
Test name
Test status
Simulation time 377743149991 ps
CPU time 57.41 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 201400 kb
Host smart-f44a8c61-412a-4df1-9324-b171be7d1281
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473126658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3473126658
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1943531508
Short name T689
Test name
Test status
Simulation time 400449918024 ps
CPU time 238.38 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:44:49 PM PDT 24
Peak memory 201420 kb
Host smart-93af7f40-573c-4d95-9316-eb4ff3893a13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943531508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1943531508
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.927930994
Short name T230
Test name
Test status
Simulation time 61052557131 ps
CPU time 350.18 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 201916 kb
Host smart-b17a5590-5099-4e6d-97fd-b3eb36e6258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927930994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.927930994
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3367424430
Short name T195
Test name
Test status
Simulation time 22757466852 ps
CPU time 14.31 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:41:11 PM PDT 24
Peak memory 201364 kb
Host smart-b9789aa8-2ba2-4483-9207-bb8d7510ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367424430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3367424430
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.383773943
Short name T701
Test name
Test status
Simulation time 3683202031 ps
CPU time 2.94 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:40:56 PM PDT 24
Peak memory 201352 kb
Host smart-a2127bd6-0601-49a1-b87c-9b7ef5ff8a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383773943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.383773943
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3139156573
Short name T44
Test name
Test status
Simulation time 5857247924 ps
CPU time 4.25 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:40:54 PM PDT 24
Peak memory 201356 kb
Host smart-fe7a47b2-8f3e-4eb3-80bd-d96313a6564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139156573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3139156573
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1649362598
Short name T28
Test name
Test status
Simulation time 79003298807 ps
CPU time 308.57 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:45:58 PM PDT 24
Peak memory 210172 kb
Host smart-de21f9f9-0e12-41b5-afe1-299f9db561c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649362598 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1649362598
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3966770862
Short name T673
Test name
Test status
Simulation time 327717283 ps
CPU time 0.83 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:40:48 PM PDT 24
Peak memory 201260 kb
Host smart-438ffa3d-6678-4f5f-b731-205b1427f37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966770862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3966770862
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1882415870
Short name T270
Test name
Test status
Simulation time 172177452224 ps
CPU time 188.05 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:43:53 PM PDT 24
Peak memory 201496 kb
Host smart-c9559b22-94a4-43cd-9fc0-7b45035bc696
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882415870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1882415870
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.128834924
Short name T311
Test name
Test status
Simulation time 497922551911 ps
CPU time 280.91 seconds
Started Aug 11 06:40:46 PM PDT 24
Finished Aug 11 06:45:27 PM PDT 24
Peak memory 201464 kb
Host smart-33338224-d0c3-41de-a8f9-3c249e57fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128834924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.128834924
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1789369436
Short name T215
Test name
Test status
Simulation time 326773587272 ps
CPU time 165.78 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:43:38 PM PDT 24
Peak memory 201440 kb
Host smart-20ce67bb-d821-4d2c-9448-177bcea880ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789369436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1789369436
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1363732182
Short name T438
Test name
Test status
Simulation time 489756145580 ps
CPU time 309.18 seconds
Started Aug 11 06:40:48 PM PDT 24
Finished Aug 11 06:45:57 PM PDT 24
Peak memory 201404 kb
Host smart-b96f8fd0-ca4a-4330-948c-949e9f19c46f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363732182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1363732182
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1271367145
Short name T165
Test name
Test status
Simulation time 326575934500 ps
CPU time 756.51 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:53:31 PM PDT 24
Peak memory 201248 kb
Host smart-de998d07-2650-46aa-9e64-d311bee71e2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271367145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1271367145
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.583081364
Short name T45
Test name
Test status
Simulation time 351318146081 ps
CPU time 193.67 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:44:02 PM PDT 24
Peak memory 201412 kb
Host smart-a999cf63-0bf4-46b6-a3b7-0c7e01f6365a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583081364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.583081364
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1628264297
Short name T54
Test name
Test status
Simulation time 611979620975 ps
CPU time 1279.5 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 07:02:10 PM PDT 24
Peak memory 201412 kb
Host smart-c174801d-5b8f-4e9d-9289-8835343d7225
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628264297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1628264297
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3467192275
Short name T379
Test name
Test status
Simulation time 126724539384 ps
CPU time 654.27 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:51:45 PM PDT 24
Peak memory 201852 kb
Host smart-a827b57e-4399-4050-bdce-88f5f1f5306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467192275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3467192275
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2331966956
Short name T683
Test name
Test status
Simulation time 44067908464 ps
CPU time 14.82 seconds
Started Aug 11 06:40:45 PM PDT 24
Finished Aug 11 06:40:59 PM PDT 24
Peak memory 201272 kb
Host smart-cd1f48d9-cdd4-426b-aa24-7ee69eed6b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331966956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2331966956
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.431157196
Short name T186
Test name
Test status
Simulation time 4760369136 ps
CPU time 2.78 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:40:57 PM PDT 24
Peak memory 201344 kb
Host smart-87fc8cfa-62bd-4215-8e7d-4ba76231d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431157196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.431157196
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1262830982
Short name T395
Test name
Test status
Simulation time 5756380425 ps
CPU time 4.27 seconds
Started Aug 11 06:40:55 PM PDT 24
Finished Aug 11 06:40:59 PM PDT 24
Peak memory 201312 kb
Host smart-eedb0adf-4fb8-4256-9a3a-58595cb1e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262830982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1262830982
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3603967145
Short name T235
Test name
Test status
Simulation time 205496906174 ps
CPU time 1015.62 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:57:52 PM PDT 24
Peak memory 201832 kb
Host smart-d000d49b-75a7-4935-897a-4e3aef35367b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603967145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3603967145
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2577374483
Short name T588
Test name
Test status
Simulation time 106351799913 ps
CPU time 309.5 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:46:02 PM PDT 24
Peak memory 217868 kb
Host smart-24d94a02-9c12-4bb0-97e6-559f821b4187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577374483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2577374483
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4161083653
Short name T688
Test name
Test status
Simulation time 508437057 ps
CPU time 0.84 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:40:57 PM PDT 24
Peak memory 201216 kb
Host smart-26a58804-751b-4ec6-a771-a7dc69ee6136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161083653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4161083653
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.420232393
Short name T368
Test name
Test status
Simulation time 339863206922 ps
CPU time 742.76 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:53:20 PM PDT 24
Peak memory 201332 kb
Host smart-219125e4-136c-4c00-8c3b-205fc0b72f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420232393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.420232393
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1529627042
Short name T287
Test name
Test status
Simulation time 491092000493 ps
CPU time 115.8 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:42:52 PM PDT 24
Peak memory 201396 kb
Host smart-74ad6d10-c43d-4291-950d-0bd92d58bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529627042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1529627042
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.554516901
Short name T618
Test name
Test status
Simulation time 167816397870 ps
CPU time 108.42 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:42:39 PM PDT 24
Peak memory 201376 kb
Host smart-b9f46b7b-db78-41d5-8549-c98c17b91d74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=554516901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.554516901
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.483008075
Short name T728
Test name
Test status
Simulation time 325588334311 ps
CPU time 352.98 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:46:52 PM PDT 24
Peak memory 201460 kb
Host smart-2f9b2b0d-6336-4fdf-8755-afb07245fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483008075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.483008075
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3148308454
Short name T394
Test name
Test status
Simulation time 161530700967 ps
CPU time 368.07 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:47:04 PM PDT 24
Peak memory 201348 kb
Host smart-a433ae10-b8b9-4a86-8249-477b2f06dbdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148308454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3148308454
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2890910530
Short name T262
Test name
Test status
Simulation time 575434359836 ps
CPU time 518.47 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:49:30 PM PDT 24
Peak memory 201448 kb
Host smart-61d7a29c-8d60-4646-bc68-417d27d7525d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890910530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2890910530
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1162504253
Short name T581
Test name
Test status
Simulation time 206318573221 ps
CPU time 151.57 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:43:28 PM PDT 24
Peak memory 201448 kb
Host smart-b60bfc81-462a-4df2-8df0-a4d659857e1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162504253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1162504253
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.616002533
Short name T5
Test name
Test status
Simulation time 104015171609 ps
CPU time 538.77 seconds
Started Aug 11 06:40:55 PM PDT 24
Finished Aug 11 06:49:54 PM PDT 24
Peak memory 201732 kb
Host smart-5601b10f-df20-45c4-b3e5-2442b4b43bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616002533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.616002533
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3115160888
Short name T568
Test name
Test status
Simulation time 33536889472 ps
CPU time 18.53 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:41:11 PM PDT 24
Peak memory 201348 kb
Host smart-8690ba5c-bada-4aa8-8598-591bdaf76ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115160888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3115160888
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.559030105
Short name T632
Test name
Test status
Simulation time 2875723059 ps
CPU time 1.11 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:40:58 PM PDT 24
Peak memory 201032 kb
Host smart-fbecf682-d502-4cbe-8058-091072452168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559030105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.559030105
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2585529152
Short name T424
Test name
Test status
Simulation time 5612783991 ps
CPU time 8.35 seconds
Started Aug 11 06:40:56 PM PDT 24
Finished Aug 11 06:41:04 PM PDT 24
Peak memory 201388 kb
Host smart-9bb8b312-d5e1-46f7-be2b-a499aac5b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585529152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2585529152
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.172429715
Short name T61
Test name
Test status
Simulation time 193110101167 ps
CPU time 794.48 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:54:15 PM PDT 24
Peak memory 201196 kb
Host smart-88f467a6-4ac8-4778-aa87-50042722d3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172429715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.172429715
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3480913827
Short name T745
Test name
Test status
Simulation time 270156103510 ps
CPU time 129.76 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:43:03 PM PDT 24
Peak memory 209816 kb
Host smart-f77fb2db-d966-4bc7-8085-96dd9d10dea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480913827 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3480913827
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4188792070
Short name T81
Test name
Test status
Simulation time 400483261 ps
CPU time 1.44 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:40:52 PM PDT 24
Peak memory 201176 kb
Host smart-c825bc57-184c-4d75-83a5-f21ded89fce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188792070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4188792070
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.74765980
Short name T328
Test name
Test status
Simulation time 509150902814 ps
CPU time 263.35 seconds
Started Aug 11 06:40:49 PM PDT 24
Finished Aug 11 06:45:12 PM PDT 24
Peak memory 201464 kb
Host smart-1eb0c794-8fa8-4203-b9d3-3ed3347ede81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74765980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating
.74765980
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.580063642
Short name T240
Test name
Test status
Simulation time 336560390454 ps
CPU time 756.96 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:53:28 PM PDT 24
Peak memory 201440 kb
Host smart-1d5f37fc-7199-4872-a72a-733772ab3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580063642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.580063642
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.354991993
Short name T213
Test name
Test status
Simulation time 334317063040 ps
CPU time 196.98 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:44:14 PM PDT 24
Peak memory 201516 kb
Host smart-83567848-49a9-48d7-b668-538c54df1ae1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=354991993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.354991993
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2331399552
Short name T190
Test name
Test status
Simulation time 483799593477 ps
CPU time 228.59 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:44:48 PM PDT 24
Peak memory 201420 kb
Host smart-0728acf2-5629-4efa-806d-398d49674658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331399552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2331399552
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1676898575
Short name T605
Test name
Test status
Simulation time 493930092831 ps
CPU time 552.29 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:50:07 PM PDT 24
Peak memory 201436 kb
Host smart-d5ca3a0e-930b-47f1-9ed6-ba455d3ab986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676898575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1676898575
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4065322551
Short name T41
Test name
Test status
Simulation time 174497319575 ps
CPU time 47.69 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 201364 kb
Host smart-9a73eae3-e5ea-4ece-aa7c-7ff7fdeac8e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065322551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4065322551
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1086531267
Short name T464
Test name
Test status
Simulation time 405606477390 ps
CPU time 228.78 seconds
Started Aug 11 06:40:53 PM PDT 24
Finished Aug 11 06:44:42 PM PDT 24
Peak memory 201516 kb
Host smart-062e67eb-1f43-42b0-a728-c64d885bdff2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086531267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1086531267
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2722597131
Short name T621
Test name
Test status
Simulation time 81584643649 ps
CPU time 320.46 seconds
Started Aug 11 06:40:55 PM PDT 24
Finished Aug 11 06:46:16 PM PDT 24
Peak memory 201032 kb
Host smart-25afdf2b-1036-4eb0-886b-5f316da70c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722597131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2722597131
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3626258807
Short name T201
Test name
Test status
Simulation time 35221516430 ps
CPU time 78.3 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:42:09 PM PDT 24
Peak memory 201272 kb
Host smart-2ff674bf-20d3-4008-bfeb-6461f9127c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626258807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3626258807
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.614433211
Short name T642
Test name
Test status
Simulation time 2988578907 ps
CPU time 2.13 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:40:49 PM PDT 24
Peak memory 201344 kb
Host smart-43bd6344-ed36-49cc-8ec7-54688fa9ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614433211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.614433211
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1783707941
Short name T672
Test name
Test status
Simulation time 5887694360 ps
CPU time 4.66 seconds
Started Aug 11 06:40:47 PM PDT 24
Finished Aug 11 06:40:52 PM PDT 24
Peak memory 201280 kb
Host smart-28935910-3815-4e29-889c-7cab7bda225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783707941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1783707941
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2064257164
Short name T692
Test name
Test status
Simulation time 504879067803 ps
CPU time 266.13 seconds
Started Aug 11 06:40:51 PM PDT 24
Finished Aug 11 06:45:17 PM PDT 24
Peak memory 201412 kb
Host smart-668bbf81-c0c0-45c3-b09a-8d757b753eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064257164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2064257164
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.321097855
Short name T636
Test name
Test status
Simulation time 125739090368 ps
CPU time 190.39 seconds
Started Aug 11 06:40:50 PM PDT 24
Finished Aug 11 06:44:01 PM PDT 24
Peak memory 210224 kb
Host smart-1c798592-55e6-4c9e-93c9-4b00b65d7393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321097855 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.321097855
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.501702628
Short name T466
Test name
Test status
Simulation time 447024907 ps
CPU time 1.52 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:41:02 PM PDT 24
Peak memory 201228 kb
Host smart-3bfe0f91-8c71-422e-8461-0f246a928281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501702628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.501702628
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.95774292
Short name T241
Test name
Test status
Simulation time 163341814526 ps
CPU time 92.94 seconds
Started Aug 11 06:40:58 PM PDT 24
Finished Aug 11 06:42:31 PM PDT 24
Peak memory 201420 kb
Host smart-49335adb-2ce6-4b08-9d26-67e388807321
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95774292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating
.95774292
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2023203490
Short name T203
Test name
Test status
Simulation time 369907349613 ps
CPU time 160.54 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:43:41 PM PDT 24
Peak memory 201600 kb
Host smart-5c924415-6596-4395-9df4-31228cabe0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023203490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2023203490
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3024690796
Short name T509
Test name
Test status
Simulation time 495245987241 ps
CPU time 88.73 seconds
Started Aug 11 06:41:00 PM PDT 24
Finished Aug 11 06:42:29 PM PDT 24
Peak memory 201464 kb
Host smart-1f9fbeed-cd1a-46c7-b6c3-1555e7da31e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024690796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3024690796
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1668216447
Short name T791
Test name
Test status
Simulation time 326588766552 ps
CPU time 180.7 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:43:53 PM PDT 24
Peak memory 201464 kb
Host smart-ee40413d-fbe7-4e74-a5a6-60d0b9fb4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668216447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1668216447
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2773610237
Short name T622
Test name
Test status
Simulation time 168232862118 ps
CPU time 42.12 seconds
Started Aug 11 06:40:54 PM PDT 24
Finished Aug 11 06:41:36 PM PDT 24
Peak memory 201368 kb
Host smart-647f7855-384f-4b3f-80e1-85ff1913339b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773610237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2773610237
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3359049061
Short name T391
Test name
Test status
Simulation time 401068902750 ps
CPU time 459.61 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:48:42 PM PDT 24
Peak memory 201528 kb
Host smart-f6a59e94-bb3b-4625-a5b1-916faf4f906e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359049061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3359049061
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.573255497
Short name T717
Test name
Test status
Simulation time 123594996658 ps
CPU time 509.73 seconds
Started Aug 11 06:40:57 PM PDT 24
Finished Aug 11 06:49:27 PM PDT 24
Peak memory 201788 kb
Host smart-8131fcac-9f01-4493-8776-f1ed3526fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573255497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.573255497
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2273446811
Short name T544
Test name
Test status
Simulation time 41254076442 ps
CPU time 96.36 seconds
Started Aug 11 06:41:02 PM PDT 24
Finished Aug 11 06:42:38 PM PDT 24
Peak memory 201344 kb
Host smart-c0487c36-9441-4abf-b698-93af43fff3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273446811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2273446811
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3269451984
Short name T498
Test name
Test status
Simulation time 4163992215 ps
CPU time 5.58 seconds
Started Aug 11 06:41:01 PM PDT 24
Finished Aug 11 06:41:06 PM PDT 24
Peak memory 200640 kb
Host smart-8118af51-0ee9-4d7f-9d80-febd21a9667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269451984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3269451984
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1408894590
Short name T604
Test name
Test status
Simulation time 6015387088 ps
CPU time 15.04 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:41:14 PM PDT 24
Peak memory 201316 kb
Host smart-9425f54a-52f6-4bc0-aecb-b04f0cfcadb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408894590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1408894590
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.23779793
Short name T340
Test name
Test status
Simulation time 366988752911 ps
CPU time 819.82 seconds
Started Aug 11 06:40:59 PM PDT 24
Finished Aug 11 06:54:39 PM PDT 24
Peak memory 201408 kb
Host smart-37aa68d9-9890-4500-9f8a-f066c2a43e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.23779793
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3558215305
Short name T366
Test name
Test status
Simulation time 981427771223 ps
CPU time 816.18 seconds
Started Aug 11 06:40:55 PM PDT 24
Finished Aug 11 06:54:32 PM PDT 24
Peak memory 217836 kb
Host smart-a3aa428b-e615-4890-8bf0-72e7e9f3b2ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558215305 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3558215305
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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