Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5910	1			T8	20		T47	7		T48	62
testmodes[AdcCtrlTestmodeNormal]	5104	1			T1	2		T2	1		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5059	1			T4	3		T7	3		T11	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2905	1			T8	19		T47	2		T48	26
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1620	1			T47	5		T48	18		T43	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1266	1			T48	18		T43	15		T50	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1607	1			T47	5		T48	21		T43	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1896	1			T1	1		T3	2		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1276	1			T48	17		T43	15		T50	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1281	1			T48	15		T43	15		T50	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1256	1			T48	20		T43	15		T50	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2269	1			T4	2		T7	2		T11	2