Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20614

1

T1

5

T2

1

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3486

1

T1

9

T3

16

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18202

1

T1

5

T3

17

T4

6

auto[1]

5898

1

T1

9

T2

1

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	258	1			T44	1		T45	36		T220	4
values[1]	649	1			T1	9		T6	1		T11	15
values[2]	653	1			T4	16		T6	1		T11	37
values[3]	705	1			T4	4		T5	1		T41	5
values[4]	769	1			T137	19		T156	26		T152	23
values[5]	701	1			T41	8		T192	1		T46	12
values[6]	777	1			T1	5		T3	12		T5	1
values[7]	671	1			T3	4		T41	14		T44	7
values[8]	2784	1			T2	1		T6	1		T7	33
values[9]	916	1			T3	1		T4	2		T43	13
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T6	1		T11	15		T133	14
values[1]	624	1			T4	16		T5	1		T6	1
values[2]	771	1			T4	4		T41	5		T137	3
values[3]	773	1			T137	16		T192	1		T156	26
values[4]	702	1			T41	8		T137	3		T46	12
values[5]	774	1			T1	5		T3	16		T5	1
values[6]	2921	1			T2	1		T7	33		T9	25
values[7]	431	1			T6	1		T112	1		T44	10
values[8]	901	1			T3	1		T4	2		T43	13
values[9]	188	1			T220	4		T141	13		T179	28
minimum	15497	1			T1	9		T8	20		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T6	1		T11	12		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T133	13		T145	13		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	16		T11	17		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T6	1		T22	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	4		T145	3		T151	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T41	5		T137	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	1		T192	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T156	14		T167	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	1		T46	6		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	8		T12	3		T156	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	3		T5	1		T11	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	2		T44	12		T156	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T2	1		T7	33		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	14		T43	1		T44	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T112	1		T25	10		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	1		T44	9		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T43	4		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T4	2		T46	13		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T220	4		T141	3		T222	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T179	18		T223	3		T172	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15142	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	9		T136	14		T30	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T11	3		T139	1		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	1		T145	11		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	20		T46	1		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T22	24		T33	1		T225	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T145	2		T151	13		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	2		T26	10		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	15		T152	12		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T156	12		T148	11		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T137	2		T46	6		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	1		T156	2		T141	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	2		T11	9		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	14		T44	12		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T9	22		T10	25		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	1		T44	4		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T143	8		T149	5		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T44	1		T152	7		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	9		T45	17		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T46	3		T133	14		T31	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T141	10		T222	9		T232	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T179	10		T172	4		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T136	14		T30	12		T234	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T44	1		T45	19		T220	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T170	1		T235	15		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	1		T11	12		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	9		T133	13		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	16		T11	17		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T22	28		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	4		T145	3		T237	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T41	5		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	1		T152	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T137	1		T156	14		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T192	1		T46	6		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	8		T156	12		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	3		T5	1		T11	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T44	12		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	7		T29	11		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T41	14		T44	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	1		T7	33		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	1		T43	1		T44	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T43	4		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T4	2		T46	13		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T45	17		T143	12		T141	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T170	12		T236	7		T172	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T11	3		T226	9		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T133	1		T136	14		T30	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	20		T46	1		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	24		T145	11		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T145	2		T237	15		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T26	10		T149	2		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T137	15		T152	12		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T137	2		T156	12		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T46	6		T33	1		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T156	2		T141	19		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	2		T11	9		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	11		T44	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T45	11		T178	10		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	3		T44	4		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T9	22		T10	25		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	1		T44	1		T133	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T43	9		T152	9		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T46	3		T133	14		T31	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T11	4		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	2		T145	12		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	1		T11	21		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T6	1		T22	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T145	3		T151	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	1		T137	3		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	16		T192	1		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T156	13		T167	1		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T137	3		T46	7		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	1		T12	3		T156	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	3		T5	1		T11	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	16		T44	13		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T2	1		T7	3		T9	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	1		T43	2		T44	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T112	1		T25	1		T143	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T6	1		T44	2		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T43	10		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T4	1		T46	4		T133	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T220	1		T141	11		T222	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	11		T223	1		T172	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15226	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	1		T136	15		T30	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T11	11		T25	2		T151	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T133	12		T145	12		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	15		T11	16		T132	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T22	26		T29	9		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	3		T145	2		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	4		T151	12		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T152	10		T33	1		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	13		T242	6		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	5		T243	4		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	7		T12	1		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T11	7		T29	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T44	11		T156	1		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T7	30		T42	38		T45	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T41	13		T44	2		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T25	9		T143	12		T194	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T44	8		T25	14		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	3		T45	18		T196	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T46	12		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T220	3		T141	2		T222	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T179	17		T223	2		T172	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T239	14		T99	12		T244	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	8		T136	13		T30	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T44	1		T45	18		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T170	13		T235	1		T236	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T6	1		T11	4		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T133	2		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T11	21		T46	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T22	26		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	1		T145	3		T237	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T41	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	16		T152	13		T149	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T137	3		T156	13		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T192	1		T46	7		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	1		T156	3		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T5	1		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	12		T44	13		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T45	12		T29	1		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	4		T41	1		T44	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T7	3		T9	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	1		T43	2		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T43	10		T152	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T4	1		T46	4		T133	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T45	18		T220	3		T143	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T235	14		T172	4		T245	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	11		T25	2		T226	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	8		T133	12		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	15		T11	16		T132	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T22	26		T29	9		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	3		T145	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	4		T246	9		T151	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	10		T241	9		T162	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T156	13		T242	6		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	5		T29	10		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	7		T156	11		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T11	7		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	11		T12	1		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	6		T29	10		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	13		T44	2		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T7	30		T42	38		T196	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T44	8		T133	2		T25	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	3		T152	11		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T46	12		T133	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20827

1

T1

14

T2

1

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3273

1

T4

22

T5

1

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18425

1

T1

9

T3

13

T4

4

auto[1]

5675

1

T1

5

T2

1

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T196	20		T29	10		T167	1
values[1]	645	1			T43	2		T44	7		T46	2
values[2]	2860	1			T2	1		T7	33		T9	25
values[3]	677	1			T3	13		T4	4		T41	5
values[4]	664	1			T11	37		T133	7		T139	2
values[5]	719	1			T4	16		T6	1		T41	14
values[6]	560	1			T44	34		T192	1		T133	25
values[7]	701	1			T3	4		T4	2		T6	1
values[8]	839	1			T1	5		T5	1		T41	8
values[9]	950	1			T1	9		T5	1		T6	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	520	1			T112	1		T43	2		T46	2
values[1]	2904	1			T2	1		T3	1		T4	4
values[2]	600	1			T3	12		T41	5		T22	27
values[3]	775	1			T11	37		T133	7		T139	2
values[4]	689	1			T4	16		T6	1		T41	14
values[5]	606	1			T44	34		T192	1		T25	3
values[6]	654	1			T3	4		T4	2		T6	1
values[7]	872	1			T1	5		T5	1		T6	1
values[8]	883	1			T1	9		T5	1		T137	16
values[9]	121	1			T146	1		T85	13		T248	27
minimum	15476	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	1		T156	12		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T112	1		T43	1		T25	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T2	1		T3	1		T7	33
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	4		T132	14		T22	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T22	11		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	5		T30	11		T184	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	17		T133	3		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T145	10		T249	3		T250	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T41	14		T45	7		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	16		T6	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T44	21		T192	1		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	3		T167	1		T149	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T11	12		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	2		T6	1		T43	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	3		T33	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T6	1		T11	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	9		T5	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T192	1		T46	6		T196	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T146	1		T85	13		T248	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T251	16		T252	1		T253	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15166	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T12	3		T226	1		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T46	1		T156	2		T230	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T43	1		T228	7		T166	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T9	22		T10	25		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	12		T22	8		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	11		T22	16		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T30	10		T152	12		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	20		T133	4		T139	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	9		T249	4		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	11		T133	14		T30	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T31	13		T250	12		T243	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T44	13		T152	9		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	16		T145	11		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	3		T11	3		T137	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T43	9		T45	17		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	2		T33	1		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	9		T22	10		T30	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T137	15		T136	14		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	6		T152	7		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T248	15		T254	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T251	13		T253	9		T255	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	4		T12	2		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T12	1		T226	10		T234	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T146	1		T226	7		T229	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T196	20		T29	10		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T44	3		T46	1		T156	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	1		T12	3		T25	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	1		T7	33		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T112	1		T132	14		T22	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	2		T197	5		T22	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	4		T41	5		T30	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	17		T133	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T152	11		T145	10		T250	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	14		T45	7		T30	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	16		T6	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	21		T192	1		T133	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T31	1		T25	3		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T11	12		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	2		T6	1		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	3		T41	8		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T43	4		T22	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	9		T5	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T6	1		T11	8		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T226	9		T229	4		T256	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T239	2		T228	14		T155	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	4		T46	1		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	1		T12	1		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	12		T22	8		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	11		T22	16		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	10		T249	4		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	20		T133	4		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T152	12		T145	9		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	11		T30	12		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T250	12		T243	16		T257	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	13		T133	14		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T31	13		T149	2		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	3		T11	3		T133	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	17		T46	3		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	2		T137	4		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	9		T22	10		T30	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	15		T136	14		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	9		T46	6		T156	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2