Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20982

1

T2

1

T5

1

T7

33

auto[ADC_CTRL_FILTER_COND_OUT]

3118

1

T1

14

T3

17

T4

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17906

1

T1

9

T3

17

T4

4

auto[1]

6194

1

T1

5

T2

1

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	426	1			T48	6		T43	2		T50	3
values[0]	14	1			T187	1		T109	13		-	-
values[1]	765	1			T3	4		T11	15		T46	2
values[2]	2871	1			T2	1		T4	2		T5	1
values[3]	753	1			T1	9		T11	17		T44	24
values[4]	623	1			T3	12		T6	1		T137	16
values[5]	747	1			T1	5		T41	22		T45	18
values[6]	619	1			T112	1		T45	36		T46	12
values[7]	717	1			T4	16		T196	20		T26	11
values[8]	758	1			T3	1		T5	1		T11	37
values[9]	956	1			T4	4		T41	5		T44	17
minimum	14851	1			T8	20		T47	18		T48	174

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T3	4		T4	2		T11	15
values[1]	2928	1			T2	1		T6	2		T7	33
values[2]	777	1			T1	9		T3	12		T5	1
values[3]	582	1			T6	1		T41	14		T137	16
values[4]	749	1			T1	5		T41	8		T45	54
values[5]	653	1			T4	16		T112	1		T46	12
values[6]	664	1			T26	11		T29	11		T30	21
values[7]	886	1			T3	1		T5	1		T43	13
values[8]	645	1			T4	4		T11	37		T41	5
values[9]	105	1			T44	7		T137	3		T241	7
minimum	15230	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T11	12		T22	17		T29	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T4	2		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T2	1		T7	33		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	2		T44	12		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T5	1		T11	8		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	9		T3	1		T156	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	1		T132	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	1		T41	14		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T45	7		T25	3		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	3		T41	8		T45	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T112	1		T46	6		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	16		T196	20		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	1		T29	11		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	11		T238	1		T240	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T44	1		T133	3		T30	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T3	1		T5	1		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T192	1		T197	5		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	4		T11	17		T41	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T44	3		T241	7		T169	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T137	1		T249	1		T287	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T109	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	3		T22	8		T152	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	3		T43	1		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T9	22		T10	25		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	12		T136	14		T30	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	9		T133	1		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	11		T156	12		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	15		T132	12		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T226	10		T234	2		T189	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	11		T229	4		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	2		T45	17		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	6		T178	10		T230	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T22	16		T152	9		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T26	10		T156	2		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T30	10		T234	14		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	4		T30	12		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	9		T44	1		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T186	12		T148	7		T170	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	20		T137	2		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T44	4		T169	9		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T137	2		T287	1		T93	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T48	6		T43	2		T50	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T318	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T187	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T109	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	12		T29	10		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T46	1		T22	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	1		T5	1		T7	33
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	2		T6	2		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	8		T133	13		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	9		T44	12		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T137	1		T132	14		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	1		T6	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	7		T168	1		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	3		T41	22		T25	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T112	1		T46	6		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T45	19		T133	11		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	1		T142	1		T143	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	16		T196	20		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T44	1		T29	11		T30	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T5	1		T11	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T44	3		T192	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	4		T41	5		T44	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14737	1			T8	20		T47	18		T48	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T169	9		T311	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T318	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	3		T152	12		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	3		T46	1		T22	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	1		T136	14		T30	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	9		T133	1		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T44	12		T156	12		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T137	15		T132	12		T145	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	11		T234	2		T302	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	11		T178	10		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	2		T226	10		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T46	6		T270	1		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	17		T133	14		T22	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	10		T143	12		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T30	10		T145	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	12		T156	2		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	20		T43	9		T46	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T44	4		T133	4		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	1		T137	4		T156	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	4		T22	9		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	4		T4	1		T43	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T2	1		T7	3		T9	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	2		T44	13		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	1		T11	10		T133	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T3	12		T156	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	16		T132	13		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	1		T41	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T45	12		T25	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	3		T41	1		T45	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T112	1		T46	7		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	1		T196	1		T22	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T26	11		T29	1		T156	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	11		T238	1		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	1		T133	5		T30	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	1		T5	1		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T192	1		T197	1		T186	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T11	21		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T44	5		T241	1		T169	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T137	3		T249	1		T287	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T109	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	11		T22	16		T29	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T22	11		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T7	30		T42	38		T24	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T44	11		T136	13		T30	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T11	7		T133	12		T25	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	8		T156	13		T84	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	13		T12	1		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T41	13		T220	3		T241	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	6		T25	2		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T41	7		T45	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	5		T27	1		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	15		T196	19		T22	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	10		T156	11		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	10		T240	13		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T133	2		T30	11		T162	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T43	3		T44	8		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T197	4		T258	3		T84	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	3		T11	16		T41	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T44	2		T241	6		T169	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T319	8		T253	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T109	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T48	6		T43	2		T50	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T318	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T187	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T109	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	4		T29	1		T152	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	4		T46	2		T22	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T5	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T6	2		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	10		T133	2		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T44	13		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T137	16		T132	13		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	12		T6	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T45	12		T168	1		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	3		T41	2		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T112	1		T46	7		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	18		T133	15		T22	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	11		T142	1		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T196	1		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T44	1		T29	1		T30	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T5	1		T11	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T44	5		T192	1		T133	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	1		T41	1		T44	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14851	1			T8	20		T47	18		T48	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T169	8		T311	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T318	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T109	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	11		T29	9		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T22	11		T143	12		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T7	30		T42	38		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T136	13		T30	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	7		T133	12		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	8		T44	11		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	13		T145	21		T242	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T220	3		T234	2		T277	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T45	6		T178	10		T241	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	2		T41	20		T25	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T46	5		T25	2		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	18		T133	10		T22	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T143	10		T151	14		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	15		T196	19		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	10		T30	11		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	16		T43	3		T46	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	2		T133	2		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	3		T41	4		T44	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30