Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20675

1

T1

14

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3425

1

T3

1

T4

18

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T3

13

T4

2

T8

20

auto[1]

5725

1

T1

14

T2

1

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T320	1		T321	4		T322	3
values[0]	58	1			T145	5		T202	23		T171	11
values[1]	622	1			T44	17		T137	16		T46	2
values[2]	575	1			T3	5		T11	15		T43	2
values[3]	709	1			T1	9		T4	16		T41	8
values[4]	573	1			T1	5		T4	2		T43	13
values[5]	2905	1			T2	1		T6	1		T7	33
values[6]	620	1			T4	4		T6	1		T46	16
values[7]	808	1			T6	1		T44	24		T192	1
values[8]	687	1			T5	2		T133	25		T12	4
values[9]	1318	1			T3	12		T11	37		T41	19
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	845	1			T11	15		T44	17		T137	19
values[1]	567	1			T3	4		T4	16		T41	8
values[2]	786	1			T1	14		T3	1		T4	2
values[3]	2925	1			T2	1		T7	33		T9	25
values[4]	508	1			T6	1		T112	1		T137	3
values[5]	759	1			T4	4		T6	1		T46	16
values[6]	696	1			T5	1		T6	1		T44	24
values[7]	707	1			T3	12		T5	1		T12	4
values[8]	851	1			T11	37		T41	19		T44	1
values[9]	234	1			T200	17		T301	1		T302	15
minimum	15222	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	12		T44	12		T137	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	15		T142	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T22	12		T184	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	16		T41	8		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	12		T43	4		T46	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T4	2		T45	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T7	33		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	8		T192	1		T136	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	1		T112	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T168	1		T275	1		T323	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	4		T6	1		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T31	1		T29	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	11		T156	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T6	1		T44	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T5	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T152	12		T149	1		T162	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T41	14		T25	3		T178	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	17		T41	5		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T200	10		T305	13		T309	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T301	1		T302	1		T303	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T284	1		T324	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	3		T44	5		T137	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T230	1		T249	4		T169	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	3		T22	10		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T43	1		T45	17		T30	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	2		T43	9		T46	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T45	11		T133	1		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T9	22		T10	25		T135	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	9		T136	14		T22	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	2		T156	12		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T275	5		T231	8		T272	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T46	3		T33	1		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	13		T139	1		T143	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	14		T156	11		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	12		T133	14		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	11		T12	1		T22	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	7		T149	2		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T178	10		T151	2		T186	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	20		T132	12		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T200	7		T305	4		T309	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T302	14		T325	6		T293	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T284	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	1		T322	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T145	3		T171	1		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T202	12		T284	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	12		T137	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	15		T142	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T11	12		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	1		T43	1		T45	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	9		T46	6		T197	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	16		T41	8		T45	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	3		T43	4		T241	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	2		T192	1		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T2	1		T6	1		T7	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	8		T22	11		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	4		T6	1		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T31	1		T29	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T196	20		T30	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	1		T44	12		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T12	3		T156	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T133	11		T25	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T3	1		T41	14		T22	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T11	17		T41	5		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T321	3		T322	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T145	2		T171	10		T327	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T202	11		T284	3		T261	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	5		T137	15		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T230	1		T249	4		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	3		T11	3		T137	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T43	1		T45	17		T30	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	6		T22	10		T152	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T45	11		T145	9		T141	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	2		T43	9		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T133	1		T136	14		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T9	22		T10	25		T135	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	9		T22	16		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	3		T156	12		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T31	13		T139	1		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	14		T33	1		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	12		T151	13		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T156	11		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	14		T149	2		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	11		T22	8		T178	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T11	20		T132	12		T26	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	4		T44	7		T137	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	1		T142	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	4		T22	11		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	1		T41	1		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	4		T43	10		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	1		T4	1		T45	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	1		T7	3		T9	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	10		T192	1		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T112	1		T137	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T168	1		T275	6		T323	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	1		T6	1		T46	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T31	14		T29	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	15		T156	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T6	1		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	12		T5	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	8		T149	3		T162	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	1		T25	1		T178	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T11	21		T41	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T200	8		T305	5		T309	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T301	1		T302	15		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T284	4		T324	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	11		T44	10		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	14		T249	2		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	11		T184	15		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	15		T41	7		T45	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	10		T43	3		T46	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T45	6		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T7	30		T42	38		T24	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	7		T136	13		T22	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T156	13		T246	9		T237	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T85	12		T310	14		T272	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	3		T46	12		T196	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	10		T220	3		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T30	10		T156	1		T225	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	11		T133	10		T25	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T22	16		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T152	11		T162	17		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T41	13		T25	2		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	16		T41	4		T132	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T200	9		T305	12		T309	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T303	2		T325	6		T288	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T321	4		T322	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T145	3		T171	11		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T202	12		T284	4		T261	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T44	7		T137	16		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T25	1		T142	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	4		T11	4		T137	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T43	2		T45	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T46	7		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T41	1		T45	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	3		T43	10		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T192	1		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T2	1		T6	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	10		T22	17		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	1		T6	1		T46	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	14		T29	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T196	1		T30	15		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	1		T44	13		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T12	3		T156	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T133	15		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T3	12		T41	1		T22	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T11	21		T41	1		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T145	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T202	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	10		T133	2		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	14		T249	2		T169	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	11		T184	15		T226	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T45	18		T29	10		T30	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	8		T46	5		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	15		T41	7		T45	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	2		T43	3		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	1		T133	12		T136	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T7	30		T42	38		T24	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	7		T22	10		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	3		T46	12		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T29	10		T143	12		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T196	19		T30	10		T228	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	11		T27	1		T220	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	1		T156	1		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T133	10		T25	9		T162	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T41	13		T22	16		T25	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	16		T41	4		T132	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30