Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18193

1

T1

5

T3

13

T4

22

auto[ADC_CTRL_FILTER_COND_OUT]

5907

1

T1

9

T2

1

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18004

1

T5

2

T6

2

T8

20

auto[1]

6096

1

T1

14

T2

1

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T280	12		T308	11		T319	8
values[0]	62	1			T46	2		T328	1		T306	1
values[1]	696	1			T5	1		T6	1		T11	17
values[2]	577	1			T112	1		T43	13		T137	3
values[3]	566	1			T1	9		T41	5		T44	7
values[4]	735	1			T3	4		T6	2		T43	2
values[5]	757	1			T4	16		T41	22		T137	16
values[6]	878	1			T3	12		T4	4		T5	1
values[7]	751	1			T11	15		T44	34		T137	3
values[8]	587	1			T4	2		T133	14		T196	20
values[9]	3243	1			T1	5		T2	1		T3	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	832	1			T6	1		T11	17		T112	1
values[1]	2988	1			T1	9		T2	1		T7	33
values[2]	497	1			T41	5		T43	2		T44	7
values[3]	696	1			T3	4		T6	2		T44	1
values[4]	894	1			T4	16		T5	1		T41	22
values[5]	782	1			T3	12		T4	4		T45	36
values[6]	691	1			T44	34		T137	3		T196	20
values[7]	657	1			T4	2		T11	52		T133	14
values[8]	721	1			T1	5		T192	1		T29	11
values[9]	116	1			T3	1		T29	11		T225	24
minimum	15226	1			T5	1		T8	20		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	8		T136	14		T12	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	1		T112	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T168	1		T149	1		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T1	9		T2	1		T7	33
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T45	7		T220	4		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	5		T43	1		T44	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T44	1		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T6	1		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	16		T41	22		T46	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T137	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T4	4		T45	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T192	1		T156	2		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	9		T142	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	12		T137	1		T196	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	2		T133	13		T197	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	29		T22	28		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	3		T29	11		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T192	1		T139	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T3	1		T29	11		T250	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	9		T154	1		T248	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T5	1		T241	7		T180	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	9		T136	14		T12	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T46	1		T226	9		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T149	14		T145	2		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1035	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T45	11		T227	4		T262	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T44	4		T133	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	12		T22	10		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	3		T133	14		T31	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	6		T156	2		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T137	15		T156	12		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	11		T45	17		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	11		T230	1		T153	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	1		T169	9		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T44	12		T137	2		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T133	1		T178	10		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	23		T22	24		T30	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	2		T158	10		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T139	1		T151	13		T179	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T250	10		T284	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T225	15		T248	10		T236	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T280	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T308	1		T319	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T328	1		T306	1		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T46	1		T180	1		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	8		T136	14		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T6	1		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T168	1		T145	3		T162	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T112	1		T43	4		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T149	1		T200	10		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	9		T41	5		T44	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T44	1		T45	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T6	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	16		T41	22		T46	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T137	1		T29	10		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	1		T4	4		T45	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T192	1		T156	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	9		T25	10		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	12		T44	12		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T4	2		T133	13		T197	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T196	20		T22	11		T30	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T1	3		T3	1		T29	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1661	1			T2	1		T7	33		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T280	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T308	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T329	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T46	1		T327	11		T330	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	9		T136	14		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	12		T226	9		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T145	2		T162	11		T148	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	9		T137	2		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T149	14		T200	7		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	4		T133	4		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T45	11		T132	12		T22	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	3		T43	1		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T46	6		T149	5		T275	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T137	15		T156	12		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	11		T45	17		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T156	11		T152	9		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T44	1		T141	10		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	3		T44	12		T137	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T133	1		T178	10		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	16		T30	14		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	2		T250	10		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1069	1			T9	22		T10	25		T11	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	10		T136	15		T12	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T6	1		T112	1		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T168	1		T149	15		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T1	1		T2	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T45	12		T220	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	1		T43	2		T44	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T44	1		T132	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	4		T6	1		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	1		T41	2		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	1		T137	16		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	12		T4	1		T45	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T192	1		T156	12		T230	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	2		T142	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	13		T137	3		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	1		T133	2		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	25		T22	26		T30	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	3		T29	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T192	1		T139	2		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T3	1		T29	1		T250	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T225	16		T154	1		T248	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T5	1		T241	1		T180	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	7		T136	13		T12	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T241	9		T226	6		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	2		T200	9		T162	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1275	1			T1	8		T7	30		T42	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T45	6		T220	3		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T41	4		T44	2		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	13		T22	11		T141	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	10		T25	14		T162	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	15		T41	20		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	9		T156	13		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	3		T45	18		T25	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	1		T179	17		T155	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	8		T258	11		T169	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	11		T196	19		T184	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T4	1		T133	12		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	27		T22	26		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	2		T29	10		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T246	9		T151	12		T242	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T29	10		T250	12		T195	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T225	8		T248	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T241	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T280	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	11		T319	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T328	1		T306	1		T329	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T46	2		T180	1		T327	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	10		T136	15		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T6	1		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T168	1		T145	3		T162	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T112	1		T43	10		T137	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	15		T200	8		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T41	1		T44	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T44	1		T45	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	4		T6	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	1		T41	2		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T137	16		T29	1		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	12		T4	1		T45	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T192	1		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	2		T25	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	4		T44	13		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T4	1		T133	2		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T196	1		T22	17		T30	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	3		T3	1		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1416	1			T2	1		T7	3		T9	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T319	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T177	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	7		T136	13		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	10		T241	6		T226	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T145	2		T162	13		T239	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T43	3		T46	12		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T200	9		T227	4		T281	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	8		T41	4		T44	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T45	6		T132	13		T22	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	10		T25	14		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	15		T41	20		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	9		T156	13		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	3		T45	18		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T156	1		T152	11		T179	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	8		T25	9		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	11		T44	11		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T4	1		T133	12		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T196	19		T22	10		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	2		T29	20		T250	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1314	1			T7	30		T11	16		T42	38

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30