Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20835

1

T1

5

T2

1

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3265

1

T1

9

T4

20

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18221

1

T1

14

T4

2

T5

2

auto[1]

5879

1

T2

1

T3

17

T4

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	331	1			T45	18		T133	7		T30	45
values[0]	22	1			T31	14		T224	5		T298	1
values[1]	582	1			T6	1		T112	1		T137	3
values[2]	684	1			T1	5		T43	15		T26	11
values[3]	673	1			T5	1		T137	16		T25	15
values[4]	573	1			T4	2		T41	13		T44	1
values[5]	854	1			T6	1		T44	24		T46	2
values[6]	742	1			T4	4		T5	1		T6	1
values[7]	676	1			T1	9		T3	5		T4	16
values[8]	593	1			T192	1		T25	3		T152	19
values[9]	3153	1			T2	1		T3	12		T7	33
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	663	1			T6	1		T43	2		T46	12
values[1]	616	1			T1	5		T43	13		T137	16
values[2]	541	1			T5	1		T25	10		T29	10
values[3]	840	1			T4	2		T41	13		T44	1
values[4]	792	1			T4	4		T5	1		T6	2
values[5]	691	1			T1	9		T11	69		T44	7
values[6]	2939	1			T2	1		T3	5		T4	16
values[7]	518	1			T192	1		T136	28		T22	22
values[8]	907	1			T3	12		T45	18		T133	7
values[9]	193	1			T238	1		T143	21		T186	13
minimum	15400	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	6		T133	13		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T43	1		T22	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	3		T137	1		T25	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	4		T29	11		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T25	10		T29	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	11		T168	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T4	2		T41	5		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T41	8		T196	20		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T6	2		T44	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	4		T41	14		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	29		T44	3		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	9		T11	8		T45	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T2	1		T3	2		T7	33
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	16		T137	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T192	1		T136	14		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T22	12		T25	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T3	1		T133	3		T30	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	7		T142	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T143	13		T186	1		T194	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T238	1		T250	10		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15145	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T137	1		T141	3		T224	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	6		T133	1		T149	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T43	1		T22	24		T26	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	2		T137	15		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T43	9		T33	1		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T162	10		T249	4		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T152	12		T158	10		T247	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	1		T133	14		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	1		T250	10		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	12		T12	1		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T145	11		T200	7		T169	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	23		T44	4		T46	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	9		T45	17		T30	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T3	3		T9	22		T10	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T137	2		T162	11		T275	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	14		T152	7		T149	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T22	10		T139	1		T265	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	11		T133	4		T30	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T45	11		T151	13		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T143	8		T186	12		T308	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T250	12		T187	2		T179	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T31	13		T12	2		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T137	2		T141	10		T224	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T133	3		T30	23		T156	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T45	7		T142	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T31	1		T298	1		T331	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T224	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T112	1		T192	1		T46	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	1		T137	1		T22	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	3		T156	14		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	5		T26	1		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	1		T137	1		T25	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T152	11		T168	1		T33	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	2		T41	5		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	8		T196	20		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T44	12		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T200	10		T242	9		T169	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T6	1		T11	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	4		T11	8		T41	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	2		T44	9		T46	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	9		T4	16		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T192	1		T152	12		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T25	3		T168	1		T265	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T2	1		T3	1		T7	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	12		T139	1		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T133	4		T30	22		T156	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T45	11		T147	10		T187	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T31	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T224	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	6		T133	1		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T137	2		T22	24		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	2		T156	12		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T43	10		T26	10		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	15		T162	10		T249	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T152	12		T33	1		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T133	14		T229	4		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	11		T33	1		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	12		T46	1		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T200	7		T169	9		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	23		T44	4		T132	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T152	9		T141	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	3		T44	1		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	2		T45	17		T30	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T152	7		T33	1		T226	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T265	7		T281	11		T248	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T3	11		T9	22		T10	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	10		T139	1		T151	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	7		T133	2		T149	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T43	2		T22	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	3		T137	16		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	10		T29	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	1		T25	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T152	13		T168	1		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	1		T41	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	1		T196	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T6	2		T44	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	1		T41	1		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	25		T44	5		T46	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T11	10		T45	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	1		T3	5		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	1		T137	3		T162	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T192	1		T136	15		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	11		T25	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T3	12		T133	5		T30	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T45	12		T142	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T143	9		T186	13		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T238	1		T250	13		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15265	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T137	3		T141	11		T224	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T46	5		T133	12		T295	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	26		T184	15		T178	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	2		T25	14		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T43	3		T29	10		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	9		T29	9		T162	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T152	10		T247	4		T222	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	1		T41	4		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	7		T196	19		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T44	11		T12	1		T237	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	3		T41	13		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	27		T44	2		T46	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	8		T11	7		T45	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T7	30		T42	38		T44	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	15		T162	13		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T136	13		T152	11		T226	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T22	11		T25	2		T265	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T133	2		T30	21		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	6		T151	12		T235	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T143	12		T194	11		T109	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T250	9		T179	2		T248	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T332	14		T182	9		T333	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T141	2		T222	8		T334	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T133	5		T30	24		T156	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T45	12		T142	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T31	14		T298	1		T331	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T224	5		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T112	1		T192	1		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T137	3		T22	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T156	13		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	12		T26	11		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T137	16		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T152	13		T168	1		T33	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	1		T41	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	1		T196	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T6	1		T44	13		T46	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T200	8		T242	1		T169	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T6	1		T11	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T11	10		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	5		T44	2		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T4	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T192	1		T152	8		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	1		T168	1		T265	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T2	1		T3	12		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	11		T139	2		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T133	2		T30	21		T156	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T45	6		T179	2		T266	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T46	5		T133	12		T295	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T22	26		T184	15		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	2		T156	13		T154	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	3		T29	10		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	14		T29	9		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	10		T33	1		T247	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	1		T41	4		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	7		T196	19		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	11		T220	3		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T200	9		T242	8		T169	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	27		T44	2		T132	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	3		T11	7		T41	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	8		T46	12		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	8		T4	15		T45	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	11		T226	6		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T25	2		T265	7		T281	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T7	30		T42	38		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	11		T151	12		T250	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30