Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18230

1

T1

5

T3

13

T4

22

auto[ADC_CTRL_FILTER_COND_OUT]

5870

1

T1

9

T2

1

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18012

1

T4

4

T5

2

T6

2

auto[1]

6088

1

T1

14

T2

1

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	135	1			T29	11		T151	26		T154	1
values[0]	30	1			T46	2		T177	23		T329	5
values[1]	699	1			T5	1		T6	1		T11	17
values[2]	605	1			T1	9		T112	1		T43	13
values[3]	535	1			T41	5		T44	7		T133	7
values[4]	783	1			T3	4		T6	2		T43	2
values[5]	742	1			T4	16		T41	22		T137	16
values[6]	875	1			T3	12		T4	4		T5	1
values[7]	788	1			T44	34		T137	3		T22	25
values[8]	523	1			T4	2		T11	15		T196	20
values[9]	3168	1			T1	5		T2	1		T3	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	710	1			T6	1		T11	17		T112	1
values[1]	2963	1			T1	9		T2	1		T7	33
values[2]	571	1			T41	5		T43	2		T44	7
values[3]	635	1			T3	4		T6	2		T44	1
values[4]	835	1			T4	16		T5	1		T41	22
values[5]	864	1			T3	12		T4	4		T45	36
values[6]	741	1			T4	2		T44	34		T137	3
values[7]	565	1			T11	52		T133	14		T197	5
values[8]	751	1			T1	5		T192	1		T29	22
values[9]	86	1			T3	1		T225	24		T250	23
minimum	15379	1			T5	1		T8	20		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	8		T136	14		T27	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	1		T112	1		T241	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T168	1		T149	1		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1619	1			T1	9		T2	1		T7	33
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T45	7		T249	1		T221	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	5		T43	1		T44	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T44	1		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T6	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	16		T41	22		T46	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T137	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	1		T4	4		T45	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T192	1		T156	2		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	2		T44	9		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T44	12		T137	1		T196	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T133	13		T197	5		T178	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	29		T30	11		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	3		T29	22		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T192	1		T139	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T3	1		T250	13		T335	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T225	9		T248	14		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15124	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T5	1		T46	1		T84	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	9		T136	14		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T226	9		T147	10		T186	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T149	14		T145	2		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1028	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T45	11		T221	15		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	1		T44	4		T133	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T132	12		T22	10		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	3		T31	13		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	6		T156	2		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T137	15		T156	12		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	11		T45	17		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T156	11		T230	1		T153	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T44	1		T151	2		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T44	12		T137	2		T22	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T133	1		T178	10		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	23		T30	14		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	2		T158	10		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T139	1		T151	13		T179	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T250	10		T284	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T225	15		T248	10		T296	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	3		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T46	1		T336	18		T284	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T29	11		T281	10		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T151	13		T154	1		T248	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T329	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T46	1		T177	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	8		T136	14		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T6	1		T241	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T168	1		T145	3		T162	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	9		T112	1		T43	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T149	1		T200	10		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	5		T44	3		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	1		T44	1		T45	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T6	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	16		T41	22		T46	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T137	1		T29	10		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T4	4		T45	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T192	1		T156	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T44	9		T25	10		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T44	12		T137	1		T22	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T4	2		T197	5		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	12		T196	20		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T1	3		T3	1		T133	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1637	1			T2	1		T7	33		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T281	11		T280	11		T308	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T151	13		T248	10		T308	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T329	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T46	1		T177	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	9		T136	14		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T226	9		T147	10		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T145	2		T162	11		T148	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	9		T137	2		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T149	14		T200	7		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T44	4		T133	4		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	11		T132	12		T22	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	3		T43	1		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	6		T156	2		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	15		T156	12		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	11		T45	17		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	11		T152	9		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T44	1		T141	10		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T44	12		T137	2		T22	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T178	10		T170	12		T337	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	3		T22	16		T30	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	2		T133	1		T250	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1042	1			T9	22		T10	25		T11	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	10		T136	15		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	1		T112	1		T241	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T168	1		T149	15		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1362	1			T1	1		T2	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	12		T249	1		T221	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	1		T43	2		T44	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T44	1		T132	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T6	1		T31	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T41	2		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	1		T137	16		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	12		T4	1		T45	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T192	1		T156	12		T230	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T44	2		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	13		T137	3		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T133	2		T197	1		T178	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	25		T30	15		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	3		T29	2		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T192	1		T139	2		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T3	1		T250	11		T335	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T225	16		T248	11		T296	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15244	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T5	1		T46	2		T84	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	7		T136	13		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T241	15		T226	6		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T145	2		T200	9		T162	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1285	1			T1	8		T7	30		T42	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T45	6		T221	14		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T41	4		T44	2		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T132	13		T22	11		T220	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	14		T162	17		T249	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	15		T41	20		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	9		T156	13		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	3		T45	18		T25	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T156	1		T179	17		T222	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	1		T44	8		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T44	11		T196	19		T22	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T133	12		T197	4		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	27		T30	10		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	2		T29	20		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T246	9		T151	12		T242	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T250	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T225	8		T248	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T12	1		T96	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T84	15		T291	2		T338	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T29	1		T281	12		T280	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T151	14		T154	1		T248	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T329	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T46	2		T177	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	10		T136	15		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T6	1		T241	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T168	1		T145	3		T162	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T112	1		T43	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	15		T200	8		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	1		T44	5		T133	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T44	1		T45	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	4		T6	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	1		T41	2		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T137	16		T29	1		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	12		T4	1		T45	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T192	1		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	2		T25	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	13		T137	3		T22	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T4	1		T197	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	4		T196	1		T22	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	3		T3	1		T133	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1384	1			T2	1		T7	3		T9	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T29	10		T281	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T151	12		T248	13		T339	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T177	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	7		T136	13		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T241	15		T226	6		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	2		T162	13		T239	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	8		T43	3		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T200	9		T227	4		T281	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	4		T44	2		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T45	6		T132	13		T22	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T133	10		T25	14		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	15		T41	20		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	9		T156	13		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	3		T45	18		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T156	1		T152	11		T179	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	8		T25	9		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	11		T22	16		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T4	1		T197	4		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	11		T196	19		T22	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	2		T133	12		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1295	1			T7	30		T11	16		T42	38

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30