Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20717

1

T1

14

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3383

1

T3

1

T4

22

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18386

1

T1

9

T3

12

T4

4

auto[1]

5714

1

T1

5

T2

1

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	50	1			T243	12		T266	28		T21	4
values[0]	62	1			T25	15		T340	16		T341	25
values[1]	537	1			T43	2		T44	7		T46	2
values[2]	2981	1			T2	1		T7	33		T9	25
values[3]	582	1			T3	13		T4	4		T41	5
values[4]	706	1			T41	14		T133	7		T139	2
values[5]	728	1			T6	1		T11	37		T45	18
values[6]	547	1			T4	16		T44	34		T31	14
values[7]	752	1			T3	4		T4	2		T6	1
values[8]	745	1			T1	5		T5	1		T41	8
values[9]	1193	1			T1	9		T5	1		T6	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T112	1		T43	2		T44	7
values[1]	2868	1			T2	1		T3	1		T4	4
values[2]	655	1			T3	12		T41	5		T22	27
values[3]	702	1			T11	37		T133	7		T139	2
values[4]	711	1			T4	16		T6	1		T41	14
values[5]	618	1			T44	34		T192	1		T25	3
values[6]	654	1			T3	4		T4	2		T6	1
values[7]	898	1			T1	5		T5	1		T6	1
values[8]	778	1			T1	9		T5	1		T137	16
values[9]	175	1			T146	1		T153	10		T249	1
minimum	15286	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	3		T46	1		T156	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T112	1		T43	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	1		T7	33		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T4	4		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T22	11		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	5		T30	11		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	17		T133	3		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T145	10		T249	3		T250	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T41	14		T45	7		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	16		T6	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	21		T192	1		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	3		T156	14		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T11	12		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	2		T6	1		T43	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	3		T27	3		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	1		T6	1		T11	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	9		T5	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T192	1		T46	6		T196	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T146	1		T249	1		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T153	1		T243	10		T251	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15119	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T286	6		T96	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	4		T46	1		T156	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T43	1		T12	1		T237	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T9	22		T10	25		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	12		T22	8		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	11		T22	16		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T30	10		T152	12		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	20		T133	4		T139	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	9		T249	4		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	11		T133	14		T30	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T31	13		T250	12		T343	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	13		T152	9		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T156	12		T149	16		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	3		T11	3		T137	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T43	9		T45	17		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	2		T151	13		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	9		T22	10		T30	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	15		T136	14		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	6		T152	7		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T330	12		T254	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T153	9		T243	2		T251	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T96	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T21	2		T174	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T243	10		T266	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T340	1		T341	12		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T25	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T44	3		T46	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	1		T12	3		T241	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	1		T7	33		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T112	1		T132	14		T22	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T44	1		T197	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T4	4		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	14		T133	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	11		T145	10		T250	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	17		T45	7		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T144	1		T250	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T44	21		T138	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T4	16		T31	1		T25	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T11	12		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	2		T6	1		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	3		T41	8		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T43	4		T22	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T1	9		T5	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T6	1		T11	8		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T21	2		T174	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T243	2		T266	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T340	15		T341	13		T327	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	4		T46	1		T230	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	1		T12	1		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	12		T22	8		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	11		T22	16		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T30	10		T249	4		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T133	4		T139	1		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T152	12		T145	9		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	20		T45	11		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T250	12		T179	2		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	13		T152	9		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T31	13		T149	2		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	3		T11	3		T133	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T45	17		T46	3		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	2		T137	4		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T43	9		T22	10		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T137	15		T136	14		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	9		T46	6		T156	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	5		T46	2		T156	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T112	1		T43	2		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T2	1		T7	3		T9	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T4	1		T132	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	12		T22	17		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	1		T30	11		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	21		T133	5		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T145	10		T249	5		T250	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T41	1		T45	12		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	1		T6	1		T31	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	15		T192	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T25	1		T156	13		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	4		T11	4		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T6	1		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	3		T27	2		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	1		T6	1		T11	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T5	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T192	1		T46	7		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T146	1		T249	1		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T153	10		T243	3		T251	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15250	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T286	1		T96	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	2		T156	11		T241	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T25	14		T241	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T7	30		T42	38		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	3		T132	13		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T22	10		T162	17		T84	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	4		T30	10		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	16		T133	2		T145	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	9		T249	2		T250	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	13		T45	6		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T4	15		T250	9		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T44	19		T152	11		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	2		T156	13		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	11		T41	7		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T4	1		T43	3		T45	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	2		T27	1		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	7		T22	11		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	8		T136	13		T25	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	5		T196	19		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T85	12		T172	7		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T243	9		T251	15		T291	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T286	5		T96	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T21	3		T174	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T243	3		T266	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T340	16		T341	14		T327	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T25	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	5		T46	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	2		T12	3		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	1		T7	3		T9	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T112	1		T132	13		T22	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	12		T44	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	1		T4	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T41	1		T133	5		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	13		T145	10		T250	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	21		T45	12		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T144	1		T250	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T44	15		T138	1		T152	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T4	1		T31	14		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	4		T11	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T6	1		T45	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	3		T41	1		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T43	10		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T1	1		T5	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T6	1		T11	10		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T21	1		T174	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T243	9		T266	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T341	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T25	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T44	2		T258	3		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	1		T241	6		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T7	30		T42	38		T24	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T132	13		T22	16		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T197	4		T22	10		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T4	3		T41	4		T30	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	13		T133	2		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T152	10		T145	9		T250	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	16		T45	6		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T250	9		T179	7		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	19		T152	11		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T4	15		T25	2		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	11		T133	12		T195	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T45	18		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	2		T41	7		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	3		T22	11		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	8		T136	13		T25	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T11	7		T46	5		T196	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30