Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20762

1

T1

5

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3338

1

T1

9

T3

1

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18125

1

T1

14

T3

5

T4

18

auto[1]

5975

1

T2

1

T3

12

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	186	1			T1	9		T6	1		T146	1
values[0]	59	1			T33	5		T242	18		T171	7
values[1]	565	1			T3	12		T4	4		T196	20
values[2]	666	1			T3	1		T4	2		T11	52
values[3]	597	1			T43	13		T45	36		T192	1
values[4]	3039	1			T2	1		T4	16		T7	33
values[5]	596	1			T6	1		T137	3		T45	18
values[6]	722	1			T1	5		T44	11		T192	1
values[7]	593	1			T5	1		T112	1		T43	2
values[8]	737	1			T41	5		T44	7		T136	28
values[9]	1123	1			T3	4		T5	1		T6	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	536	1			T3	13		T4	4		T41	8
values[1]	673	1			T4	2		T11	52		T137	3
values[2]	622	1			T43	13		T132	26		T25	10
values[3]	3030	1			T2	1		T4	16		T6	1
values[4]	655	1			T44	1		T45	18		T133	25
values[5]	635	1			T1	5		T43	2		T44	34
values[6]	734	1			T5	1		T112	1		T46	2
values[7]	641	1			T6	1		T41	5		T44	7
values[8]	1008	1			T3	4		T5	1		T6	1
values[9]	108	1			T1	9		T146	1		T151	11
minimum	15458	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	1		T4	4		T141	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T41	8		T196	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	12		T137	1		T25	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	2		T11	17		T45	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	4		T132	14		T25	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	1		T167	1		T258	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T2	1		T4	16		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T41	14		T133	3		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	7		T149	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T44	1		T133	11		T22	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	3		T133	13		T30	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	1		T44	21		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T112	1		T25	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T46	1		T136	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T41	5		T44	3		T22	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T31	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	1		T5	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T22	11		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T146	1		T151	9		T229	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T1	9		T85	7		T283	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15195	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T224	1		T35	2		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	11		T141	19		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T156	12		T145	9		T226	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	3		T137	2		T26	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	20		T45	17		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	9		T132	12		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T250	10		T251	13		T304	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T9	22		T10	25		T11	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	4		T33	1		T225	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T45	11		T149	14		T162	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T133	14		T22	10		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	2		T133	1		T30	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T43	1		T44	13		T224	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T148	11		T250	12		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	1		T136	14		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T44	4		T22	8		T281	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	13		T12	1		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	3		T137	15		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T22	16		T152	7		T237	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	2		T229	14		T282	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T33	8		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T224	5		T247	13		T284	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T146	1		T151	9		T229	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T1	9		T6	1		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T33	4		T171	1		T273	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T242	18		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T4	4		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T196	20		T156	14		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	12		T137	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T4	2		T11	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	4		T132	14		T25	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	19		T192	1		T156	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1711	1			T2	1		T4	16		T7	33
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	14		T33	1		T240	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	1		T137	1		T45	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	14		T225	9		T84	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	3		T133	13		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	10		T192	1		T22	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T112	1		T25	3		T30	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T43	1		T44	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T41	5		T44	3		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T136	14		T31	1		T143	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	1		T5	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T6	1		T12	3		T22	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T151	2		T229	14		T281	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	2		T325	6		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T33	1		T171	6		T273	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T284	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	11		T141	19		T179	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T156	12		T153	9		T187	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	3		T137	2		T26	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	20		T145	9		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T43	9		T132	12		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	17		T156	11		T269	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T9	22		T10	25		T11	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	1		T250	10		T169	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T137	2		T45	11		T46	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T133	18		T225	15		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T133	1		T30	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T44	1		T22	10		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	14		T148	11		T250	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T43	1		T44	12		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T44	4		T248	10		T302	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T136	14		T31	13		T143	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	3		T137	15		T22	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	1		T22	16		T152	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	12		T4	1		T141	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T41	1		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	4		T137	3		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	1		T11	21		T45	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T43	10		T132	13		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T144	1		T167	1		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T2	1		T4	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	1		T133	5		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T45	12		T149	15		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	1		T133	15		T22	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	3		T133	2		T30	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	2		T44	15		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T112	1		T25	1		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T46	2		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T41	1		T44	5		T22	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T31	14		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	4		T5	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	1		T22	17		T152	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T146	1		T151	3		T229	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T1	1		T85	1		T283	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15320	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T224	6		T35	2		T247	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T4	3		T141	15		T241	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	7		T196	19		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	11		T25	14		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	1		T11	16		T45	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	3		T132	13		T25	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T258	8		T250	12		T251	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T4	15		T7	30		T11	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	13		T133	2		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	6		T162	13		T155	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T133	10		T22	11		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	2		T133	12		T30	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T44	19		T242	14		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	2		T250	9		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T136	13		T30	10		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	4		T44	2		T22	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T152	10		T143	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T197	4		T178	10		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T22	10		T152	11		T237	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T151	8		T229	15		T282	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T1	8		T85	6		T283	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T33	1		T179	7		T344	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T247	9		T316	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T146	1		T151	3		T229	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T1	1		T6	1		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T33	4		T171	7		T273	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T242	1		T284	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	12		T4	1		T141	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T196	1		T156	13		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	4		T137	3		T26	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T4	1		T11	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	10		T132	13		T25	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	18		T192	1		T156	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	1		T4	1		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	1		T33	2		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	1		T137	3		T45	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T133	20		T225	16		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	3		T133	2		T30	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T44	3		T192	1		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T112	1		T25	1		T30	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T43	2		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T41	1		T44	5		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T136	15		T31	14		T143	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	4		T5	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T6	1		T12	3		T22	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T151	8		T229	15		T194	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T1	8		T85	6		T325	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T33	1		T273	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	3		T141	15		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T196	19		T156	13		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	11		T29	9		T220	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T11	16		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T43	3		T132	13		T25	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	18		T156	1		T258	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T4	15		T7	30		T11	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T41	13		T240	8		T250	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T45	6		T46	5		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T133	12		T225	8		T84	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	2		T133	12		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	8		T22	11		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T25	2		T30	10		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T44	11		T30	10		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T41	4		T44	2		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	13		T143	22		T200	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T197	4		T22	16		T178	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	1		T22	10		T152	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30