Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	2		T156	3		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T112	1		T43	2		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T2	1		T3	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T132	13		T22	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	12		T22	17		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	1		T30	11		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	21		T133	5		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T145	10		T249	5		T250	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	1		T45	12		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T6	1		T31	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	15		T192	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	1		T167	1		T149	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	4		T11	4		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T4	1		T6	1		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	3		T33	2		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	1		T6	1		T11	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T5	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T192	1		T46	7		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T146	1		T85	1		T248	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T251	14		T252	1		T253	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15311	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T12	3		T226	11		T234	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T156	11		T258	3		T87	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T25	14		T241	6		T228	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T7	30		T42	38		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	3		T132	13		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	10		T162	17		T194	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	4		T30	10		T184	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	16		T133	2		T145	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T145	9		T249	2		T250	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	13		T45	6		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	15		T250	9		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	19		T152	11		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T25	2		T145	12		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	11		T41	7		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	1		T43	3		T45	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T151	12		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	7		T22	11		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	8		T136	13		T25	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T46	5		T196	19		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T85	12		T248	11		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T251	15		T253	10		T255	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T44	2		T189	2		T259	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T12	1		T234	15		T222	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T146	1		T226	10		T229	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T196	1		T29	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	5		T46	2		T156	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	2		T12	3		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T2	1		T7	3		T9	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T112	1		T132	13		T22	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	13		T197	1		T22	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T41	1		T30	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	21		T133	5		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T152	13		T145	10		T250	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	1		T45	12		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T6	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	15		T192	1		T133	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	14		T25	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	4		T11	4		T133	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T6	1		T45	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	3		T41	1		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T43	10		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T5	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T6	1		T11	10		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T226	6		T229	2		T85	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T196	19		T29	9		T239	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	2		T156	11		T258	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T25	14		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T7	30		T42	38		T24	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	13		T22	16		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T197	4		T22	10		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	3		T41	4		T30	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	16		T133	2		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	10		T145	9		T250	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	13		T45	6		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	15		T250	9		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	19		T133	10		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T25	2		T145	12		T179	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	11		T133	12		T141	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T45	18		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T41	7		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	3		T22	11		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	8		T136	13		T25	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	7		T46	5		T156	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30