Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20665

1

T1

5

T2

1

T3

5

auto[ADC_CTRL_FILTER_COND_OUT]

3435

1

T1

9

T3

12

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18127

1

T1

5

T3

17

T4

6

auto[1]

5973

1

T1

9

T2

1

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T260	17		-	-		-	-
values[0]	54	1			T146	1		T221	1		T170	16
values[1]	606	1			T1	9		T6	1		T11	15
values[2]	618	1			T6	1		T11	37		T46	2
values[3]	674	1			T4	20		T5	1		T41	5
values[4]	875	1			T137	19		T156	26		T152	23
values[5]	665	1			T3	12		T41	8		T192	1
values[6]	747	1			T1	5		T5	1		T11	17
values[7]	700	1			T3	4		T41	14		T44	7
values[8]	2744	1			T2	1		T6	1		T7	33
values[9]	1183	1			T3	1		T4	2		T112	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	804	1			T1	9		T6	1		T11	15
values[1]	632	1			T4	16		T5	1		T6	1
values[2]	719	1			T4	4		T41	5		T137	3
values[3]	789	1			T137	16		T192	1		T156	40
values[4]	763	1			T41	8		T137	3		T46	12
values[5]	695	1			T1	5		T3	16		T5	1
values[6]	2917	1			T2	1		T7	33		T9	25
values[7]	476	1			T6	1		T112	1		T44	10
values[8]	807	1			T3	1		T4	2		T44	1
values[9]	273	1			T43	13		T220	4		T140	1
minimum	15225	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T11	12		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	9		T133	13		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	16		T11	17		T132	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T6	1		T22	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	4		T46	1		T145	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	5		T137	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T137	1		T192	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T156	26		T167	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T137	1		T46	6		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	8		T12	3		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	3		T3	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T44	12		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T2	1		T7	33		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	14		T43	1		T44	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T112	1		T25	10		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T6	1		T44	9		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T44	1		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	2		T46	13		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T43	4		T220	4		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T200	10		T179	18		T223	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	3		T139	1		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	1		T136	14		T30	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	20		T132	12		T237	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	24		T33	1		T225	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	1		T145	2		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	2		T26	10		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	15		T152	12		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T156	14		T148	11		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T137	2		T46	6		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	1		T141	19		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	2		T3	3		T11	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	11		T44	12		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T9	22		T10	25		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	1		T44	4		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T143	8		T149	5		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T44	1		T231	8		T262	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T45	17		T30	10		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	3		T133	14		T31	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T43	9		T141	10		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T200	7		T179	10		T172	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T260	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T170	1		T263	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T146	1		T221	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T11	12		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	9		T133	13		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	17		T46	1		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	1		T22	28		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	20		T168	1		T145	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T41	5		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	1		T152	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T137	1		T156	14		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T192	1		T46	6		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T41	8		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	3		T5	1		T11	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	12		T12	3		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	1		T45	7		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	14		T44	3		T133	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	1		T7	33		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	1		T43	1		T44	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T3	1		T112	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T4	2		T46	13		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T170	15		T263	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T247	2		T264	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T11	3		T239	2		T227	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T133	1		T136	14		T30	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	20		T46	1		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	24		T33	1		T225	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T145	2		T237	15		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T26	10		T149	2		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	15		T152	12		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T137	2		T156	12		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	6		T33	1		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	11		T156	2		T141	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	2		T11	9		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	12		T12	1		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	3		T45	11		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	4		T133	4		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T9	22		T10	25		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T43	1		T44	1		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T43	9		T45	17		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T46	3		T133	14		T31	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T11	4		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T133	2		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	1		T11	21		T132	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T6	1		T22	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	1		T46	2		T145	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T41	1		T137	3		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	16		T192	1		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T156	16		T167	1		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T137	3		T46	7		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	1		T12	3		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	3		T3	4		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	12		T44	13		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	1		T7	3		T9	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	1		T43	2		T44	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T112	1		T25	1		T143	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	1		T44	2		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	1		T44	1		T45	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T4	1		T46	4		T133	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T43	10		T220	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T200	8		T179	11		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	11		T25	2		T151	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	8		T133	12		T136	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	15		T11	16		T132	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T22	26		T29	9		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	3		T145	2		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	4		T246	9		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T152	10		T33	1		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T156	24		T242	6		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	5		T243	4		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	7		T12	1		T141	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	2		T11	7		T29	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	11		T27	1		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T7	30		T42	38		T45	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	13		T44	2		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	9		T143	12		T194	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T44	8		T25	14		T265	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T45	18		T196	19		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	1		T46	12		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T43	3		T220	3		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T200	9		T179	17		T223	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T170	16		T263	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T146	1		T221	1		T247	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	1		T11	4		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T133	2		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	21		T46	2		T132	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T22	26		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	2		T168	1		T145	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T41	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T137	16		T152	13		T149	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T137	3		T156	13		T151	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T192	1		T46	7		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	12		T41	1		T156	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T5	1		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T44	13		T12	3		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	4		T45	12		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	1		T44	5		T133	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T2	1		T7	3		T9	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T43	2		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T3	1		T112	1		T43	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T4	1		T46	4		T133	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T260	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T264	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T11	11		T25	2		T239	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	8		T133	12		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	16		T132	13		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T22	26		T29	9		T241	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	18		T145	2		T237	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	4		T246	9		T221	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	10		T241	9		T162	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	13		T151	12		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	5		T29	10		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	7		T156	11		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	2		T11	7		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	11		T12	1		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	6		T29	10		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	13		T44	2		T133	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T7	30		T42	38		T196	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	8		T25	14		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T43	3		T45	18		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T4	1		T46	12		T133	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30