Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20790

1

T1

5

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3310

1

T1

9

T3

1

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18097

1

T1

14

T3

5

T4

18

auto[1]

6003

1

T2

1

T3

12

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T85	7		T278	1		-	-
values[0]	25	1			T224	6		T279	2		T280	12
values[1]	572	1			T3	12		T4	4		T196	20
values[2]	734	1			T3	1		T4	2		T11	52
values[3]	590	1			T43	13		T45	36		T192	1
values[4]	3011	1			T2	1		T4	16		T6	1
values[5]	545	1			T137	3		T45	18		T46	12
values[6]	833	1			T1	5		T44	11		T192	1
values[7]	482	1			T5	1		T112	1		T43	2
values[8]	832	1			T41	5		T44	7		T136	28
values[9]	1251	1			T1	9		T3	4		T5	1
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	861	1			T3	13		T4	4		T11	52
values[1]	561	1			T137	3		T45	36		T192	1
values[2]	727	1			T4	2		T43	13		T132	26
values[3]	2964	1			T2	1		T4	16		T6	1
values[4]	631	1			T44	1		T45	18		T133	39
values[5]	626	1			T1	5		T43	2		T44	34
values[6]	747	1			T5	1		T112	1		T46	2
values[7]	687	1			T6	1		T41	5		T44	7
values[8]	951	1			T3	4		T5	1		T6	1
values[9]	122	1			T1	9		T146	1		T151	11
minimum	15223	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T4	4		T11	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	1		T11	17		T41	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T137	1		T25	15		T27	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	19		T192	1		T156	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T43	4		T132	14		T25	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	2		T144	1		T258	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1644	1			T2	1		T4	16		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	14		T133	3		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	7		T133	13		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	1		T133	11		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	3		T30	23		T156	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	1		T44	21		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T112	1		T148	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T46	1		T136	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	5		T44	3		T22	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T31	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	1		T5	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T152	12		T237	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T146	1		T151	9		T229	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T1	9		T275	1		T85	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	11		T11	3		T26	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	20		T156	12		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T137	2		T149	2		T186	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	17		T156	11		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T43	9		T132	12		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T250	10		T164	9		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T9	22		T10	25		T11	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T133	4		T33	1		T225	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	11		T133	1		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	14		T141	10		T265	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	2		T30	26		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T44	13		T22	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T148	11		T250	12		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T46	1		T136	14		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T44	4		T22	8		T281	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	13		T12	1		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	3		T137	15		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T152	7		T237	15		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	2		T229	14		T282	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T275	5		T283	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T224	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T278	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T85	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T279	1		T280	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T224	1		T284	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T4	4		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T196	20		T138	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	12		T137	1		T29	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T4	2		T11	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T43	4		T132	14		T25	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	19		T192	1		T156	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T2	1		T4	16		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	14		T240	9		T258	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T137	1		T45	7		T46	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	14		T167	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T1	3		T133	13		T30	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	10		T192	1		T22	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T112	1		T25	3		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T43	1		T44	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T41	5		T44	3		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T136	14		T31	1		T152	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T3	1		T5	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T1	9		T6	2		T12	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	1		T280	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T224	5		T284	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	11		T26	10		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T153	9		T187	2		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	3		T137	2		T186	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	20		T156	12		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	9		T132	12		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T45	17		T156	11		T269	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T9	22		T10	25		T11	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T250	10		T169	9		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	2		T45	11		T46	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	18		T33	1		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T133	1		T30	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	1		T22	10		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T148	11		T250	12		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	1		T44	12		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	4		T228	7		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T136	14		T31	13		T152	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	3		T137	15		T22	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T12	1		T22	16		T152	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	12		T4	1		T11	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T11	21		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T137	3		T25	1		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	18		T192	1		T156	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T43	10		T132	13		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	1		T144	1		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	1		T4	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	1		T133	5		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T45	12		T133	2		T149	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T44	1		T133	15		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T30	28		T156	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	2		T44	15		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T112	1		T148	12		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T46	2		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	1		T44	5		T22	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T31	14		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	4		T5	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T152	8		T237	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T146	1		T151	3		T229	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T1	1		T275	6		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T224	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	3		T11	11		T141	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	16		T41	7		T196	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T25	14		T27	1		T29	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	18		T156	1		T250	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T43	3		T132	13		T25	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	1		T258	8		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T4	15		T7	30		T11	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	13		T133	2		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T45	6		T133	12		T162	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T133	10		T29	10		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	2		T30	21		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	19		T22	11		T242	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T250	9		T228	6		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	13		T30	10		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T41	4		T44	2		T22	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T22	10		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T197	4		T178	10		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T152	11		T237	3		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T151	8		T229	15		T286	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T1	8		T85	6		T283	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T278	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T85	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T279	2		T280	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T224	6		T284	4		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	12		T4	1		T26	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T196	1		T138	1		T153	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	4		T137	3		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T4	1		T11	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T43	10		T132	13		T25	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	18		T192	1		T156	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T2	1		T4	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T41	1		T240	1		T258	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	3		T45	12		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	20		T167	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	3		T133	2		T30	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	3		T192	1		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	1		T25	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T43	2		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	1		T44	5		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T136	15		T31	14		T152	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T3	4		T5	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T1	1		T6	2		T12	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T85	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	3		T141	15		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T196	19		T242	17		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	11		T29	9		T220	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	1		T11	16		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	3		T132	13		T25	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T45	18		T156	1		T251	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T4	15		T7	30		T11	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	13		T240	8		T258	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T45	6		T46	5		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T133	12		T225	8		T84	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	2		T133	12		T30	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	8		T22	11		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T25	2		T250	9		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T44	11		T30	10		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	4		T44	2		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	13		T152	10		T143	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T197	4		T22	16		T178	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	8		T12	1		T22	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30