Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20746

1

T2

1

T4

2

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3354

1

T1

14

T3

17

T4

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18026

1

T1

9

T3

17

T4

6

auto[1]

6074

1

T1

5

T2

1

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	541	1			T48	6		T43	2		T50	3
values[0]	1	1			T187	1		-	-		-	-
values[1]	775	1			T3	4		T11	15		T46	2
values[2]	2894	1			T2	1		T4	2		T6	2
values[3]	706	1			T1	9		T5	1		T11	17
values[4]	600	1			T3	12		T6	1		T137	16
values[5]	802	1			T1	5		T41	22		T45	18
values[6]	588	1			T112	1		T45	36		T46	12
values[7]	704	1			T4	16		T196	20		T26	11
values[8]	811	1			T3	1		T5	1		T11	37
values[9]	827	1			T4	4		T41	5		T44	17
minimum	14851	1			T8	20		T47	18		T48	174

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	688	1			T3	4		T4	2		T43	2
values[1]	2941	1			T2	1		T6	2		T7	33
values[2]	705	1			T1	9		T3	12		T5	1
values[3]	563	1			T6	1		T41	14		T137	16
values[4]	887	1			T1	5		T41	8		T45	54
values[5]	626	1			T4	16		T112	1		T46	12
values[6]	551	1			T26	11		T29	11		T30	21
values[7]	910	1			T5	1		T43	13		T44	11
values[8]	717	1			T3	1		T4	4		T11	37
values[9]	68	1			T249	1		T287	3		T278	1
minimum	15444	1			T8	20		T11	15		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	2		T22	17		T29	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T43	1		T22	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T2	1		T6	2		T7	33
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T44	12		T136	14		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	1		T11	8		T25	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	9		T3	1		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T132	14		T12	3		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T41	14		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T41	8		T45	7		T25	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	3		T45	19		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T46	6		T27	3		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	16		T112	1		T196	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T29	11		T142	1		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	1		T30	11		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T44	10		T30	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T43	4		T46	13		T133	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T41	5		T44	3		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T4	4		T11	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T284	1		T111	2		T260	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T249	1		T287	2		T278	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15154	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T11	12		T187	1		T288	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	8		T152	12		T149	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	3		T43	1		T22	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T9	22		T10	25		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	12		T136	14		T30	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	9		T145	11		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	11		T133	1		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	12		T12	1		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T137	15		T226	10		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T45	11		T178	10		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	2		T45	17		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	6		T152	9		T230	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T22	16		T145	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T143	12		T179	3		T87	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T26	10		T30	10		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	1		T30	12		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T43	9		T46	3		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T44	4		T186	12		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	20		T137	4		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T284	2		T111	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T287	1		T289	5		T93	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	1		T12	2		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T11	3		T288	15		T290	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T48	6		T43	2		T50	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T142	1		T258	4		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T187	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	1		T29	10		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	1		T11	12		T22	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T2	1		T4	2		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T43	1		T136	14		T30	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T11	8		T25	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	9		T44	12		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	14		T12	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T6	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T41	8		T45	7		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	3		T41	14		T25	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	6		T25	3		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T112	1		T45	19		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T142	1		T143	11		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	16		T196	20		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T44	1		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T11	17		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	5		T44	12		T197	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	4		T137	2		T133	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14737	1			T8	20		T47	18		T48	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T169	9		T170	15		T291	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T292	1		T293	14		T289	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T46	1		T152	12		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	3		T11	3		T22	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T9	22		T10	25		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	1		T136	14		T30	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	9		T139	1		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T44	12		T133	1		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T132	12		T12	1		T145	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	11		T137	15		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T45	11		T178	10		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	2		T226	10		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T46	6		T152	9		T275	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	17		T133	14		T22	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	12		T230	1		T249	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	10		T30	10		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	12		T156	2		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	20		T43	9		T46	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	5		T186	12		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T137	4		T133	4		T156	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T22	9		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	4		T43	2		T22	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T2	1		T6	2		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	13		T136	15		T30	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	1		T11	10		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T3	12		T133	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	13		T12	3		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	1		T41	1		T137	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T41	1		T45	12		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	3		T45	18		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	7		T27	2		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	1		T112	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	1		T142	1		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	11		T30	11		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T44	3		T30	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T43	10		T46	4		T133	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	1		T44	5		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T4	1		T11	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T284	3		T111	2		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T249	1		T287	3		T278	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15280	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T11	4		T187	1		T288	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T22	16		T29	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T22	11		T143	12		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T7	30		T42	38		T24	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	11		T136	13		T30	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	7		T25	9		T145	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T1	8		T133	12		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	13		T12	1		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	13		T220	3		T242	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	7		T45	6		T25	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	2		T45	18		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	5		T27	1		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	15		T196	19		T22	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	10		T143	10		T258	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	10		T151	14		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	8		T30	11		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	3		T46	12		T133	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	4		T44	2		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	3		T11	16		T184	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T111	1		T260	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T289	5		T253	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T174	10		T111	8		T294	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T11	11		T288	15		T290	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	429	1			T48	6		T43	2		T50	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T142	1		T258	1		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T187	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T46	2		T29	1		T152	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	4		T11	4		T22	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	1		T4	1		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	2		T136	15		T30	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T11	10		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T44	13		T133	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T132	13		T12	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	12		T6	1		T137	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T41	1		T45	12		T178	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	3		T41	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	7		T25	1		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T112	1		T45	18		T133	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T142	1		T143	13		T230	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T196	1		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T44	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T11	21		T43	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T44	7		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T4	1		T137	6		T133	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14851	1			T8	20		T47	18		T48	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T169	8		T84	15		T291	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T258	3		T85	6		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	9		T152	10		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	11		T22	11		T143	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T4	1		T7	30		T42	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	13		T30	10		T195	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	7		T25	9		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	8		T44	11		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	13		T12	1		T145	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T220	3		T242	17		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T41	7		T45	6		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	2		T41	13		T25	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	5		T25	2		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	18		T133	10		T22	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T143	10		T258	8		T249	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	15		T196	19		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	10		T30	11		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	16		T43	3		T46	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	4		T44	10		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	3		T133	2		T184	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30