Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20787

1

T1

5

T2

1

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3313

1

T1

9

T4

4

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18038

1

T1

14

T4

2

T5

2

auto[1]

6062

1

T2

1

T3

17

T4

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	55	1			T30	45		T273	2		T296	8
values[0]	51	1			T31	14		T149	3		T224	5
values[1]	528	1			T6	1		T112	1		T137	3
values[2]	705	1			T1	5		T43	15		T26	11
values[3]	672	1			T5	1		T137	16		T25	15
values[4]	642	1			T4	2		T6	1		T41	13
values[5]	754	1			T44	24		T46	2		T220	4
values[6]	772	1			T4	4		T5	1		T6	1
values[7]	705	1			T1	9		T3	5		T4	16
values[8]	566	1			T192	1		T25	3		T152	19
values[9]	3433	1			T2	1		T3	12		T7	33
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	816	1			T1	5		T6	1		T112	1
values[1]	645	1			T43	13		T137	16		T25	15
values[2]	584	1			T5	1		T25	10		T29	10
values[3]	724	1			T4	2		T41	5		T44	1
values[4]	892	1			T4	4		T6	2		T41	22
values[5]	661	1			T1	9		T3	4		T5	1
values[6]	2956	1			T2	1		T3	1		T4	16
values[7]	526	1			T192	1		T136	28		T22	22
values[8]	845	1			T3	12		T45	18		T133	7
values[9]	216	1			T142	1		T238	1		T143	21
minimum	15235	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	3		T112	1		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	1		T43	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T137	1		T156	14		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	4		T25	15		T29	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T25	10		T29	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	1		T168	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	2		T41	5		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T196	20		T29	11		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	2		T44	12		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T4	4		T41	22		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T5	1		T11	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	9		T11	8		T45	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T2	1		T3	1		T4	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	1		T132	14		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T192	1		T136	14		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T22	12		T25	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	1		T133	3		T30	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	7		T238	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T143	13		T241	7		T246	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T142	1		T238	1		T250	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T166	1		T297	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T46	6		T133	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	1		T137	2		T22	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	15		T156	12		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	9		T33	1		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T152	12		T249	4		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T158	10		T170	15		T247	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	1		T133	14		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	1		T250	10		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	12		T12	1		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T145	11		T141	19		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	3		T11	23		T44	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	9		T45	17		T30	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T9	22		T10	25		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	2		T132	12		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	14		T152	7		T226	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T22	10		T139	1		T281	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	11		T133	4		T30	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	11		T151	13		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T143	8		T186	12		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T250	12		T187	2		T179	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T166	12		T297	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T30	23		T273	1		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T31	1		T149	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T224	1		T267	8		T299	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T112	1		T192	1		T46	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	1		T137	1		T22	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	3		T156	14		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	5		T26	1		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T137	1		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	15		T142	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	2		T6	1		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T41	8		T196	20		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	12		T46	1		T220	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T167	1		T200	10		T240	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T6	1		T11	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	4		T41	14		T132	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	2		T4	16		T44	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	9		T11	8		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T192	1		T152	12		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T25	3		T168	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1791	1			T2	1		T3	1		T7	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T45	7		T22	12		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T30	22		T273	1		T296	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T31	13		T149	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T224	4		T267	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T46	6		T133	1		T256	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	2		T22	24		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T156	12		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	10		T26	10		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	15		T152	12		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T33	1		T147	14		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T133	14		T229	4		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T145	11		T33	1		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	12		T46	1		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T200	7		T169	9		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	23		T44	4		T12	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T132	12		T152	9		T141	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	3		T44	1		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	9		T137	2		T45	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T152	7		T33	1		T226	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T164	3		T265	7		T281	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T3	11		T9	22		T10	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T45	11		T22	10		T139	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	3		T112	1		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	1		T43	2		T137	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	16		T156	13		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	10		T25	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T25	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	1		T168	1		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	1		T41	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T196	1		T29	1		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	2		T44	13		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	1		T41	2		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	4		T5	1		T11	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	1		T11	10		T45	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T2	1		T3	1		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	3		T132	13		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T192	1		T136	15		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	11		T25	1		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	12		T133	5		T30	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	12		T238	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T143	9		T241	1		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T142	1		T238	1		T250	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T166	13		T297	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	2		T46	5		T133	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	26		T184	15		T178	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	13		T250	19		T239	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T43	3		T25	14		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	9		T29	9		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T154	12		T247	4		T222	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	1		T41	4		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T196	19		T29	10		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T44	11		T12	1		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T4	3		T41	20		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	27		T44	2		T46	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	8		T11	7		T45	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T4	15		T7	30		T42	38
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	13		T27	1		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	13		T152	11		T226	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T22	11		T25	2		T281	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T133	2		T30	21		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T45	6		T151	12		T235	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T143	12		T241	6		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T250	9		T179	2		T248	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T30	24		T273	2		T296	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T31	14		T149	3		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T224	5		T267	9		T299	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T112	1		T192	1		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T137	3		T22	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	3		T156	13		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T43	12		T26	11		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T137	16		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T25	1		T142	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T6	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	1		T196	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	13		T46	2		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T167	1		T200	8		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T6	1		T11	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	1		T41	1		T132	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	5		T4	1		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T11	10		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T192	1		T152	8		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T25	1		T168	1		T164	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T2	1		T3	12		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T45	12		T22	11		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T30	21		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T182	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T267	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	5		T133	12		T295	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T22	26		T184	15		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	2		T156	13		T239	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	3		T29	10		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T29	9		T152	10		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T25	14		T33	1		T247	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T41	4		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	7		T196	19		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T44	11		T220	3		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T200	9		T240	13		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	27		T44	2		T12	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	3		T41	13		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	15		T44	8		T46	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	8		T11	7		T45	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	11		T226	6		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T25	2		T265	7		T281	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T7	30		T42	38		T133	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T45	6		T22	11		T151	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30