Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20499

1

T1

14

T2

1

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3601

1

T3

13

T4

18

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18365

1

T3

1

T4

2

T5

1

auto[1]

5735

1

T1

14

T2

1

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	240	1			T41	5		T25	3		T300	1
values[0]	12	1			T284	4		T261	8		-	-
values[1]	692	1			T44	17		T137	16		T46	2
values[2]	511	1			T3	4		T11	15		T43	2
values[3]	828	1			T1	14		T3	1		T4	16
values[4]	560	1			T4	2		T11	17		T43	13
values[5]	2858	1			T2	1		T6	1		T7	33
values[6]	650	1			T4	4		T6	1		T46	16
values[7]	768	1			T6	1		T44	24		T196	20
values[8]	698	1			T5	2		T192	1		T133	25
values[9]	1066	1			T3	12		T11	37		T41	14
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	696	1			T11	15		T44	7		T137	19
values[1]	612	1			T3	4		T4	16		T41	8
values[2]	727	1			T1	14		T3	1		T4	2
values[3]	2982	1			T2	1		T7	33		T9	25
values[4]	475	1			T6	1		T112	1		T137	3
values[5]	817	1			T4	4		T6	1		T46	16
values[6]	729	1			T5	1		T6	1		T44	24
values[7]	623	1			T3	12		T5	1		T22	25
values[8]	942	1			T11	37		T41	19		T44	1
values[9]	150	1			T301	1		T302	15		T303	3
minimum	15347	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	12		T44	3		T137	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	15		T142	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T22	12		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	16		T41	8		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	12		T197	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T4	2		T45	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	1		T7	33		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T136	14		T22	11		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T112	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T168	1		T246	10		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	4		T6	1		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T31	1		T29	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T12	3		T30	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T44	12		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T22	17		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	1		T249	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T41	14		T25	3		T178	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T11	17		T41	5		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T304	1		T305	13		T277	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T301	1		T302	1		T303	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15135	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T262	1		T248	10		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	3		T44	4		T137	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T230	1		T249	4		T169	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	3		T22	10		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T43	1		T45	17		T30	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	2		T148	11		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	11		T46	6		T133	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T9	22		T10	25		T11	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T136	14		T22	16		T162	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T137	2		T156	12		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T275	5		T231	8		T272	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	3		T33	1		T269	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T31	13		T139	1		T143	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T30	14		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T44	12		T133	14		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	8		T152	7		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	11		T224	5		T227	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T178	10		T151	2		T200	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	20		T132	12		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T305	4		T277	10		T307	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T302	14		T293	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	1		T46	1		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T262	15		T248	10		T308	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T25	3		T300	1		T187	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T41	5		T158	1		T179	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T284	1		T261	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T44	12		T137	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	1		T230	1		T249	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T11	12		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	1		T45	19		T25	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	12		T197	5		T22	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	1		T4	16		T41	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	8		T43	4		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	2		T133	13		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T2	1		T6	1		T7	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T22	11		T168	1		T162	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	4		T6	1		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T31	1		T29	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T196	20		T30	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	1		T44	12		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	2		T12	3		T22	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T192	1		T133	11		T25	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T41	14		T178	11		T141	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	1		T11	17		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T187	2		T309	2		T288	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T158	10		T179	3		T302	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T284	3		T261	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T44	5		T137	15		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T230	1		T249	4		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	3		T11	3		T137	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T43	1		T45	17		T30	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T22	10		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T45	11		T46	6		T30	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	9		T43	9		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T133	1		T136	14		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T9	22		T10	25		T135	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	16		T162	11		T231	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	3		T156	12		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	13		T139	1		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	14		T33	1		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	12		T151	13		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T22	8		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	14		T149	2		T162	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T178	10		T141	10		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	11		T11	20		T132	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	4		T44	5		T137	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	1		T142	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	4		T22	11		T152	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T41	1		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	4		T197	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T4	1		T45	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T2	1		T7	3		T9	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	15		T22	17		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T112	1		T137	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T168	1		T246	1		T275	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	1		T6	1		T46	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T31	14		T29	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	1		T12	3		T30	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T44	13		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T22	9		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	12		T249	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T41	1		T25	1		T178	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T11	21		T41	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T304	1		T305	5		T277	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T301	1		T302	15		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15246	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T262	16		T248	11		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	11		T44	2		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	14		T249	2		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	11		T152	10		T226	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	15		T41	7		T45	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	10		T197	4		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T45	6		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T7	30		T11	7		T42	38
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	13		T22	10		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T156	13		T237	3		T258	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T246	9		T310	14		T272	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	3		T46	12		T196	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T29	10		T220	3		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	1		T30	10		T156	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	11		T133	10		T25	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T22	16		T152	11		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T227	7		T243	9		T155	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T41	13		T25	2		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	16		T41	4		T132	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T305	12		T277	11		T307	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T303	2		T288	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T44	8		T145	2		T240	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	9		T311	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T25	1		T300	1		T187	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T41	1		T158	11		T179	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T284	4		T261	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T44	7		T137	16		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T167	1		T230	2		T249	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	4		T11	4		T137	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	2		T45	18		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	4		T197	1		T22	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T4	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	10		T43	10		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T133	2		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	1		T6	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	17		T168	1		T162	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	1		T6	1		T46	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	14		T29	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T196	1		T30	15		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	1		T44	13		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	2		T12	3		T22	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T192	1		T133	15		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T41	1		T178	11		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T3	12		T11	21		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T25	2		T309	11		T288	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T41	4		T179	2		T194	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	10		T133	2		T145	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T249	2		T169	8		T312	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	11		T152	10		T226	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	18		T25	14		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	10		T197	4		T22	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	15		T41	7		T45	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	7		T43	3		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T133	12		T136	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T7	30		T42	38		T24	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	10		T162	13		T310	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	3		T46	12		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	10		T143	12		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T196	19		T30	10		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T44	11		T27	1		T220	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T22	16		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	10		T25	9		T162	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T41	13		T178	10		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	16		T132	13		T152	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30