Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24100

1

T1

14

T2

1

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20517

1

T1

9

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3583

1

T1

5

T3

1

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18045

1

T1

5

T3

12

T6

1

auto[1]

6055

1

T1

9

T2

1

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

12

T2

1

T3

3

auto[1]

3960

1

T1

2

T3

14

T9

22

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	161	1			T3	1		T46	2		T25	3
values[0]	3	1			T247	3		-	-		-	-
values[1]	906	1			T137	16		T45	18		T192	1
values[2]	674	1			T1	9		T6	1		T11	69
values[3]	609	1			T1	5		T25	15		T29	10
values[4]	498	1			T3	12		T46	12		T197	5
values[5]	2977	1			T2	1		T4	4		T6	1
values[6]	740	1			T5	1		T46	16		T132	26
values[7]	671	1			T3	4		T5	1		T41	8
values[8]	912	1			T41	14		T112	1		T43	2
values[9]	732	1			T4	18		T6	1		T41	5
minimum	15217	1			T8	20		T47	18		T48	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	883	1			T43	13		T44	7		T137	16
values[1]	642	1			T1	9		T6	1		T11	69
values[2]	502	1			T1	5		T27	3		T184	16
values[3]	2890	1			T2	1		T3	12		T7	33
values[4]	629	1			T4	4		T6	1		T45	36
values[5]	794	1			T3	4		T5	1		T41	8
values[6]	780	1			T5	1		T44	10		T22	27
values[7]	747	1			T6	1		T41	19		T112	1
values[8]	631	1			T3	1		T4	2		T44	1
values[9]	130	1			T4	16		T169	18		T235	14
minimum	15472	1			T8	20		T47	18		T48	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

4067

1

T1

10

T4

19

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T43	4		T44	3		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T133	3		T31	1		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	9		T6	1		T11	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	20		T137	1		T29	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T168	1		T275	1		T239	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	3		T27	3		T184	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T2	1		T3	1		T7	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	11		T142	1		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T4	4		T152	12		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	1		T45	19		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	1		T5	1		T41	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T132	14		T133	11		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T44	9		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	11		T238	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T41	5		T43	1		T44	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T41	14		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	2		T44	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T46	1		T156	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T4	16		T169	9		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T235	14		T271	7		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15180	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T168	1		T221	1		T262	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	9		T44	4		T137	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T133	4		T31	13		T30	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	20		T30	26		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	12		T137	2		T158	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T275	5		T239	2		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	2		T162	11		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T3	11		T9	22		T10	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	12		T226	10		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T152	7		T149	2		T270	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	17		T136	14		T237	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	3		T46	3		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T132	12		T133	14		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	1		T22	16		T26	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T152	12		T162	10		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T43	1		T44	12		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	18		T149	14		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	2		T133	1		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	1		T156	2		T247	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T169	9		T236	12		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T271	1		T272	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	11		T12	2		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T262	4		T247	2		T281	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T25	3		T314	1		T188	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T3	1		T46	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T247	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T137	1		T45	7		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	3		T31	1		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	9		T6	1		T11	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	20		T137	1		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	15		T29	10		T30	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	3		T184	16		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T46	6		T197	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	3		T29	11		T142	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T2	1		T4	4		T7	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	1		T45	19		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T46	13		T151	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T132	14		T133	11		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T5	1		T41	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T167	1		T162	18		T258	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T43	1		T44	12		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T41	14		T112	1		T22	29
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	18		T41	5		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T156	12		T258	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15103	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T188	15		T288	10		T290	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T46	1		T247	4		T271	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T137	15		T45	11		T143	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T133	4		T31	13		T30	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	20		T43	9		T44	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	12		T137	2		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	26		T275	5		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	2		T162	11		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	11		T46	6		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T226	10		T234	14		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T9	22		T10	25		T135	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	17		T136	14		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T46	3		T151	13		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T132	12		T133	14		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	3		T44	1		T149	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T162	10		T228	14		T222	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	1		T44	12		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T22	18		T152	12		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	2		T133	1		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T156	2		T248	10		T279	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T33	7		T199	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T43	10		T44	5		T137	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T133	5		T31	14		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T6	1		T11	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	14		T137	3		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T168	1		T275	6		T239	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	3		T27	2		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T3	12		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	1		T142	1		T143	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	1		T152	8		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T45	18		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	4		T5	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T132	13		T133	15		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T44	2		T22	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T152	13		T238	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	1		T43	2		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T41	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T44	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T46	2		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T4	1		T169	10		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T235	1		T271	2		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15309	1			T8	20		T47	18		T48	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T168	1		T221	1		T262	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	3		T44	2		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T133	2		T30	10		T241	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	8		T11	16		T25	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	18		T29	10		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T239	14		T276	1		T277	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	2		T27	1		T184	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T7	30		T42	38		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T29	10		T143	10		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T4	3		T152	11		T265	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T45	18		T136	13		T237	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	7		T46	12		T196	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T132	13		T133	10		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T44	8		T22	10		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T152	10		T162	17		T222	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	4		T44	11		T25	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	13		T22	27		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T4	1		T133	12		T25	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T156	11		T258	3		T194	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T4	15		T169	8		T315	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T235	13		T271	6		T272	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T45	6		T241	9		T243	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T281	2		T316	14		T317	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T25	1		T314	1		T188	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T3	1		T46	2		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T247	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T137	16		T45	12		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T133	5		T31	14		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T6	1		T11	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	14		T137	3		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T25	1		T29	1		T30	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	3		T184	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	12		T46	7		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	2		T29	1		T142	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	1		T4	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	1		T45	18		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T46	4		T151	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T132	13		T133	15		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	4		T5	1		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T167	1		T162	11		T258	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	2		T44	13		T22	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T41	1		T112	1		T22	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	2		T41	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T156	3		T258	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15217	1			T8	20		T47	18		T48	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T25	2		T288	21		T290	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T247	4		T295	9		T271	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T45	6		T143	12		T145	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T133	2		T30	10		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	8		T11	16		T43	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	18		T29	10		T240	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	14		T29	9		T30	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	2		T184	15		T162	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	5		T197	4		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T27	1		T29	10		T234	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T4	3		T7	30		T42	38
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	18		T136	13		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	12		T151	12		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T132	13		T133	10		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	7		T44	8		T196	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T162	17		T258	8		T195	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	11		T22	10		T25	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T41	13		T22	27		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	16		T41	4		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	11		T258	3		T194	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20033

1

T1

4

T2

1

T3

17

auto[1]

auto[0]

4067

1

T1

10

T4

19

T7

30