Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.83 98.33 91.02


Total test records in report: 918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T796 /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3491910312 Aug 12 06:09:13 PM PDT 24 Aug 12 06:11:39 PM PDT 24 253397374192 ps
T260 /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3052067242 Aug 12 06:13:16 PM PDT 24 Aug 12 06:16:49 PM PDT 24 527031369990 ps
T797 /workspace/coverage/default/3.adc_ctrl_fsm_reset.1964181628 Aug 12 06:08:56 PM PDT 24 Aug 12 06:15:42 PM PDT 24 102531253478 ps
T61 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.791270296 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:28 PM PDT 24 643326112 ps
T798 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2992287383 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:55 PM PDT 24 410806672 ps
T113 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3584556504 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:47 PM PDT 24 538435253 ps
T799 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.109828980 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:55 PM PDT 24 420858116 ps
T62 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1402087189 Aug 12 05:50:40 PM PDT 24 Aug 12 05:50:43 PM PDT 24 1104163659 ps
T54 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4176119855 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:55 PM PDT 24 2301564494 ps
T800 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2401864339 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:57 PM PDT 24 586104406 ps
T801 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2867605498 Aug 12 05:50:55 PM PDT 24 Aug 12 05:50:57 PM PDT 24 287890354 ps
T802 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2989264067 Aug 12 05:50:54 PM PDT 24 Aug 12 05:50:56 PM PDT 24 529600761 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2407019263 Aug 12 05:50:24 PM PDT 24 Aug 12 05:50:26 PM PDT 24 387038575 ps
T57 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.594988965 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:39 PM PDT 24 4621573639 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.527011825 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:35 PM PDT 24 837642093 ps
T68 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2090106732 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:41 PM PDT 24 415788359 ps
T803 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1546579780 Aug 12 05:50:55 PM PDT 24 Aug 12 05:50:56 PM PDT 24 534318814 ps
T75 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.938742582 Aug 12 05:50:44 PM PDT 24 Aug 12 05:50:46 PM PDT 24 365445548 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1033831723 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:36 PM PDT 24 371962233 ps
T58 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2204771218 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:54 PM PDT 24 8739295586 ps
T70 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1649066865 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:49 PM PDT 24 561771831 ps
T115 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.752426919 Aug 12 05:50:27 PM PDT 24 Aug 12 05:50:28 PM PDT 24 508374970 ps
T116 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2138010218 Aug 12 05:50:50 PM PDT 24 Aug 12 05:50:52 PM PDT 24 530273819 ps
T804 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1771689995 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:40 PM PDT 24 366834716 ps
T805 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.983978620 Aug 12 05:50:31 PM PDT 24 Aug 12 05:50:32 PM PDT 24 471150243 ps
T806 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1602575755 Aug 12 05:51:00 PM PDT 24 Aug 12 05:51:02 PM PDT 24 483180703 ps
T92 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2858163544 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:41 PM PDT 24 593701547 ps
T807 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3799129310 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:27 PM PDT 24 343777055 ps
T808 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2306301486 Aug 12 05:50:41 PM PDT 24 Aug 12 05:50:42 PM PDT 24 362148660 ps
T809 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1725508389 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:58 PM PDT 24 466954863 ps
T73 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1055934598 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:54 PM PDT 24 320791139 ps
T810 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.497854068 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:54 PM PDT 24 343647908 ps
T131 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1588466063 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:43 PM PDT 24 410353429 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2641859530 Aug 12 05:50:27 PM PDT 24 Aug 12 05:50:30 PM PDT 24 603727788 ps
T811 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1132722357 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:50 PM PDT 24 376486084 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3437744804 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:43 PM PDT 24 387837586 ps
T126 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1188628657 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:55 PM PDT 24 2338938783 ps
T117 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1946054622 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:44 PM PDT 24 479594994 ps
T813 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2960803002 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:34 PM PDT 24 450113385 ps
T814 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2369307127 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:34 PM PDT 24 282189307 ps
T55 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1633876795 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:53 PM PDT 24 21528645290 ps
T56 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2033830427 Aug 12 05:50:35 PM PDT 24 Aug 12 05:50:45 PM PDT 24 4432168171 ps
T815 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.716964678 Aug 12 05:50:58 PM PDT 24 Aug 12 05:51:00 PM PDT 24 482684320 ps
T76 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.314189396 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:41 PM PDT 24 448189101 ps
T816 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.391994965 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:57 PM PDT 24 398087857 ps
T817 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2979073939 Aug 12 05:50:49 PM PDT 24 Aug 12 05:50:51 PM PDT 24 535004164 ps
T122 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3570217985 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:35 PM PDT 24 556825633 ps
T127 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4186371776 Aug 12 05:50:39 PM PDT 24 Aug 12 05:51:02 PM PDT 24 4524257095 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4244350645 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:56 PM PDT 24 4030775083 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3219663895 Aug 12 05:50:45 PM PDT 24 Aug 12 05:50:47 PM PDT 24 641880587 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1092249115 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:35 PM PDT 24 518279152 ps
T820 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2393294088 Aug 12 05:50:57 PM PDT 24 Aug 12 05:50:58 PM PDT 24 327824366 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3912695419 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:38 PM PDT 24 3273932119 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1426868257 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:34 PM PDT 24 399716976 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3531957747 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:47 PM PDT 24 2562729334 ps
T822 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1252053677 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:57 PM PDT 24 432968048 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.492233420 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:28 PM PDT 24 291811738 ps
T824 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2025116632 Aug 12 05:50:54 PM PDT 24 Aug 12 05:50:55 PM PDT 24 534103167 ps
T63 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4241202086 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:59 PM PDT 24 4349425157 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2287385559 Aug 12 05:50:27 PM PDT 24 Aug 12 05:50:29 PM PDT 24 424385995 ps
T825 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3901342302 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:27 PM PDT 24 902095806 ps
T826 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2794874414 Aug 12 05:51:00 PM PDT 24 Aug 12 05:51:01 PM PDT 24 531747983 ps
T129 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3953515464 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:48 PM PDT 24 522941362 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4008613384 Aug 12 05:50:25 PM PDT 24 Aug 12 05:50:33 PM PDT 24 4407386997 ps
T827 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4212467144 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:50 PM PDT 24 405848270 ps
T120 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.717030669 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:33 PM PDT 24 574685771 ps
T828 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2335225559 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:42 PM PDT 24 5365098279 ps
T829 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1518196937 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:54 PM PDT 24 495224095 ps
T830 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4274795287 Aug 12 05:50:55 PM PDT 24 Aug 12 05:50:57 PM PDT 24 516545317 ps
T831 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4244422217 Aug 12 05:50:38 PM PDT 24 Aug 12 05:50:39 PM PDT 24 472436950 ps
T832 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1132568983 Aug 12 05:50:59 PM PDT 24 Aug 12 05:51:00 PM PDT 24 470034086 ps
T121 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2325658532 Aug 12 05:50:31 PM PDT 24 Aug 12 05:50:32 PM PDT 24 343261059 ps
T833 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2644921696 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:35 PM PDT 24 649410181 ps
T834 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3472906729 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:27 PM PDT 24 729535651 ps
T835 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3292296223 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:58 PM PDT 24 374362233 ps
T836 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.594536745 Aug 12 05:50:54 PM PDT 24 Aug 12 05:50:55 PM PDT 24 454669387 ps
T837 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2100607309 Aug 12 05:50:41 PM PDT 24 Aug 12 05:50:43 PM PDT 24 456406426 ps
T838 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1223914385 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:51 PM PDT 24 770575712 ps
T64 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3477369082 Aug 12 05:50:38 PM PDT 24 Aug 12 05:50:51 PM PDT 24 8334247230 ps
T345 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2806938872 Aug 12 05:50:50 PM PDT 24 Aug 12 05:50:53 PM PDT 24 4104486592 ps
T123 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2618784129 Aug 12 05:50:37 PM PDT 24 Aug 12 05:50:55 PM PDT 24 9869402685 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3013324431 Aug 12 05:50:36 PM PDT 24 Aug 12 05:50:37 PM PDT 24 469431880 ps
T124 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2319732101 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:44 PM PDT 24 483789621 ps
T840 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3783988674 Aug 12 05:50:37 PM PDT 24 Aug 12 05:50:39 PM PDT 24 514966176 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3720063925 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:49 PM PDT 24 482212907 ps
T346 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3153142778 Aug 12 05:50:41 PM PDT 24 Aug 12 05:50:49 PM PDT 24 8687420803 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2840394757 Aug 12 05:50:35 PM PDT 24 Aug 12 05:50:53 PM PDT 24 7628918121 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3712406300 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:41 PM PDT 24 4484758395 ps
T844 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1782320481 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:50 PM PDT 24 461009840 ps
T845 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2895584339 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:54 PM PDT 24 394023385 ps
T77 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2218172543 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:52 PM PDT 24 8739921728 ps
T125 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.433041795 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:54 PM PDT 24 345864614 ps
T347 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3850562353 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:43 PM PDT 24 4070724779 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1156848027 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:51 PM PDT 24 4618495523 ps
T847 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1113436554 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:41 PM PDT 24 382504234 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4261209247 Aug 12 05:50:25 PM PDT 24 Aug 12 05:51:23 PM PDT 24 26877907461 ps
T849 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3301376707 Aug 12 05:50:37 PM PDT 24 Aug 12 05:50:39 PM PDT 24 408077060 ps
T78 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2275650499 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:39 PM PDT 24 4623068224 ps
T850 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1020054796 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:49 PM PDT 24 620367558 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2664791587 Aug 12 05:50:57 PM PDT 24 Aug 12 05:51:01 PM PDT 24 5192642622 ps
T852 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2073780486 Aug 12 05:50:57 PM PDT 24 Aug 12 05:50:58 PM PDT 24 444810098 ps
T853 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3383627814 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:48 PM PDT 24 501374410 ps
T854 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2138588203 Aug 12 05:50:58 PM PDT 24 Aug 12 05:51:00 PM PDT 24 341055357 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2280016111 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:34 PM PDT 24 507413846 ps
T856 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2166274139 Aug 12 05:50:44 PM PDT 24 Aug 12 05:50:46 PM PDT 24 472423475 ps
T857 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3068122781 Aug 12 05:50:36 PM PDT 24 Aug 12 05:50:38 PM PDT 24 608641161 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.201224444 Aug 12 05:50:24 PM PDT 24 Aug 12 05:50:27 PM PDT 24 589444062 ps
T859 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3813107847 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:43 PM PDT 24 441143720 ps
T860 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1236323066 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:36 PM PDT 24 2806975246 ps
T861 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2338630392 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:55 PM PDT 24 468365056 ps
T862 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2315270498 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:52 PM PDT 24 2738860750 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3993588419 Aug 12 05:50:29 PM PDT 24 Aug 12 05:50:48 PM PDT 24 8152129981 ps
T864 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2270023213 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:55 PM PDT 24 349233568 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2178765742 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:38 PM PDT 24 4696193863 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3491504556 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:55 PM PDT 24 4137014465 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3976924305 Aug 12 05:50:40 PM PDT 24 Aug 12 05:50:42 PM PDT 24 2593704202 ps
T868 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.620297206 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:54 PM PDT 24 530011388 ps
T869 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.31403738 Aug 12 05:50:25 PM PDT 24 Aug 12 05:50:27 PM PDT 24 1652032374 ps
T870 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2221639863 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:27 PM PDT 24 399651522 ps
T871 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1775073481 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:56 PM PDT 24 2095846399 ps
T872 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3032053826 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:54 PM PDT 24 498778266 ps
T873 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1649868711 Aug 12 05:50:41 PM PDT 24 Aug 12 05:50:42 PM PDT 24 358668414 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1970146891 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:42 PM PDT 24 428565155 ps
T875 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1755639812 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:51 PM PDT 24 386442680 ps
T876 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3115287102 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:54 PM PDT 24 4830207667 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3792306505 Aug 12 05:50:38 PM PDT 24 Aug 12 05:50:40 PM PDT 24 660027580 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.768466839 Aug 12 05:50:35 PM PDT 24 Aug 12 05:50:37 PM PDT 24 504799964 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.994740991 Aug 12 05:50:28 PM PDT 24 Aug 12 05:50:48 PM PDT 24 8673594100 ps
T880 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.575242210 Aug 12 05:50:37 PM PDT 24 Aug 12 05:50:39 PM PDT 24 488729934 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3890661821 Aug 12 05:50:30 PM PDT 24 Aug 12 05:50:34 PM PDT 24 756460346 ps
T882 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.164734501 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:35 PM PDT 24 499484275 ps
T883 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1303587365 Aug 12 05:51:00 PM PDT 24 Aug 12 05:51:01 PM PDT 24 483379463 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1933326962 Aug 12 05:50:31 PM PDT 24 Aug 12 05:50:33 PM PDT 24 427338300 ps
T885 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.950562482 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:35 PM PDT 24 382313115 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2046542094 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:48 PM PDT 24 324767793 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.602389065 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:38 PM PDT 24 1160437479 ps
T888 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1959279835 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:42 PM PDT 24 4624779678 ps
T889 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3795123878 Aug 12 05:50:25 PM PDT 24 Aug 12 05:50:26 PM PDT 24 490354772 ps
T890 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2821868336 Aug 12 05:50:35 PM PDT 24 Aug 12 05:50:39 PM PDT 24 4448709207 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.614228995 Aug 12 05:50:52 PM PDT 24 Aug 12 05:50:53 PM PDT 24 406852869 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.772190995 Aug 12 05:50:48 PM PDT 24 Aug 12 05:50:49 PM PDT 24 492319155 ps
T893 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4045573446 Aug 12 05:50:26 PM PDT 24 Aug 12 05:50:27 PM PDT 24 312868461 ps
T894 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3931863516 Aug 12 05:50:59 PM PDT 24 Aug 12 05:51:00 PM PDT 24 373511879 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2543828414 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:44 PM PDT 24 354366015 ps
T896 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3468370414 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:57 PM PDT 24 312181297 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3268885053 Aug 12 05:50:27 PM PDT 24 Aug 12 05:50:28 PM PDT 24 1526281299 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3802173517 Aug 12 05:50:41 PM PDT 24 Aug 12 05:50:53 PM PDT 24 4531822306 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3428684798 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:38 PM PDT 24 2268700138 ps
T900 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3349851200 Aug 12 05:50:46 PM PDT 24 Aug 12 05:50:49 PM PDT 24 432800878 ps
T901 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1040740209 Aug 12 05:50:39 PM PDT 24 Aug 12 05:50:45 PM PDT 24 3976651616 ps
T902 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3633911118 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:44 PM PDT 24 575756817 ps
T348 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4061074941 Aug 12 05:50:38 PM PDT 24 Aug 12 05:50:52 PM PDT 24 8414059363 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2786078396 Aug 12 05:50:45 PM PDT 24 Aug 12 05:50:47 PM PDT 24 581120818 ps
T904 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.116822317 Aug 12 05:50:53 PM PDT 24 Aug 12 05:50:55 PM PDT 24 355655331 ps
T905 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2734030494 Aug 12 05:50:38 PM PDT 24 Aug 12 05:50:41 PM PDT 24 4398253336 ps
T906 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.949502474 Aug 12 05:50:47 PM PDT 24 Aug 12 05:50:49 PM PDT 24 446146673 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.350488674 Aug 12 05:50:28 PM PDT 24 Aug 12 05:50:31 PM PDT 24 2435297648 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1646483408 Aug 12 05:50:35 PM PDT 24 Aug 12 05:51:00 PM PDT 24 51146550287 ps
T909 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4258078337 Aug 12 05:50:31 PM PDT 24 Aug 12 05:50:34 PM PDT 24 316619096 ps
T910 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1051176378 Aug 12 05:50:33 PM PDT 24 Aug 12 05:50:35 PM PDT 24 528468443 ps
T911 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3887137541 Aug 12 05:50:34 PM PDT 24 Aug 12 05:50:39 PM PDT 24 4692816439 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2650227177 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:38 PM PDT 24 1366290607 ps
T913 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2028469664 Aug 12 05:50:56 PM PDT 24 Aug 12 05:50:57 PM PDT 24 329369694 ps
T914 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1772125748 Aug 12 05:50:32 PM PDT 24 Aug 12 05:50:33 PM PDT 24 1427688801 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2029099470 Aug 12 05:50:49 PM PDT 24 Aug 12 05:50:53 PM PDT 24 595219532 ps
T916 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.956480763 Aug 12 05:50:42 PM PDT 24 Aug 12 05:50:46 PM PDT 24 2444501393 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.923456779 Aug 12 05:50:31 PM PDT 24 Aug 12 05:50:32 PM PDT 24 1327862538 ps
T918 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3217942806 Aug 12 05:50:50 PM PDT 24 Aug 12 05:50:51 PM PDT 24 391037817 ps

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.705204634
Short name T1
Test name
Test status
Simulation time 328013365085 ps
CPU time 584.07 seconds
Started Aug 12 06:10:13 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 201664 kb
Host smart-01d85429-9338-4edd-bba5-b7601a809037
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705204634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.705204634
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1657019161
Short name T43
Test name
Test status
Simulation time 409265165513 ps
CPU time 387.88 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:15:50 PM PDT 24
Peak memory 212164 kb
Host smart-afbe3617-334d-40a4-8e1c-aab6ad8a91d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657019161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1657019161
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2126261849
Short name T11
Test name
Test status
Simulation time 538912742702 ps
CPU time 210.25 seconds
Started Aug 12 06:11:26 PM PDT 24
Finished Aug 12 06:14:57 PM PDT 24
Peak memory 201616 kb
Host smart-81dcb5b9-1248-4057-8caf-2b90a830b3f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126261849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2126261849
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1464089985
Short name T12
Test name
Test status
Simulation time 34404973877 ps
CPU time 11.32 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:12:25 PM PDT 24
Peak memory 210164 kb
Host smart-d996340a-3aee-4b0b-a772-6620c3d00f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464089985 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1464089985
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.81480482
Short name T44
Test name
Test status
Simulation time 664818823401 ps
CPU time 377.84 seconds
Started Aug 12 06:09:36 PM PDT 24
Finished Aug 12 06:15:54 PM PDT 24
Peak memory 201724 kb
Host smart-a35a6213-6039-4861-87c3-ed35e9527493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81480482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.81480482
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2799364109
Short name T145
Test name
Test status
Simulation time 557461354704 ps
CPU time 277.62 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:14:03 PM PDT 24
Peak memory 201656 kb
Host smart-bd727a04-3243-4093-91c0-9d60d876cd31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799364109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2799364109
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3175073173
Short name T51
Test name
Test status
Simulation time 90422849285 ps
CPU time 268.01 seconds
Started Aug 12 06:11:56 PM PDT 24
Finished Aug 12 06:16:24 PM PDT 24
Peak memory 201912 kb
Host smart-beacae37-1e9e-485b-87e3-4c8a6a4b1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175073173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3175073173
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.436646550
Short name T152
Test name
Test status
Simulation time 543708255184 ps
CPU time 1194.34 seconds
Started Aug 12 06:11:47 PM PDT 24
Finished Aug 12 06:31:42 PM PDT 24
Peak memory 201676 kb
Host smart-38838bbc-729a-4f2d-bc6d-8b1d3515b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436646550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.436646550
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3647286841
Short name T250
Test name
Test status
Simulation time 590953076892 ps
CPU time 621.86 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:19:47 PM PDT 24
Peak memory 201676 kb
Host smart-10d87d7a-4d75-49ce-8031-4cb413ff064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647286841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3647286841
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2431511846
Short name T46
Test name
Test status
Simulation time 489209099994 ps
CPU time 148.2 seconds
Started Aug 12 06:09:58 PM PDT 24
Finished Aug 12 06:12:26 PM PDT 24
Peak memory 201640 kb
Host smart-bee8cda6-ba02-4d63-b845-ecb49f3edde7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431511846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2431511846
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1402087189
Short name T62
Test name
Test status
Simulation time 1104163659 ps
CPU time 2.33 seconds
Started Aug 12 05:50:40 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 201204 kb
Host smart-ca1adc82-815a-426f-b354-8998c9b4fb30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402087189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1402087189
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1304045874
Short name T248
Test name
Test status
Simulation time 503540751516 ps
CPU time 558.4 seconds
Started Aug 12 06:10:50 PM PDT 24
Finished Aug 12 06:20:08 PM PDT 24
Peak memory 201704 kb
Host smart-e96dae2d-17fe-44bb-97e1-5b1f647738ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304045874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1304045874
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3608715053
Short name T45
Test name
Test status
Simulation time 389768821402 ps
CPU time 243.3 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:13:21 PM PDT 24
Peak memory 201556 kb
Host smart-ea30a80e-c7d5-47df-af2e-e96bc6b4c4b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608715053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3608715053
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2080275993
Short name T22
Test name
Test status
Simulation time 541854661844 ps
CPU time 332.59 seconds
Started Aug 12 06:09:51 PM PDT 24
Finished Aug 12 06:15:24 PM PDT 24
Peak memory 201628 kb
Host smart-222bf4b9-ff5b-47c4-85f6-a3389bee5a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080275993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2080275993
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2739602825
Short name T133
Test name
Test status
Simulation time 520658857441 ps
CPU time 322.7 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:15:22 PM PDT 24
Peak memory 201636 kb
Host smart-2f5a1c01-7ba4-4816-8a67-c954f4390c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739602825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2739602825
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.910522136
Short name T390
Test name
Test status
Simulation time 514671625 ps
CPU time 1.22 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:08:50 PM PDT 24
Peak memory 201464 kb
Host smart-43ecff81-33d5-46c4-a652-cd9cf2556d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910522136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.910522136
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2342970584
Short name T156
Test name
Test status
Simulation time 496379575681 ps
CPU time 1177.63 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:29:37 PM PDT 24
Peak memory 201656 kb
Host smart-335fcc1f-bc23-4fbb-b868-a581f760ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342970584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2342970584
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1633876795
Short name T55
Test name
Test status
Simulation time 21528645290 ps
CPU time 20.36 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 201172 kb
Host smart-31187ed3-76d5-4514-a098-7ddd72a6ddf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633876795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1633876795
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1589926360
Short name T80
Test name
Test status
Simulation time 3967389489 ps
CPU time 9.54 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:09:02 PM PDT 24
Peak memory 217000 kb
Host smart-0483c3c2-c6fd-49bb-97cb-7db5a3cee6da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589926360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1589926360
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3474371033
Short name T143
Test name
Test status
Simulation time 335035847950 ps
CPU time 90.61 seconds
Started Aug 12 06:10:01 PM PDT 24
Finished Aug 12 06:11:32 PM PDT 24
Peak memory 201640 kb
Host smart-eb07869c-f202-4210-891a-d061793a689a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474371033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3474371033
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4286354552
Short name T170
Test name
Test status
Simulation time 507778231298 ps
CPU time 300.52 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:14:28 PM PDT 24
Peak memory 201636 kb
Host smart-203127e2-7254-45e6-813b-28fb8ba53edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286354552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4286354552
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2245820640
Short name T249
Test name
Test status
Simulation time 548097464236 ps
CPU time 1286.48 seconds
Started Aug 12 06:09:26 PM PDT 24
Finished Aug 12 06:30:52 PM PDT 24
Peak memory 201676 kb
Host smart-be748bb6-9171-44bb-a85e-e7c7210ea41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245820640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2245820640
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.530628651
Short name T151
Test name
Test status
Simulation time 483619768876 ps
CPU time 276.92 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:15:59 PM PDT 24
Peak memory 201668 kb
Host smart-ff699d32-c0c4-4332-82fb-79b662434e7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530628651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.530628651
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.651116846
Short name T10
Test name
Test status
Simulation time 490619027976 ps
CPU time 1070.97 seconds
Started Aug 12 06:09:18 PM PDT 24
Finished Aug 12 06:27:09 PM PDT 24
Peak memory 201688 kb
Host smart-da683fe3-483f-4301-88e8-0402593b530e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=651116846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.651116846
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2372550854
Short name T234
Test name
Test status
Simulation time 368652875664 ps
CPU time 404.33 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:15:34 PM PDT 24
Peak memory 201612 kb
Host smart-264ccbd6-7e81-4540-9bbb-a475f1ff0655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372550854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2372550854
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4160026233
Short name T247
Test name
Test status
Simulation time 520530087518 ps
CPU time 626.74 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 201680 kb
Host smart-0ae28963-8a95-437b-a9b6-0904ef35adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160026233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4160026233
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.4141719547
Short name T277
Test name
Test status
Simulation time 511894962529 ps
CPU time 1269.67 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:30:24 PM PDT 24
Peak memory 201648 kb
Host smart-43137884-71ce-41fd-a51a-74473387f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141719547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4141719547
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3463198953
Short name T284
Test name
Test status
Simulation time 480043065635 ps
CPU time 188.68 seconds
Started Aug 12 06:11:21 PM PDT 24
Finished Aug 12 06:14:29 PM PDT 24
Peak memory 201728 kb
Host smart-97528c0d-5bce-4b68-a2ee-cc47e900e9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463198953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3463198953
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2218172543
Short name T77
Test name
Test status
Simulation time 8739921728 ps
CPU time 12.84 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:52 PM PDT 24
Peak memory 201236 kb
Host smart-f9bc3d1a-a5fe-4c06-89e8-4c0796aaf608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218172543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2218172543
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1060460283
Short name T228
Test name
Test status
Simulation time 519559901087 ps
CPU time 1155.06 seconds
Started Aug 12 06:10:18 PM PDT 24
Finished Aug 12 06:29:33 PM PDT 24
Peak memory 201688 kb
Host smart-c25efee3-6030-4e86-a5f9-689468929744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060460283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1060460283
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4274601610
Short name T253
Test name
Test status
Simulation time 504185594787 ps
CPU time 153.56 seconds
Started Aug 12 06:12:10 PM PDT 24
Finished Aug 12 06:14:43 PM PDT 24
Peak memory 201640 kb
Host smart-b66d4e4b-539a-42f2-be8b-288b45b94a50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274601610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4274601610
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3169851075
Short name T224
Test name
Test status
Simulation time 327080387753 ps
CPU time 764.09 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 201668 kb
Host smart-16655261-1eb6-4348-bb10-6269e66c9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169851075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3169851075
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.461996007
Short name T288
Test name
Test status
Simulation time 491214437463 ps
CPU time 307.44 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:14:00 PM PDT 24
Peak memory 201592 kb
Host smart-f9be49a2-0549-4125-8d45-f3a8b9fd272c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461996007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.461996007
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2181611726
Short name T179
Test name
Test status
Simulation time 525624566945 ps
CPU time 1201 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:29:06 PM PDT 24
Peak memory 201676 kb
Host smart-512f37a9-d1cb-440c-a752-8fdcb3139b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181611726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2181611726
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2838008249
Short name T33
Test name
Test status
Simulation time 217214138805 ps
CPU time 22.3 seconds
Started Aug 12 06:12:47 PM PDT 24
Finished Aug 12 06:13:09 PM PDT 24
Peak memory 209900 kb
Host smart-5eb88bc4-e952-48aa-8430-97b44d181b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838008249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2838008249
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1419379772
Short name T31
Test name
Test status
Simulation time 324548471837 ps
CPU time 759.92 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:21:57 PM PDT 24
Peak memory 202068 kb
Host smart-7e36bed0-a81f-4592-bfb7-7e64bad8ead7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419379772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1419379772
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3232017072
Short name T222
Test name
Test status
Simulation time 337478276069 ps
CPU time 353.43 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:15:36 PM PDT 24
Peak memory 201660 kb
Host smart-0458c9e4-c0e0-48ae-b4f9-00eeb72d005b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232017072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3232017072
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1302239917
Short name T174
Test name
Test status
Simulation time 334657349732 ps
CPU time 135.48 seconds
Started Aug 12 06:09:12 PM PDT 24
Finished Aug 12 06:11:27 PM PDT 24
Peak memory 201612 kb
Host smart-e553f5e7-0d20-416f-bc24-d4358a991bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302239917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1302239917
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4064284273
Short name T280
Test name
Test status
Simulation time 327000720230 ps
CPU time 750.3 seconds
Started Aug 12 06:10:19 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 201716 kb
Host smart-4569ff7a-464f-4e23-b142-c2212ba98c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064284273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4064284273
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3052067242
Short name T260
Test name
Test status
Simulation time 527031369990 ps
CPU time 213.1 seconds
Started Aug 12 06:13:16 PM PDT 24
Finished Aug 12 06:16:49 PM PDT 24
Peak memory 201704 kb
Host smart-00cbab17-bf1c-4ebd-86b0-de4d7e155b22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052067242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3052067242
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1900010228
Short name T169
Test name
Test status
Simulation time 193063299245 ps
CPU time 52.03 seconds
Started Aug 12 06:09:31 PM PDT 24
Finished Aug 12 06:10:23 PM PDT 24
Peak memory 201692 kb
Host smart-d331ea9f-5d1a-4e58-a61d-326bacb2523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900010228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1900010228
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.701506086
Short name T24
Test name
Test status
Simulation time 401395847829 ps
CPU time 464.84 seconds
Started Aug 12 06:08:46 PM PDT 24
Finished Aug 12 06:16:31 PM PDT 24
Peak memory 201680 kb
Host smart-90de5f32-fd24-41b5-8eeb-19d645e46276
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701506086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.701506086
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.247630745
Short name T275
Test name
Test status
Simulation time 162449949975 ps
CPU time 407.13 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:16:10 PM PDT 24
Peak memory 201672 kb
Host smart-bfd864b3-aeb5-4dd8-b33c-1e4337d2a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247630745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.247630745
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3886636871
Short name T273
Test name
Test status
Simulation time 337499328183 ps
CPU time 478.44 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:17:03 PM PDT 24
Peak memory 201696 kb
Host smart-079b7f38-a992-463a-a1ab-d095f91654c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886636871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3886636871
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2331677391
Short name T109
Test name
Test status
Simulation time 406186327574 ps
CPU time 444.41 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:16:27 PM PDT 24
Peak memory 201612 kb
Host smart-103fea17-c1c6-4c7d-8358-e0ff7ca7d38c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331677391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2331677391
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.752426919
Short name T115
Test name
Test status
Simulation time 508374970 ps
CPU time 0.9 seconds
Started Aug 12 05:50:27 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 200888 kb
Host smart-cbe8ac6b-2bee-47ec-a476-c929a4c6507d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752426919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.752426919
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.791270296
Short name T61
Test name
Test status
Simulation time 643326112 ps
CPU time 1.96 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 209356 kb
Host smart-e58b8f0c-5ace-456d-b3be-ce3ddaeee144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791270296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.791270296
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.654119265
Short name T271
Test name
Test status
Simulation time 494799270231 ps
CPU time 260.59 seconds
Started Aug 12 06:10:03 PM PDT 24
Finished Aug 12 06:14:24 PM PDT 24
Peak memory 201672 kb
Host smart-53b42ed1-be32-4c22-a074-839fcddcd25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654119265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.654119265
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3979515273
Short name T341
Test name
Test status
Simulation time 494556017961 ps
CPU time 1199.56 seconds
Started Aug 12 06:10:26 PM PDT 24
Finished Aug 12 06:30:26 PM PDT 24
Peak memory 201656 kb
Host smart-1df2d752-b55e-499d-b392-c08b8b67ac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979515273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3979515273
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2513562458
Short name T329
Test name
Test status
Simulation time 495816544695 ps
CPU time 592.13 seconds
Started Aug 12 06:10:39 PM PDT 24
Finished Aug 12 06:20:31 PM PDT 24
Peak memory 201648 kb
Host smart-a9c1a66c-2769-42f7-8242-b99d6903add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513562458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2513562458
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1965009048
Short name T187
Test name
Test status
Simulation time 325733742840 ps
CPU time 147.1 seconds
Started Aug 12 06:09:43 PM PDT 24
Finished Aug 12 06:12:11 PM PDT 24
Peak memory 201616 kb
Host smart-197fa607-1fd3-49c7-8e90-117d2de896e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965009048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1965009048
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4261566110
Short name T266
Test name
Test status
Simulation time 320129838035 ps
CPU time 729.61 seconds
Started Aug 12 06:10:16 PM PDT 24
Finished Aug 12 06:22:26 PM PDT 24
Peak memory 201640 kb
Host smart-8d1f95df-3b5c-476a-bae3-f4c81a2fb1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261566110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4261566110
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1588435835
Short name T204
Test name
Test status
Simulation time 1403626518601 ps
CPU time 828.63 seconds
Started Aug 12 06:11:21 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 210108 kb
Host smart-746abe28-3fae-473c-85ab-f55509313ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588435835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1588435835
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2919158117
Short name T290
Test name
Test status
Simulation time 559510059251 ps
CPU time 899.54 seconds
Started Aug 12 06:11:50 PM PDT 24
Finished Aug 12 06:26:50 PM PDT 24
Peak memory 212256 kb
Host smart-c5f8385e-db5d-47f1-ac4b-a93997e2b09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919158117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2919158117
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3794011421
Short name T85
Test name
Test status
Simulation time 351325472320 ps
CPU time 206.75 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:15:41 PM PDT 24
Peak memory 201696 kb
Host smart-7975bb60-139e-44c6-b2cd-1b697d775020
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794011421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3794011421
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1791604345
Short name T96
Test name
Test status
Simulation time 487716079028 ps
CPU time 1114.16 seconds
Started Aug 12 06:10:05 PM PDT 24
Finished Aug 12 06:28:39 PM PDT 24
Peak memory 201664 kb
Host smart-c749d4e8-db09-43dc-b7f6-ddfc67101303
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791604345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1791604345
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2870111773
Short name T322
Test name
Test status
Simulation time 325591986782 ps
CPU time 206.23 seconds
Started Aug 12 06:10:14 PM PDT 24
Finished Aug 12 06:13:41 PM PDT 24
Peak memory 201636 kb
Host smart-5356cad1-1582-4f39-9104-2294f772dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870111773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2870111773
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1777412694
Short name T25
Test name
Test status
Simulation time 548461257873 ps
CPU time 1181.66 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 201616 kb
Host smart-aab2d7e5-fea2-428c-ae29-36bea93c2720
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777412694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1777412694
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4157714103
Short name T318
Test name
Test status
Simulation time 202004849304 ps
CPU time 252.11 seconds
Started Aug 12 06:11:05 PM PDT 24
Finished Aug 12 06:15:17 PM PDT 24
Peak memory 201808 kb
Host smart-4d777eb8-6568-4025-bc9c-94a662517229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157714103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4157714103
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1550837213
Short name T297
Test name
Test status
Simulation time 214063529494 ps
CPU time 531.6 seconds
Started Aug 12 06:12:04 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 201788 kb
Host smart-ce9ee944-18b1-4e82-9168-714de45185c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550837213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1550837213
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.943124489
Short name T241
Test name
Test status
Simulation time 576175361402 ps
CPU time 1261.57 seconds
Started Aug 12 06:09:39 PM PDT 24
Finished Aug 12 06:30:41 PM PDT 24
Peak memory 201656 kb
Host smart-6e3445ec-a6f1-47de-b11f-4b2d4cf4f4d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943124489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.943124489
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1372794172
Short name T261
Test name
Test status
Simulation time 327113634491 ps
CPU time 695.38 seconds
Started Aug 12 06:09:47 PM PDT 24
Finished Aug 12 06:21:23 PM PDT 24
Peak memory 201664 kb
Host smart-27a05cd0-d979-453e-a774-44ee0d504ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372794172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1372794172
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1851748529
Short name T177
Test name
Test status
Simulation time 528667101890 ps
CPU time 160.21 seconds
Started Aug 12 06:10:12 PM PDT 24
Finished Aug 12 06:12:52 PM PDT 24
Peak memory 201648 kb
Host smart-673aae79-4d8d-411b-80b2-5207903a00ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851748529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1851748529
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1524579013
Short name T308
Test name
Test status
Simulation time 491613442724 ps
CPU time 201.77 seconds
Started Aug 12 06:11:56 PM PDT 24
Finished Aug 12 06:15:18 PM PDT 24
Peak memory 201664 kb
Host smart-db7709c2-0125-4d0f-9c7d-a7ec153e28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524579013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1524579013
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2824690293
Short name T355
Test name
Test status
Simulation time 130200849068 ps
CPU time 457.81 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:20:27 PM PDT 24
Peak memory 201900 kb
Host smart-cb9c7734-8cc4-4b9b-a21b-a737fdae0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824690293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2824690293
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3808306906
Short name T201
Test name
Test status
Simulation time 88686178920 ps
CPU time 496.65 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:17:25 PM PDT 24
Peak memory 201984 kb
Host smart-2cdf1f1a-ef95-4e3a-855d-192b787fbd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808306906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3808306906
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2085257652
Short name T278
Test name
Test status
Simulation time 328143572355 ps
CPU time 708.95 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 201612 kb
Host smart-26739894-d4c4-4f64-ac2e-0b8e7c4ae94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085257652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2085257652
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3486816580
Short name T302
Test name
Test status
Simulation time 487006956734 ps
CPU time 493.27 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:17:41 PM PDT 24
Peak memory 201656 kb
Host smart-e23affb9-0baf-45de-ae37-75bee82169c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486816580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3486816580
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1832217606
Short name T182
Test name
Test status
Simulation time 378420935528 ps
CPU time 187.17 seconds
Started Aug 12 06:10:08 PM PDT 24
Finished Aug 12 06:13:15 PM PDT 24
Peak memory 201600 kb
Host smart-134f4263-8b2f-4c1b-b13b-4a8f81139ddf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832217606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1832217606
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1602262312
Short name T233
Test name
Test status
Simulation time 181008088952 ps
CPU time 374.8 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:18:29 PM PDT 24
Peak memory 201668 kb
Host smart-6a994425-65bd-4e04-9655-5ffb357af789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602262312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1602262312
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2908308278
Short name T320
Test name
Test status
Simulation time 166417319973 ps
CPU time 199.19 seconds
Started Aug 12 06:12:13 PM PDT 24
Finished Aug 12 06:15:33 PM PDT 24
Peak memory 201660 kb
Host smart-039a8492-618d-4200-9fde-e6196990b4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908308278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2908308278
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2285972858
Short name T731
Test name
Test status
Simulation time 16386764505 ps
CPU time 10.69 seconds
Started Aug 12 06:12:34 PM PDT 24
Finished Aug 12 06:12:44 PM PDT 24
Peak memory 211644 kb
Host smart-5bc40e7e-b16a-41df-863d-98234b5b2216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285972858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2285972858
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.820157662
Short name T30
Test name
Test status
Simulation time 492291204718 ps
CPU time 278.89 seconds
Started Aug 12 06:12:56 PM PDT 24
Finished Aug 12 06:17:35 PM PDT 24
Peak memory 201704 kb
Host smart-4e7e6edb-ffc1-4a6e-ac3b-6a663e557b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820157662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.820157662
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2407019263
Short name T69
Test name
Test status
Simulation time 387038575 ps
CPU time 1.72 seconds
Started Aug 12 05:50:24 PM PDT 24
Finished Aug 12 05:50:26 PM PDT 24
Peak memory 200956 kb
Host smart-389f8820-5d3c-426f-8bbb-2451805e9c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407019263 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2407019263
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4061074941
Short name T348
Test name
Test status
Simulation time 8414059363 ps
CPU time 12.98 seconds
Started Aug 12 05:50:38 PM PDT 24
Finished Aug 12 05:50:52 PM PDT 24
Peak memory 201216 kb
Host smart-6358c594-861c-41ad-8b05-aacb4031e993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061074941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4061074941
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1979912629
Short name T283
Test name
Test status
Simulation time 526900893671 ps
CPU time 206.68 seconds
Started Aug 12 06:08:43 PM PDT 24
Finished Aug 12 06:12:10 PM PDT 24
Peak memory 201680 kb
Host smart-2d46d00a-e39d-4af9-abd7-ec52de4a0d06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979912629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1979912629
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1910661963
Short name T281
Test name
Test status
Simulation time 325365640105 ps
CPU time 746.86 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 201688 kb
Host smart-8f196e01-4014-4730-ac50-aac4a6b610ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910661963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1910661963
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1226561319
Short name T214
Test name
Test status
Simulation time 135268275444 ps
CPU time 439.87 seconds
Started Aug 12 06:09:12 PM PDT 24
Finished Aug 12 06:16:32 PM PDT 24
Peak memory 201936 kb
Host smart-35aa2c59-7bde-403e-9728-72e2307b7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226561319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1226561319
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3109152809
Short name T242
Test name
Test status
Simulation time 525962306072 ps
CPU time 1091.5 seconds
Started Aug 12 06:09:47 PM PDT 24
Finished Aug 12 06:27:59 PM PDT 24
Peak memory 201616 kb
Host smart-3a6d06c2-e0d3-43dc-ae97-c7d4e143a6a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109152809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3109152809
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.904077062
Short name T354
Test name
Test status
Simulation time 117090470086 ps
CPU time 614.48 seconds
Started Aug 12 06:09:51 PM PDT 24
Finished Aug 12 06:20:06 PM PDT 24
Peak memory 201896 kb
Host smart-1d00adde-ce37-4f9c-a07c-48511dd030be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904077062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
904077062
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3287609362
Short name T213
Test name
Test status
Simulation time 82164837703 ps
CPU time 434.17 seconds
Started Aug 12 06:10:10 PM PDT 24
Finished Aug 12 06:17:25 PM PDT 24
Peak memory 201888 kb
Host smart-eaea2d01-24dd-4379-a9cc-a6fca522632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287609362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3287609362
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2072752034
Short name T357
Test name
Test status
Simulation time 134774964455 ps
CPU time 409.22 seconds
Started Aug 12 06:10:28 PM PDT 24
Finished Aug 12 06:17:17 PM PDT 24
Peak memory 201880 kb
Host smart-4e4c8767-8af6-4565-b264-4b0f8071f5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072752034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2072752034
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1252626183
Short name T239
Test name
Test status
Simulation time 227786464363 ps
CPU time 523.37 seconds
Started Aug 12 06:10:32 PM PDT 24
Finished Aug 12 06:19:16 PM PDT 24
Peak memory 201736 kb
Host smart-101cdb5f-763c-4189-83be-df69bfc4b80f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252626183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1252626183
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.954496457
Short name T216
Test name
Test status
Simulation time 80922685482 ps
CPU time 325.92 seconds
Started Aug 12 06:10:30 PM PDT 24
Finished Aug 12 06:15:57 PM PDT 24
Peak memory 201940 kb
Host smart-ac885fff-0753-41e7-b7ac-be526de72af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954496457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.954496457
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.828182382
Short name T202
Test name
Test status
Simulation time 301492589538 ps
CPU time 1012.02 seconds
Started Aug 12 06:10:44 PM PDT 24
Finished Aug 12 06:27:36 PM PDT 24
Peak memory 201872 kb
Host smart-c35de21f-d530-4d5b-afe4-d04abe921028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828182382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
828182382
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3707068128
Short name T263
Test name
Test status
Simulation time 177708360539 ps
CPU time 53.02 seconds
Started Aug 12 06:12:16 PM PDT 24
Finished Aug 12 06:13:09 PM PDT 24
Peak memory 201656 kb
Host smart-3c408b03-a339-4a57-b40f-60c52e2b3ff3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707068128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3707068128
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4272007499
Short name T254
Test name
Test status
Simulation time 485806453073 ps
CPU time 1171.43 seconds
Started Aug 12 06:12:44 PM PDT 24
Finished Aug 12 06:32:15 PM PDT 24
Peak memory 201692 kb
Host smart-d400cc8c-c48c-43be-80c2-6f7cf6c7f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272007499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4272007499
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3927470444
Short name T319
Test name
Test status
Simulation time 570255401014 ps
CPU time 653.01 seconds
Started Aug 12 06:12:57 PM PDT 24
Finished Aug 12 06:23:50 PM PDT 24
Peak memory 201660 kb
Host smart-b7b3a256-6d1c-4be5-a3a7-3330fa4512eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927470444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3927470444
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2622270940
Short name T264
Test name
Test status
Simulation time 354181379327 ps
CPU time 218.15 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:12:47 PM PDT 24
Peak memory 201620 kb
Host smart-3537161a-487c-4dc2-8b3c-6493d1df1ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622270940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2622270940
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1901369563
Short name T267
Test name
Test status
Simulation time 165881307933 ps
CPU time 104.33 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:10:51 PM PDT 24
Peak memory 201660 kb
Host smart-d1de268e-dccd-45bf-a055-726ea82f6db5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901369563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1901369563
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3890661821
Short name T881
Test name
Test status
Simulation time 756460346 ps
CPU time 3.97 seconds
Started Aug 12 05:50:30 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 201120 kb
Host smart-cbc5b7c1-a754-48b9-9eea-f461da28f1e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890661821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3890661821
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4261209247
Short name T848
Test name
Test status
Simulation time 26877907461 ps
CPU time 57.38 seconds
Started Aug 12 05:50:25 PM PDT 24
Finished Aug 12 05:51:23 PM PDT 24
Peak memory 201088 kb
Host smart-4c68f8c6-9f22-43ef-8c2b-6ae9a633426a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261209247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4261209247
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3901342302
Short name T825
Test name
Test status
Simulation time 902095806 ps
CPU time 1.26 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 200892 kb
Host smart-98aa19ac-c56b-49b3-b34c-aeda14d468bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901342302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3901342302
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.201224444
Short name T858
Test name
Test status
Simulation time 589444062 ps
CPU time 2.39 seconds
Started Aug 12 05:50:24 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 201012 kb
Host smart-cb30b615-9c6a-4b89-b81b-ba2ca15e545b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201224444 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.201224444
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4045573446
Short name T893
Test name
Test status
Simulation time 312868461 ps
CPU time 1.08 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 200896 kb
Host smart-bdfbd86d-5241-46bd-b62f-a19b90eb909f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045573446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4045573446
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2221639863
Short name T870
Test name
Test status
Simulation time 399651522 ps
CPU time 0.89 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 200908 kb
Host smart-3c3c566f-2ebc-4984-803d-2b8e37f8a68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221639863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2221639863
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.350488674
Short name T907
Test name
Test status
Simulation time 2435297648 ps
CPU time 2.94 seconds
Started Aug 12 05:50:28 PM PDT 24
Finished Aug 12 05:50:31 PM PDT 24
Peak memory 201032 kb
Host smart-46b90fcf-a594-42a4-80c2-e5c6955aee9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350488674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.350488674
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.994740991
Short name T879
Test name
Test status
Simulation time 8673594100 ps
CPU time 19.62 seconds
Started Aug 12 05:50:28 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 201352 kb
Host smart-b4362913-75b3-41af-97c8-6c67ae2cc361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994740991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.994740991
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.31403738
Short name T869
Test name
Test status
Simulation time 1652032374 ps
CPU time 1.63 seconds
Started Aug 12 05:50:25 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 201016 kb
Host smart-4c5b5097-963c-4d69-969c-90b28ccaa80c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasi
ng.31403738
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3912695419
Short name T118
Test name
Test status
Simulation time 3273932119 ps
CPU time 6.33 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 201136 kb
Host smart-40ee2a31-52ad-4164-b603-3ac48e2640d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912695419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3912695419
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3472906729
Short name T834
Test name
Test status
Simulation time 729535651 ps
CPU time 1.12 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 200900 kb
Host smart-10b2ca2a-f3d0-4af7-bcd3-4424a43ad30b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472906729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3472906729
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3795123878
Short name T889
Test name
Test status
Simulation time 490354772 ps
CPU time 0.9 seconds
Started Aug 12 05:50:25 PM PDT 24
Finished Aug 12 05:50:26 PM PDT 24
Peak memory 200792 kb
Host smart-eb8f51a6-52ad-42a8-8189-392f453a4710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795123878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3795123878
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4008613384
Short name T130
Test name
Test status
Simulation time 4407386997 ps
CPU time 8.06 seconds
Started Aug 12 05:50:25 PM PDT 24
Finished Aug 12 05:50:33 PM PDT 24
Peak memory 201196 kb
Host smart-a3ef2d9a-3a5a-4eed-83dc-92572e6bddd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008613384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4008613384
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.492233420
Short name T823
Test name
Test status
Simulation time 291811738 ps
CPU time 1.89 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 201216 kb
Host smart-085f3cf9-07c9-4c3b-b7fb-6e4fa412cd91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492233420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.492233420
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3993588419
Short name T863
Test name
Test status
Simulation time 8152129981 ps
CPU time 18.55 seconds
Started Aug 12 05:50:29 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 201248 kb
Host smart-3657275e-d5fa-4ee9-8b89-2ce58922a1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993588419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3993588419
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3783988674
Short name T840
Test name
Test status
Simulation time 514966176 ps
CPU time 1.48 seconds
Started Aug 12 05:50:37 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201012 kb
Host smart-7a202018-24a3-4037-bede-cba3abc82cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783988674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3783988674
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1946054622
Short name T117
Test name
Test status
Simulation time 479594994 ps
CPU time 1.42 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:44 PM PDT 24
Peak memory 200908 kb
Host smart-6a8ae1b2-fd0d-4b99-aeb1-bb3143d6f2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946054622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1946054622
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4244422217
Short name T831
Test name
Test status
Simulation time 472436950 ps
CPU time 0.78 seconds
Started Aug 12 05:50:38 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 200872 kb
Host smart-8c35660b-f35b-4202-b7aa-bed7092c1004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244422217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4244422217
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1959279835
Short name T888
Test name
Test status
Simulation time 4624779678 ps
CPU time 2.6 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 201144 kb
Host smart-7be9e6a5-c3d9-4d24-bd61-13a83c6d71f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959279835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1959279835
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3219663895
Short name T818
Test name
Test status
Simulation time 641880587 ps
CPU time 1.86 seconds
Started Aug 12 05:50:45 PM PDT 24
Finished Aug 12 05:50:47 PM PDT 24
Peak memory 201128 kb
Host smart-9f34ab71-1dfc-4fee-bcd8-333ab55b87ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219663895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3219663895
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2786078396
Short name T903
Test name
Test status
Simulation time 581120818 ps
CPU time 1.14 seconds
Started Aug 12 05:50:45 PM PDT 24
Finished Aug 12 05:50:47 PM PDT 24
Peak memory 200956 kb
Host smart-c00e7531-cd9e-49ba-a05f-9d2b277205a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786078396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2786078396
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1588466063
Short name T131
Test name
Test status
Simulation time 410353429 ps
CPU time 0.95 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 200900 kb
Host smart-751ca394-9be7-4ce7-a05c-102497e9dde2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588466063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1588466063
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3813107847
Short name T859
Test name
Test status
Simulation time 441143720 ps
CPU time 0.93 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 200896 kb
Host smart-7ed2cbd4-e6d2-4850-bf70-afdae34dae20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813107847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3813107847
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.956480763
Short name T916
Test name
Test status
Simulation time 2444501393 ps
CPU time 3.44 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:46 PM PDT 24
Peak memory 201032 kb
Host smart-367da0ce-d2b4-4933-a297-2b1fd2068aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956480763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.956480763
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1970146891
Short name T874
Test name
Test status
Simulation time 428565155 ps
CPU time 2.28 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 201152 kb
Host smart-2c5628a8-65b6-4f7c-add2-fcb1900917eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970146891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1970146891
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2100607309
Short name T837
Test name
Test status
Simulation time 456406426 ps
CPU time 1.89 seconds
Started Aug 12 05:50:41 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 201048 kb
Host smart-2329c6af-781c-4c7e-8428-946da5031b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100607309 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2100607309
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3633911118
Short name T902
Test name
Test status
Simulation time 575756817 ps
CPU time 2.06 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:44 PM PDT 24
Peak memory 200904 kb
Host smart-5b02cb4b-2c50-48f3-8e5b-1a67a087e0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633911118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3633911118
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1771689995
Short name T804
Test name
Test status
Simulation time 366834716 ps
CPU time 1.44 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:40 PM PDT 24
Peak memory 200836 kb
Host smart-21691317-c3b1-4a95-b60e-98c1c492b2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771689995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1771689995
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3976924305
Short name T867
Test name
Test status
Simulation time 2593704202 ps
CPU time 2.36 seconds
Started Aug 12 05:50:40 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 200996 kb
Host smart-2594c98f-0ab9-476a-bfea-9b5356f27274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976924305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3976924305
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3437744804
Short name T812
Test name
Test status
Simulation time 387837586 ps
CPU time 2.98 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 201188 kb
Host smart-19957c34-0fbf-4b82-8b3a-9a5532b24b39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437744804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3437744804
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3477369082
Short name T64
Test name
Test status
Simulation time 8334247230 ps
CPU time 12.69 seconds
Started Aug 12 05:50:38 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 201228 kb
Host smart-5d22db82-d9d3-44d6-ba36-998f33667054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477369082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3477369082
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.938742582
Short name T75
Test name
Test status
Simulation time 365445548 ps
CPU time 1.79 seconds
Started Aug 12 05:50:44 PM PDT 24
Finished Aug 12 05:50:46 PM PDT 24
Peak memory 200952 kb
Host smart-0914fff2-0f73-4666-982e-bd80f566b5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938742582 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.938742582
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2319732101
Short name T124
Test name
Test status
Simulation time 483789621 ps
CPU time 1.77 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:44 PM PDT 24
Peak memory 200904 kb
Host smart-95a4b93c-3e76-4a0a-8fb7-711f9fbd3fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319732101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2319732101
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2543828414
Short name T895
Test name
Test status
Simulation time 354366015 ps
CPU time 1.42 seconds
Started Aug 12 05:50:42 PM PDT 24
Finished Aug 12 05:50:44 PM PDT 24
Peak memory 200892 kb
Host smart-07fc92d0-1819-4afc-8408-f4f3ccb8b478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543828414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2543828414
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2335225559
Short name T828
Test name
Test status
Simulation time 5365098279 ps
CPU time 2.5 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 201204 kb
Host smart-f51dd557-bd47-447f-9e73-bedaf8099aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335225559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2335225559
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2858163544
Short name T92
Test name
Test status
Simulation time 593701547 ps
CPU time 1.88 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 201232 kb
Host smart-664f9341-1a48-440c-b8ce-5a38ec7bc95b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858163544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2858163544
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3153142778
Short name T346
Test name
Test status
Simulation time 8687420803 ps
CPU time 8.16 seconds
Started Aug 12 05:50:41 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 201228 kb
Host smart-db4b1525-0f1d-489b-8c12-1c24e283af1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153142778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3153142778
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3383627814
Short name T853
Test name
Test status
Simulation time 501374410 ps
CPU time 1.74 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 201052 kb
Host smart-53086a72-cf0d-4bbc-902d-624a373529a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383627814 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3383627814
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3953515464
Short name T129
Test name
Test status
Simulation time 522941362 ps
CPU time 1.37 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 200828 kb
Host smart-dfde9204-625f-44eb-9d96-6b1ef85b2758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953515464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3953515464
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3217942806
Short name T918
Test name
Test status
Simulation time 391037817 ps
CPU time 1.57 seconds
Started Aug 12 05:50:50 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 200800 kb
Host smart-f1e5ae7a-f00d-4cf6-bb92-4e51f97cda26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217942806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3217942806
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1188628657
Short name T126
Test name
Test status
Simulation time 2338938783 ps
CPU time 2.59 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 201028 kb
Host smart-643175ba-f3bd-4ce5-b19f-63177ba19a13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188628657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1188628657
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1649066865
Short name T70
Test name
Test status
Simulation time 561771831 ps
CPU time 2.64 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 201188 kb
Host smart-675f5176-50ba-4275-856d-490545da47d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649066865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1649066865
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4241202086
Short name T63
Test name
Test status
Simulation time 4349425157 ps
CPU time 11.23 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:59 PM PDT 24
Peak memory 201152 kb
Host smart-948018b8-0618-4736-94fc-e65fec80489d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241202086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4241202086
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.949502474
Short name T906
Test name
Test status
Simulation time 446146673 ps
CPU time 1.37 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 201028 kb
Host smart-cf796feb-82cc-4859-aeb9-aa7fd6f725bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949502474 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.949502474
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.620297206
Short name T868
Test name
Test status
Simulation time 530011388 ps
CPU time 1.09 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200884 kb
Host smart-c5b00f46-a299-4e93-9aed-715512620911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620297206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.620297206
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1132722357
Short name T811
Test name
Test status
Simulation time 376486084 ps
CPU time 0.87 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:50 PM PDT 24
Peak memory 200828 kb
Host smart-37cf4845-eddc-4463-b828-19ac828ee3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132722357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1132722357
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2315270498
Short name T862
Test name
Test status
Simulation time 2738860750 ps
CPU time 3.97 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:52 PM PDT 24
Peak memory 200988 kb
Host smart-cef43c0b-cf1b-4cbf-ac07-a624bf77f43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315270498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2315270498
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1020054796
Short name T850
Test name
Test status
Simulation time 620367558 ps
CPU time 2.27 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 201152 kb
Host smart-31310737-e899-4002-bcc2-a2bcbc5e1765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020054796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1020054796
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4244350645
Short name T59
Test name
Test status
Simulation time 4030775083 ps
CPU time 3.89 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:56 PM PDT 24
Peak memory 201240 kb
Host smart-75818667-cc18-40fb-81bd-12aaabedcc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244350645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4244350645
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3349851200
Short name T900
Test name
Test status
Simulation time 432800878 ps
CPU time 2.04 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 200924 kb
Host smart-152cfc66-df33-4a78-84da-69b344c16585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349851200 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3349851200
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4212467144
Short name T827
Test name
Test status
Simulation time 405848270 ps
CPU time 1.23 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:50 PM PDT 24
Peak memory 200916 kb
Host smart-2c766a9d-e68a-4565-8e64-bd16ae94c306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212467144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4212467144
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3720063925
Short name T841
Test name
Test status
Simulation time 482212907 ps
CPU time 1.17 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 200856 kb
Host smart-19f0a4bd-c74a-45a1-bdfa-cb848c414b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720063925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3720063925
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4176119855
Short name T54
Test name
Test status
Simulation time 2301564494 ps
CPU time 8.88 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 201016 kb
Host smart-c625b1e1-3b3f-4ee3-ab7e-b30e7bb4ada4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176119855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4176119855
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1755639812
Short name T875
Test name
Test status
Simulation time 386442680 ps
CPU time 2.75 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 209376 kb
Host smart-9bae0221-7ff9-48a1-b23c-1c544f1cf22b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755639812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1755639812
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1156848027
Short name T846
Test name
Test status
Simulation time 4618495523 ps
CPU time 4.05 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 201104 kb
Host smart-55b67496-90b2-46b1-9be2-2438c14ab5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156848027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1156848027
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.772190995
Short name T892
Test name
Test status
Simulation time 492319155 ps
CPU time 1.17 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:49 PM PDT 24
Peak memory 201020 kb
Host smart-055f34a8-c09b-4e55-ba0a-6fd09a8113c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772190995 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.772190995
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2138010218
Short name T116
Test name
Test status
Simulation time 530273819 ps
CPU time 0.96 seconds
Started Aug 12 05:50:50 PM PDT 24
Finished Aug 12 05:50:52 PM PDT 24
Peak memory 200932 kb
Host smart-1c4a3eed-696f-4918-984a-54a6f394e30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138010218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2138010218
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2046542094
Short name T886
Test name
Test status
Simulation time 324767793 ps
CPU time 1.33 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 200880 kb
Host smart-33cb89f4-7276-42e2-84cc-5615fd3b84bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046542094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2046542094
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1775073481
Short name T871
Test name
Test status
Simulation time 2095846399 ps
CPU time 3.13 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:56 PM PDT 24
Peak memory 200972 kb
Host smart-dd2e6339-5cb1-40d6-acd2-2e98d638fb89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775073481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1775073481
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1055934598
Short name T73
Test name
Test status
Simulation time 320791139 ps
CPU time 1.98 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 201220 kb
Host smart-4aab49d8-e7d1-4d0f-8d56-8b57c5bb45e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055934598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1055934598
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2204771218
Short name T58
Test name
Test status
Simulation time 8739295586 ps
CPU time 6.88 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 201180 kb
Host smart-e3bc953e-405a-4f08-ad90-ded0173883dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204771218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2204771218
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2979073939
Short name T817
Test name
Test status
Simulation time 535004164 ps
CPU time 1.31 seconds
Started Aug 12 05:50:49 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 200996 kb
Host smart-5c90f7f7-4c96-4f87-9059-f4e39301700b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979073939 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2979073939
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3584556504
Short name T113
Test name
Test status
Simulation time 538435253 ps
CPU time 1.34 seconds
Started Aug 12 05:50:46 PM PDT 24
Finished Aug 12 05:50:47 PM PDT 24
Peak memory 200828 kb
Host smart-d5ec4b0e-41bd-4602-ba32-68570f81fc5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584556504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3584556504
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.614228995
Short name T891
Test name
Test status
Simulation time 406852869 ps
CPU time 0.9 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 200896 kb
Host smart-70439fd7-8ec9-4d9a-aa5b-3735b3b025ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614228995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.614228995
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3115287102
Short name T876
Test name
Test status
Simulation time 4830207667 ps
CPU time 6.37 seconds
Started Aug 12 05:50:47 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 201164 kb
Host smart-bae1a498-69fa-4bbc-bb96-fe5c32db84c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115287102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3115287102
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1223914385
Short name T838
Test name
Test status
Simulation time 770575712 ps
CPU time 2.63 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:51 PM PDT 24
Peak memory 201140 kb
Host smart-5b59b3fe-88a8-447b-b04e-b6dd47559577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223914385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1223914385
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3491504556
Short name T866
Test name
Test status
Simulation time 4137014465 ps
CPU time 6.7 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 201168 kb
Host smart-85ad9388-eb47-4ba0-920b-7c9306fc90b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491504556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3491504556
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2338630392
Short name T861
Test name
Test status
Simulation time 468365056 ps
CPU time 1.53 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 201016 kb
Host smart-8e25bb64-de6f-45fc-a94c-3afca3b4541f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338630392 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2338630392
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.433041795
Short name T125
Test name
Test status
Simulation time 345864614 ps
CPU time 1.59 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200884 kb
Host smart-21b6cc11-acce-4071-ab81-5c970eba3231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433041795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.433041795
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1782320481
Short name T844
Test name
Test status
Simulation time 461009840 ps
CPU time 1.71 seconds
Started Aug 12 05:50:48 PM PDT 24
Finished Aug 12 05:50:50 PM PDT 24
Peak memory 200916 kb
Host smart-d026007c-a8dd-4a28-83de-c40df6510a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782320481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1782320481
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2664791587
Short name T851
Test name
Test status
Simulation time 5192642622 ps
CPU time 3.69 seconds
Started Aug 12 05:50:57 PM PDT 24
Finished Aug 12 05:51:01 PM PDT 24
Peak memory 201216 kb
Host smart-1949dd1b-386f-453d-b742-473f2e44bf2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664791587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2664791587
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2029099470
Short name T915
Test name
Test status
Simulation time 595219532 ps
CPU time 3.19 seconds
Started Aug 12 05:50:49 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 216992 kb
Host smart-6a65a1f7-b00c-4d5b-8597-1c70d4328a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029099470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2029099470
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2806938872
Short name T345
Test name
Test status
Simulation time 4104486592 ps
CPU time 3.03 seconds
Started Aug 12 05:50:50 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 201084 kb
Host smart-b84096c0-5790-4826-9c2d-e23001cff6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806938872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2806938872
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.602389065
Short name T887
Test name
Test status
Simulation time 1160437479 ps
CPU time 5.28 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 201020 kb
Host smart-60ceb8d1-a5ae-4362-8f2d-d28171f0a26e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602389065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.602389065
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1646483408
Short name T908
Test name
Test status
Simulation time 51146550287 ps
CPU time 24.67 seconds
Started Aug 12 05:50:35 PM PDT 24
Finished Aug 12 05:51:00 PM PDT 24
Peak memory 201136 kb
Host smart-2112035f-ad02-41b9-aa3f-f54f2c8e7f94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646483408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1646483408
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3268885053
Short name T897
Test name
Test status
Simulation time 1526281299 ps
CPU time 1.31 seconds
Started Aug 12 05:50:27 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 200892 kb
Host smart-35a6d81e-ffdb-4850-83b1-f08262901409
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268885053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3268885053
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.164734501
Short name T882
Test name
Test status
Simulation time 499484275 ps
CPU time 2.1 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 201036 kb
Host smart-4dbc2a3f-a9bf-457e-a373-7576e4c3fa58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164734501 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.164734501
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2287385559
Short name T119
Test name
Test status
Simulation time 424385995 ps
CPU time 1.81 seconds
Started Aug 12 05:50:27 PM PDT 24
Finished Aug 12 05:50:29 PM PDT 24
Peak memory 200888 kb
Host smart-a8672d35-7313-4a8c-a829-c2a81438b9f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287385559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2287385559
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3799129310
Short name T807
Test name
Test status
Simulation time 343777055 ps
CPU time 1.43 seconds
Started Aug 12 05:50:26 PM PDT 24
Finished Aug 12 05:50:27 PM PDT 24
Peak memory 200848 kb
Host smart-997c6276-035c-4097-b716-b9eaa7e77d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799129310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3799129310
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3428684798
Short name T899
Test name
Test status
Simulation time 2268700138 ps
CPU time 4.59 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 201092 kb
Host smart-24624bd3-7e01-4ba1-b760-a856e3af8ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428684798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3428684798
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2641859530
Short name T102
Test name
Test status
Simulation time 603727788 ps
CPU time 2.93 seconds
Started Aug 12 05:50:27 PM PDT 24
Finished Aug 12 05:50:30 PM PDT 24
Peak memory 209376 kb
Host smart-f15e20a7-6e7a-4ce1-843f-2c954aaac16d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641859530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2641859530
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3850562353
Short name T347
Test name
Test status
Simulation time 4070724779 ps
CPU time 10.66 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 201200 kb
Host smart-b260ad87-30e2-4b1f-9388-e819c95f4f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850562353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3850562353
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4274795287
Short name T830
Test name
Test status
Simulation time 516545317 ps
CPU time 1.6 seconds
Started Aug 12 05:50:55 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200904 kb
Host smart-4b4ec4f4-4862-4826-80f6-9b62b4cebbc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274795287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4274795287
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2794874414
Short name T826
Test name
Test status
Simulation time 531747983 ps
CPU time 1.27 seconds
Started Aug 12 05:51:00 PM PDT 24
Finished Aug 12 05:51:01 PM PDT 24
Peak memory 200888 kb
Host smart-7476a8c5-f1e0-45f3-9bfd-c89090e28ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794874414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2794874414
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.594536745
Short name T836
Test name
Test status
Simulation time 454669387 ps
CPU time 0.94 seconds
Started Aug 12 05:50:54 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200904 kb
Host smart-100ec9a3-1c2a-4c53-a33a-16ae25abadd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594536745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.594536745
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2270023213
Short name T864
Test name
Test status
Simulation time 349233568 ps
CPU time 1.47 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200916 kb
Host smart-4cc79299-89c3-474f-9693-a3e557285aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270023213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2270023213
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1252053677
Short name T822
Test name
Test status
Simulation time 432968048 ps
CPU time 0.92 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200856 kb
Host smart-c9b56a6c-b424-4bc9-817d-df4adaf5806e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252053677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1252053677
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2073780486
Short name T852
Test name
Test status
Simulation time 444810098 ps
CPU time 1.14 seconds
Started Aug 12 05:50:57 PM PDT 24
Finished Aug 12 05:50:58 PM PDT 24
Peak memory 200896 kb
Host smart-4f03e093-a361-40e8-83bd-3d760fe8e0e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073780486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2073780486
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3931863516
Short name T894
Test name
Test status
Simulation time 373511879 ps
CPU time 1.48 seconds
Started Aug 12 05:50:59 PM PDT 24
Finished Aug 12 05:51:00 PM PDT 24
Peak memory 200900 kb
Host smart-0bcc2c11-fb79-4943-b0bb-db4adeefbd0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931863516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3931863516
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1518196937
Short name T829
Test name
Test status
Simulation time 495224095 ps
CPU time 1.72 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200884 kb
Host smart-99473bbd-8fb5-44e1-8e15-70bf4bb99986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518196937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1518196937
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2025116632
Short name T824
Test name
Test status
Simulation time 534103167 ps
CPU time 0.99 seconds
Started Aug 12 05:50:54 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200856 kb
Host smart-f106f4e3-9ae0-4af3-a4b7-42fb2da821c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025116632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2025116632
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2401864339
Short name T800
Test name
Test status
Simulation time 586104406 ps
CPU time 0.73 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200852 kb
Host smart-2402366f-86d9-4a94-800a-973e14483bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401864339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2401864339
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.527011825
Short name T114
Test name
Test status
Simulation time 837642093 ps
CPU time 1.93 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 201020 kb
Host smart-2071c3dd-e4aa-4ce6-81cd-d45c84598590
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527011825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.527011825
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1772125748
Short name T914
Test name
Test status
Simulation time 1427688801 ps
CPU time 1.01 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:33 PM PDT 24
Peak memory 200800 kb
Host smart-439b6207-119b-4c88-afe5-af2ebe7d4a69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772125748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1772125748
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2960803002
Short name T813
Test name
Test status
Simulation time 450113385 ps
CPU time 1.21 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 201028 kb
Host smart-42a33ce3-f8c1-4154-8227-dba78c88b203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960803002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2960803002
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2325658532
Short name T121
Test name
Test status
Simulation time 343261059 ps
CPU time 1.57 seconds
Started Aug 12 05:50:31 PM PDT 24
Finished Aug 12 05:50:32 PM PDT 24
Peak memory 200868 kb
Host smart-bc62caeb-4847-474d-952b-ac27e43c15d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325658532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2325658532
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2369307127
Short name T814
Test name
Test status
Simulation time 282189307 ps
CPU time 1.25 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 200904 kb
Host smart-1ff4c457-2ba3-4ad5-81d0-edb811333822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369307127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2369307127
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3531957747
Short name T128
Test name
Test status
Simulation time 2562729334 ps
CPU time 8.1 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:47 PM PDT 24
Peak memory 201012 kb
Host smart-e588fa8e-ebea-4c36-91ee-48320abc5774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531957747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3531957747
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1033831723
Short name T74
Test name
Test status
Simulation time 371962233 ps
CPU time 2.2 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:36 PM PDT 24
Peak memory 201176 kb
Host smart-1ade6f34-c020-43f4-b58b-94f5a7680456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033831723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1033831723
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1040740209
Short name T901
Test name
Test status
Simulation time 3976651616 ps
CPU time 6.45 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:45 PM PDT 24
Peak memory 200428 kb
Host smart-898fd7ed-48ae-4cec-9023-451b00553c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040740209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1040740209
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.716964678
Short name T815
Test name
Test status
Simulation time 482684320 ps
CPU time 1.23 seconds
Started Aug 12 05:50:58 PM PDT 24
Finished Aug 12 05:51:00 PM PDT 24
Peak memory 200904 kb
Host smart-5a820ced-3273-469e-aa92-44c48fb36e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716964678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.716964678
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2138588203
Short name T854
Test name
Test status
Simulation time 341055357 ps
CPU time 1.42 seconds
Started Aug 12 05:50:58 PM PDT 24
Finished Aug 12 05:51:00 PM PDT 24
Peak memory 200808 kb
Host smart-680fd44c-9ecf-4151-8121-7070dc1e2065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138588203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2138588203
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1602575755
Short name T806
Test name
Test status
Simulation time 483180703 ps
CPU time 1.78 seconds
Started Aug 12 05:51:00 PM PDT 24
Finished Aug 12 05:51:02 PM PDT 24
Peak memory 200916 kb
Host smart-92610ffd-12b3-4a6b-a88f-ae6c40c6d3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602575755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1602575755
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2028469664
Short name T913
Test name
Test status
Simulation time 329369694 ps
CPU time 0.81 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 201040 kb
Host smart-f22a6dc1-0e32-435e-b330-1296b165f170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028469664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2028469664
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2895584339
Short name T845
Test name
Test status
Simulation time 394023385 ps
CPU time 1.47 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200880 kb
Host smart-1244eb59-accf-4c04-8599-0ebb7faf5c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895584339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2895584339
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3468370414
Short name T896
Test name
Test status
Simulation time 312181297 ps
CPU time 0.83 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200896 kb
Host smart-50f8a5c7-1698-47d0-84b7-80eef40e625a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468370414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3468370414
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.116822317
Short name T904
Test name
Test status
Simulation time 355655331 ps
CPU time 1.46 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200912 kb
Host smart-7e1f328c-84a2-4471-9937-81ddf7f263bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116822317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.116822317
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.497854068
Short name T810
Test name
Test status
Simulation time 343647908 ps
CPU time 1.36 seconds
Started Aug 12 05:50:52 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200824 kb
Host smart-208c3a4e-c477-4471-87b6-52cc3a16e79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497854068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.497854068
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1132568983
Short name T832
Test name
Test status
Simulation time 470034086 ps
CPU time 0.91 seconds
Started Aug 12 05:50:59 PM PDT 24
Finished Aug 12 05:51:00 PM PDT 24
Peak memory 200808 kb
Host smart-7c8b54d0-1473-4ea3-8e84-ddb7e7206868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132568983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1132568983
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3292296223
Short name T835
Test name
Test status
Simulation time 374362233 ps
CPU time 1.48 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:58 PM PDT 24
Peak memory 200864 kb
Host smart-36284a86-4334-41d9-a4ab-a0720e1512b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292296223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3292296223
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2650227177
Short name T912
Test name
Test status
Simulation time 1366290607 ps
CPU time 6.11 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 201064 kb
Host smart-9ea49a74-c3f9-4ccb-b393-2100f841d337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650227177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2650227177
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2618784129
Short name T123
Test name
Test status
Simulation time 9869402685 ps
CPU time 18.03 seconds
Started Aug 12 05:50:37 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 201144 kb
Host smart-16dddff9-71be-42cc-b370-65ed7c0b1a22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618784129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2618784129
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.923456779
Short name T917
Test name
Test status
Simulation time 1327862538 ps
CPU time 1.46 seconds
Started Aug 12 05:50:31 PM PDT 24
Finished Aug 12 05:50:32 PM PDT 24
Peak memory 200904 kb
Host smart-e2e16ff6-f28f-47fb-9548-d961c187bf4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923456779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.923456779
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2280016111
Short name T855
Test name
Test status
Simulation time 507413846 ps
CPU time 1.23 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 201004 kb
Host smart-162defa9-508f-4e4d-90fa-592f8591ce88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280016111 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2280016111
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3301376707
Short name T849
Test name
Test status
Simulation time 408077060 ps
CPU time 1.74 seconds
Started Aug 12 05:50:37 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 200928 kb
Host smart-6d113b74-036d-45ea-ba51-05e9a4593c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301376707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3301376707
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3013324431
Short name T839
Test name
Test status
Simulation time 469431880 ps
CPU time 0.88 seconds
Started Aug 12 05:50:36 PM PDT 24
Finished Aug 12 05:50:37 PM PDT 24
Peak memory 200876 kb
Host smart-68ae5b7d-e9c5-416f-99d1-055d2996d52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013324431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3013324431
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2178765742
Short name T865
Test name
Test status
Simulation time 4696193863 ps
CPU time 5.46 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 201180 kb
Host smart-9b896eed-226a-4fba-af54-e4a2c9c86a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178765742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2178765742
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3068122781
Short name T857
Test name
Test status
Simulation time 608641161 ps
CPU time 2.06 seconds
Started Aug 12 05:50:36 PM PDT 24
Finished Aug 12 05:50:38 PM PDT 24
Peak memory 217144 kb
Host smart-d06ecefb-2961-4e21-a95e-5090e4dc24aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068122781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3068122781
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2840394757
Short name T842
Test name
Test status
Simulation time 7628918121 ps
CPU time 18.28 seconds
Started Aug 12 05:50:35 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 201160 kb
Host smart-82fd827a-1db5-47b0-9db6-b6bfc0769c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840394757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2840394757
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1303587365
Short name T883
Test name
Test status
Simulation time 483379463 ps
CPU time 1.31 seconds
Started Aug 12 05:51:00 PM PDT 24
Finished Aug 12 05:51:01 PM PDT 24
Peak memory 200852 kb
Host smart-7b369958-0044-4fdc-aa14-7e8f01771ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303587365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1303587365
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2989264067
Short name T802
Test name
Test status
Simulation time 529600761 ps
CPU time 1.96 seconds
Started Aug 12 05:50:54 PM PDT 24
Finished Aug 12 05:50:56 PM PDT 24
Peak memory 200832 kb
Host smart-7e9a7008-339b-4ee7-b26e-e6ad3061ec11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989264067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2989264067
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2393294088
Short name T820
Test name
Test status
Simulation time 327824366 ps
CPU time 0.83 seconds
Started Aug 12 05:50:57 PM PDT 24
Finished Aug 12 05:50:58 PM PDT 24
Peak memory 200896 kb
Host smart-48aad60d-1fb2-46d3-b8cb-48423e349bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393294088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2393294088
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.391994965
Short name T816
Test name
Test status
Simulation time 398087857 ps
CPU time 0.85 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200852 kb
Host smart-bf9e7a4a-84d0-4a0b-95b0-678bfa4ad68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391994965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.391994965
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3032053826
Short name T872
Test name
Test status
Simulation time 498778266 ps
CPU time 0.88 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:54 PM PDT 24
Peak memory 200912 kb
Host smart-580a6c9e-219d-4534-8c4c-284311bcfd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032053826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3032053826
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.109828980
Short name T799
Test name
Test status
Simulation time 420858116 ps
CPU time 1.13 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200916 kb
Host smart-4d3f994a-2304-4d44-8a9b-d10c19d8640f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109828980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.109828980
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1546579780
Short name T803
Test name
Test status
Simulation time 534318814 ps
CPU time 1.07 seconds
Started Aug 12 05:50:55 PM PDT 24
Finished Aug 12 05:50:56 PM PDT 24
Peak memory 200880 kb
Host smart-8f894822-f364-4c78-bbdc-cb72281f5aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546579780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1546579780
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2867605498
Short name T801
Test name
Test status
Simulation time 287890354 ps
CPU time 1.23 seconds
Started Aug 12 05:50:55 PM PDT 24
Finished Aug 12 05:50:57 PM PDT 24
Peak memory 200904 kb
Host smart-6bd49b42-5aef-4856-bb43-2e3b37fed773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867605498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2867605498
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2992287383
Short name T798
Test name
Test status
Simulation time 410806672 ps
CPU time 1.08 seconds
Started Aug 12 05:50:53 PM PDT 24
Finished Aug 12 05:50:55 PM PDT 24
Peak memory 200852 kb
Host smart-edc8ecf9-de4c-4a4a-b119-6cf046616891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992287383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2992287383
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1725508389
Short name T809
Test name
Test status
Simulation time 466954863 ps
CPU time 1.66 seconds
Started Aug 12 05:50:56 PM PDT 24
Finished Aug 12 05:50:58 PM PDT 24
Peak memory 200888 kb
Host smart-f09bb01f-ef38-4242-80f3-d9021fdcb9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725508389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1725508389
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1933326962
Short name T884
Test name
Test status
Simulation time 427338300 ps
CPU time 2.09 seconds
Started Aug 12 05:50:31 PM PDT 24
Finished Aug 12 05:50:33 PM PDT 24
Peak memory 201040 kb
Host smart-40de4033-b940-46c8-8798-7acbbc877e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933326962 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1933326962
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.950562482
Short name T885
Test name
Test status
Simulation time 382313115 ps
CPU time 1.68 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 200860 kb
Host smart-9ab8e55a-e126-4fbb-ad54-7940c1ff69ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950562482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.950562482
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.768466839
Short name T878
Test name
Test status
Simulation time 504799964 ps
CPU time 1.67 seconds
Started Aug 12 05:50:35 PM PDT 24
Finished Aug 12 05:50:37 PM PDT 24
Peak memory 200824 kb
Host smart-ae863406-a943-45de-9dcb-41659f5e70ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768466839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.768466839
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2821868336
Short name T890
Test name
Test status
Simulation time 4448709207 ps
CPU time 3.11 seconds
Started Aug 12 05:50:35 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201164 kb
Host smart-f85c3a9e-c1e4-42a0-a3ac-46f1536eebb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821868336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2821868336
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4258078337
Short name T909
Test name
Test status
Simulation time 316619096 ps
CPU time 2.77 seconds
Started Aug 12 05:50:31 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 201216 kb
Host smart-a4ffde10-ef05-471e-9ad1-95a3504125e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258078337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4258078337
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.594988965
Short name T57
Test name
Test status
Simulation time 4621573639 ps
CPU time 7.21 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201196 kb
Host smart-4b3a7731-43c8-4c9a-8d4f-422c3b9b6d74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594988965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.594988965
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.575242210
Short name T880
Test name
Test status
Simulation time 488729934 ps
CPU time 1.15 seconds
Started Aug 12 05:50:37 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201036 kb
Host smart-9f881b8a-3191-4764-86b1-5e4dcf2a46f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575242210 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.575242210
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3570217985
Short name T122
Test name
Test status
Simulation time 556825633 ps
CPU time 1.08 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 200892 kb
Host smart-b93c7a56-c6b7-4858-8bb6-4d67d09c341d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570217985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3570217985
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1051176378
Short name T910
Test name
Test status
Simulation time 528468443 ps
CPU time 2.01 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 200912 kb
Host smart-eb98aa0a-fe8f-4273-bbec-96e06c73b37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051176378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1051176378
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2033830427
Short name T56
Test name
Test status
Simulation time 4432168171 ps
CPU time 10.36 seconds
Started Aug 12 05:50:35 PM PDT 24
Finished Aug 12 05:50:45 PM PDT 24
Peak memory 201200 kb
Host smart-c43b1d3f-586f-465b-88a3-66156485697b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033830427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2033830427
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1092249115
Short name T819
Test name
Test status
Simulation time 518279152 ps
CPU time 1.65 seconds
Started Aug 12 05:50:33 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 201192 kb
Host smart-54f42bde-1b97-45ca-a488-c69334ae9b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092249115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1092249115
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2275650499
Short name T78
Test name
Test status
Simulation time 4623068224 ps
CPU time 4.75 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201156 kb
Host smart-c44c6af6-d505-447c-9895-70e6d09e536d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275650499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2275650499
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2644921696
Short name T833
Test name
Test status
Simulation time 649410181 ps
CPU time 0.95 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:35 PM PDT 24
Peak memory 201024 kb
Host smart-99f0a9ee-86b9-4d3d-b07d-bd236bb0b5dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644921696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2644921696
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.717030669
Short name T120
Test name
Test status
Simulation time 574685771 ps
CPU time 1.15 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:33 PM PDT 24
Peak memory 201040 kb
Host smart-4001375d-184b-47ee-9679-395cb79e8332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717030669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.717030669
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.983978620
Short name T805
Test name
Test status
Simulation time 471150243 ps
CPU time 0.9 seconds
Started Aug 12 05:50:31 PM PDT 24
Finished Aug 12 05:50:32 PM PDT 24
Peak memory 200908 kb
Host smart-481901fc-ca1b-4ad6-bbd4-e46d7fa2a723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983978620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.983978620
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1236323066
Short name T860
Test name
Test status
Simulation time 2806975246 ps
CPU time 3.89 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:36 PM PDT 24
Peak memory 200968 kb
Host smart-ee49b992-92a8-4be6-b538-3e1b23d5664a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236323066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1236323066
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1426868257
Short name T821
Test name
Test status
Simulation time 399716976 ps
CPU time 2.28 seconds
Started Aug 12 05:50:32 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 201208 kb
Host smart-c4198eef-4be4-492b-8c69-b9a477fdb29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426868257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1426868257
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3712406300
Short name T843
Test name
Test status
Simulation time 4484758395 ps
CPU time 6.68 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 201200 kb
Host smart-14c84780-4beb-4b82-9bdb-743d6c22e75f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712406300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3712406300
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.314189396
Short name T76
Test name
Test status
Simulation time 448189101 ps
CPU time 1.36 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 201008 kb
Host smart-20e5ca9d-9e7d-48a0-96fe-a6bfc39b939b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314189396 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.314189396
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1649868711
Short name T873
Test name
Test status
Simulation time 358668414 ps
CPU time 1.62 seconds
Started Aug 12 05:50:41 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 200932 kb
Host smart-8f0fa155-58c6-4a7a-8194-0ef8368dbc6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649868711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1649868711
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2306301486
Short name T808
Test name
Test status
Simulation time 362148660 ps
CPU time 0.77 seconds
Started Aug 12 05:50:41 PM PDT 24
Finished Aug 12 05:50:42 PM PDT 24
Peak memory 200884 kb
Host smart-abf2e4ca-f23a-48c9-a8ce-2e48568d591e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306301486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2306301486
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2734030494
Short name T905
Test name
Test status
Simulation time 4398253336 ps
CPU time 2.4 seconds
Started Aug 12 05:50:38 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 201144 kb
Host smart-a18bc1b2-62cd-41e1-9afa-edbc40ca0ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734030494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2734030494
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2090106732
Short name T68
Test name
Test status
Simulation time 415788359 ps
CPU time 1.77 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 200388 kb
Host smart-9c1cead6-f4a7-4ede-8e0f-ecbef00cc9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090106732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2090106732
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3887137541
Short name T911
Test name
Test status
Simulation time 4692816439 ps
CPU time 4.43 seconds
Started Aug 12 05:50:34 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 201200 kb
Host smart-fb87faf4-a832-402c-a773-61893fddd09d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887137541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3887137541
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3792306505
Short name T877
Test name
Test status
Simulation time 660027580 ps
CPU time 1.35 seconds
Started Aug 12 05:50:38 PM PDT 24
Finished Aug 12 05:50:40 PM PDT 24
Peak memory 209448 kb
Host smart-94189fce-41a0-4586-a087-c904f440865d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792306505 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3792306505
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2166274139
Short name T856
Test name
Test status
Simulation time 472423475 ps
CPU time 1.97 seconds
Started Aug 12 05:50:44 PM PDT 24
Finished Aug 12 05:50:46 PM PDT 24
Peak memory 200792 kb
Host smart-aa9a006e-11f6-4480-805b-9e6078ceb408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166274139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2166274139
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1113436554
Short name T847
Test name
Test status
Simulation time 382504234 ps
CPU time 1.44 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 200900 kb
Host smart-9f46f438-ccef-481a-8ef6-aa570ec5ccda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113436554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1113436554
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4186371776
Short name T127
Test name
Test status
Simulation time 4524257095 ps
CPU time 23.21 seconds
Started Aug 12 05:50:39 PM PDT 24
Finished Aug 12 05:51:02 PM PDT 24
Peak memory 201192 kb
Host smart-f19a8190-a271-4ff4-8be4-39d47582bb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186371776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4186371776
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3802173517
Short name T898
Test name
Test status
Simulation time 4531822306 ps
CPU time 12.01 seconds
Started Aug 12 05:50:41 PM PDT 24
Finished Aug 12 05:50:53 PM PDT 24
Peak memory 201236 kb
Host smart-7855932d-0e80-48d0-ad91-3e0e0c83508c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802173517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3802173517
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2667416784
Short name T256
Test name
Test status
Simulation time 495572272545 ps
CPU time 1156.39 seconds
Started Aug 12 06:08:44 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 201660 kb
Host smart-88210bcf-40bc-45d5-b1dc-fcdeb67643a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667416784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2667416784
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2392080059
Short name T757
Test name
Test status
Simulation time 482782964116 ps
CPU time 1114.95 seconds
Started Aug 12 06:08:43 PM PDT 24
Finished Aug 12 06:27:18 PM PDT 24
Peak memory 201660 kb
Host smart-90bba9f4-3f47-4a95-a5a4-2d9b81569302
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392080059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2392080059
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2097182997
Short name T595
Test name
Test status
Simulation time 325063122827 ps
CPU time 132.24 seconds
Started Aug 12 06:08:43 PM PDT 24
Finished Aug 12 06:10:55 PM PDT 24
Peak memory 201648 kb
Host smart-ff31fa8a-ff08-47d8-a258-b48f4719f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097182997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2097182997
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1538414836
Short name T157
Test name
Test status
Simulation time 164753175730 ps
CPU time 79.13 seconds
Started Aug 12 06:08:46 PM PDT 24
Finished Aug 12 06:10:06 PM PDT 24
Peak memory 201648 kb
Host smart-2a5d6ee2-dfd6-40a8-acb2-68571f827261
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538414836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1538414836
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1179017922
Short name T630
Test name
Test status
Simulation time 169269426198 ps
CPU time 85.6 seconds
Started Aug 12 06:08:42 PM PDT 24
Finished Aug 12 06:10:08 PM PDT 24
Peak memory 201640 kb
Host smart-ab65d1a0-07c4-4eee-8abc-7e27db4e410c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179017922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1179017922
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2760984579
Short name T211
Test name
Test status
Simulation time 130806357264 ps
CPU time 512.63 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:17:21 PM PDT 24
Peak memory 201916 kb
Host smart-01904816-7a26-45b1-a35d-e338c75a1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760984579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2760984579
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2448401841
Short name T610
Test name
Test status
Simulation time 35369931531 ps
CPU time 12.29 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:09:02 PM PDT 24
Peak memory 201504 kb
Host smart-4608fc90-f254-411b-b655-05652398349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448401841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2448401841
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2439342344
Short name T511
Test name
Test status
Simulation time 4088421462 ps
CPU time 3.12 seconds
Started Aug 12 06:08:40 PM PDT 24
Finished Aug 12 06:08:44 PM PDT 24
Peak memory 201484 kb
Host smart-3c387250-17e1-4635-ae3d-185eda45290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439342344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2439342344
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1001909568
Short name T760
Test name
Test status
Simulation time 5962378472 ps
CPU time 4.51 seconds
Started Aug 12 06:08:45 PM PDT 24
Finished Aug 12 06:08:50 PM PDT 24
Peak memory 201504 kb
Host smart-5792f4b9-c14e-4e74-a9bb-fdd95a603282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001909568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1001909568
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1705083937
Short name T226
Test name
Test status
Simulation time 354298574973 ps
CPU time 834.51 seconds
Started Aug 12 06:08:45 PM PDT 24
Finished Aug 12 06:22:40 PM PDT 24
Peak memory 201656 kb
Host smart-a1cebe4a-c400-41b0-876f-f8832cbbb85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705083937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1705083937
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3509211394
Short name T634
Test name
Test status
Simulation time 3787558623 ps
CPU time 11.03 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:09:00 PM PDT 24
Peak memory 209900 kb
Host smart-2e4de035-e467-4fcb-8f1b-48b4f346069c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509211394 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3509211394
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.624721249
Short name T500
Test name
Test status
Simulation time 328177845 ps
CPU time 0.78 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:08:49 PM PDT 24
Peak memory 201444 kb
Host smart-46af054c-46ac-4927-80dc-f4c050ca3431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624721249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.624721249
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3805470753
Short name T132
Test name
Test status
Simulation time 191742008239 ps
CPU time 422.96 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:15:53 PM PDT 24
Peak memory 201684 kb
Host smart-a8ade34e-3f65-4e6a-90bb-480b6b46b3ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805470753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3805470753
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.202619163
Short name T703
Test name
Test status
Simulation time 325085640605 ps
CPU time 334.92 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:14:28 PM PDT 24
Peak memory 201608 kb
Host smart-bd9fe2d5-7d80-4424-978a-3fa1db320895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202619163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.202619163
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2203960415
Short name T453
Test name
Test status
Simulation time 165777684286 ps
CPU time 402.57 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:15:37 PM PDT 24
Peak memory 201680 kb
Host smart-d0be3436-649f-482c-a631-79e4f6d400d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203960415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2203960415
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1090031628
Short name T582
Test name
Test status
Simulation time 330607846099 ps
CPU time 402.22 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:15:31 PM PDT 24
Peak memory 201640 kb
Host smart-7acd9b02-9140-40bb-bc07-8896e4a0cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090031628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1090031628
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1891143457
Short name T644
Test name
Test status
Simulation time 167789717313 ps
CPU time 205.18 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:12:17 PM PDT 24
Peak memory 201580 kb
Host smart-da8a6ee8-0716-4107-ba93-3cae0478a1f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891143457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1891143457
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.811023230
Short name T792
Test name
Test status
Simulation time 172003617287 ps
CPU time 104.75 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:10:34 PM PDT 24
Peak memory 201716 kb
Host smart-644efc61-3133-406d-8841-0a6da8f552ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811023230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.811023230
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1098695546
Short name T533
Test name
Test status
Simulation time 609954931989 ps
CPU time 750.44 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 201644 kb
Host smart-3c495d36-a3f9-4629-a7a5-245e0a43c0c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098695546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1098695546
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3841789194
Short name T579
Test name
Test status
Simulation time 116920163389 ps
CPU time 394.38 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:15:31 PM PDT 24
Peak memory 201892 kb
Host smart-09dbd1e4-b639-44b5-8fcb-44958915e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841789194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3841789194
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.595982008
Short name T391
Test name
Test status
Simulation time 32801067822 ps
CPU time 79.4 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:10:08 PM PDT 24
Peak memory 201488 kb
Host smart-e23dcd9d-4667-46b9-b698-45885f919ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595982008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.595982008
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2214465184
Short name T715
Test name
Test status
Simulation time 5245882733 ps
CPU time 9.07 seconds
Started Aug 12 06:08:47 PM PDT 24
Finished Aug 12 06:08:56 PM PDT 24
Peak memory 201484 kb
Host smart-267569b6-4991-4d86-aced-7c94b161314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214465184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2214465184
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.288816712
Short name T67
Test name
Test status
Simulation time 7653313805 ps
CPU time 18.93 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:09:08 PM PDT 24
Peak memory 218128 kb
Host smart-6fbd962c-7ea1-47e8-a7e3-7a6eed4c4281
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288816712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.288816712
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4118949597
Short name T647
Test name
Test status
Simulation time 6052262273 ps
CPU time 8.88 seconds
Started Aug 12 06:08:47 PM PDT 24
Finished Aug 12 06:08:56 PM PDT 24
Peak memory 201448 kb
Host smart-ca330302-7ed7-425e-83ad-5d49195ed02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118949597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4118949597
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.833782917
Short name T667
Test name
Test status
Simulation time 630793611613 ps
CPU time 1966.61 seconds
Started Aug 12 06:08:51 PM PDT 24
Finished Aug 12 06:41:38 PM PDT 24
Peak memory 201964 kb
Host smart-a49e414b-83f6-4c27-8311-b1c920370a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833782917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.833782917
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.795190222
Short name T544
Test name
Test status
Simulation time 2819163027 ps
CPU time 8.06 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:08:59 PM PDT 24
Peak memory 209944 kb
Host smart-3061016b-6f18-4b15-9000-f09e2989708c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795190222 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.795190222
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3336633077
Short name T72
Test name
Test status
Simulation time 418936628 ps
CPU time 0.78 seconds
Started Aug 12 06:09:09 PM PDT 24
Finished Aug 12 06:09:10 PM PDT 24
Peak memory 201460 kb
Host smart-9fcbc40a-c40e-46be-8e00-5749914e690f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336633077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3336633077
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4044379874
Short name T282
Test name
Test status
Simulation time 349282456780 ps
CPU time 201.12 seconds
Started Aug 12 06:09:12 PM PDT 24
Finished Aug 12 06:12:33 PM PDT 24
Peak memory 201704 kb
Host smart-bb347ce8-1a52-4b01-9e80-079a62c7b613
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044379874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4044379874
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.499747172
Short name T291
Test name
Test status
Simulation time 491004755301 ps
CPU time 165.9 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:11:54 PM PDT 24
Peak memory 201692 kb
Host smart-4df32a1d-a2e7-48e0-901e-c1cff3f916fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499747172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.499747172
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2236774600
Short name T296
Test name
Test status
Simulation time 486916174368 ps
CPU time 300.93 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:14:14 PM PDT 24
Peak memory 201680 kb
Host smart-a52fcac4-775f-4c29-b2ab-5d215fa5c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236774600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2236774600
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4142537589
Short name T694
Test name
Test status
Simulation time 326682537337 ps
CPU time 192.34 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:12:20 PM PDT 24
Peak memory 201712 kb
Host smart-75e656f5-49e7-4a60-8c0d-69ab26eb6c20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142537589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4142537589
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3607798014
Short name T495
Test name
Test status
Simulation time 164701540017 ps
CPU time 291.96 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:14:03 PM PDT 24
Peak memory 201604 kb
Host smart-1ccf32d3-d7d8-43f9-87b8-077e063f2dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607798014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3607798014
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.301816491
Short name T685
Test name
Test status
Simulation time 164001821109 ps
CPU time 46.95 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:09:54 PM PDT 24
Peak memory 201636 kb
Host smart-b26163db-0b3b-4ffd-9b76-5f4f3e039042
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=301816491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.301816491
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3491910312
Short name T796
Test name
Test status
Simulation time 253397374192 ps
CPU time 146.13 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:11:39 PM PDT 24
Peak memory 201588 kb
Host smart-a0594f40-eaa0-437d-9b38-28b0a8d5f914
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491910312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3491910312
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3943513714
Short name T657
Test name
Test status
Simulation time 388733554437 ps
CPU time 781.01 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 201660 kb
Host smart-069632db-494d-4d1c-83ce-69bdcc039b57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943513714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3943513714
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2454943255
Short name T436
Test name
Test status
Simulation time 84421892969 ps
CPU time 299.87 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:14:08 PM PDT 24
Peak memory 201928 kb
Host smart-7a9b4c6b-d911-48fe-9715-b6a24fa5ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454943255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2454943255
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1207501633
Short name T413
Test name
Test status
Simulation time 33263559390 ps
CPU time 23.67 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:09:34 PM PDT 24
Peak memory 201484 kb
Host smart-b6ec5413-eacb-4fd3-a579-b73ae9030e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207501633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1207501633
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1114293851
Short name T608
Test name
Test status
Simulation time 4747369221 ps
CPU time 2.82 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:09:14 PM PDT 24
Peak memory 201512 kb
Host smart-dc1c1336-d1b8-4ac1-b03c-16ace5dc0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114293851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1114293851
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3385508241
Short name T739
Test name
Test status
Simulation time 5797735315 ps
CPU time 4.37 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:09:15 PM PDT 24
Peak memory 201444 kb
Host smart-00a0d713-8023-45ea-be28-e62606925913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385508241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3385508241
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3715761884
Short name T221
Test name
Test status
Simulation time 701996659562 ps
CPU time 443.24 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:16:33 PM PDT 24
Peak memory 201648 kb
Host smart-043ca85d-c233-4e72-a7b7-340a3f30a384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715761884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3715761884
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2229731676
Short name T28
Test name
Test status
Simulation time 2230793008 ps
CPU time 7.87 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:09:18 PM PDT 24
Peak memory 209980 kb
Host smart-8f31f9fb-8e1f-4b1d-9c07-88beb5de67c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229731676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2229731676
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2450889428
Short name T717
Test name
Test status
Simulation time 307101635 ps
CPU time 1.31 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:09:17 PM PDT 24
Peak memory 201460 kb
Host smart-1c60d1c5-d126-4fb8-8b2d-9ff1b312ec89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450889428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2450889428
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2386700163
Short name T598
Test name
Test status
Simulation time 193494986227 ps
CPU time 11.13 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:09:29 PM PDT 24
Peak memory 201684 kb
Host smart-5a1da191-2fd5-4afe-b01d-f6e86744929d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386700163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2386700163
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3591692988
Short name T309
Test name
Test status
Simulation time 335383454625 ps
CPU time 427.94 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:16:23 PM PDT 24
Peak memory 201632 kb
Host smart-5a9de4da-ae3b-4a0c-ae0d-7a996075a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591692988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3591692988
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3295260211
Short name T147
Test name
Test status
Simulation time 334659242271 ps
CPU time 358.28 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:15:09 PM PDT 24
Peak memory 201652 kb
Host smart-3a24ba4b-f8e0-4dfd-b0b9-0a633fa2bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295260211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3295260211
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1968328702
Short name T385
Test name
Test status
Simulation time 334262659616 ps
CPU time 746.42 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 201732 kb
Host smart-7606e811-7276-42ed-a742-8b3a902f21d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968328702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1968328702
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3839894963
Short name T730
Test name
Test status
Simulation time 157256937679 ps
CPU time 76 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:10:28 PM PDT 24
Peak memory 201668 kb
Host smart-e92e9715-f30d-4a14-9351-7c8fa8464520
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839894963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3839894963
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.444996244
Short name T724
Test name
Test status
Simulation time 383405502581 ps
CPU time 252.12 seconds
Started Aug 12 06:09:09 PM PDT 24
Finished Aug 12 06:13:21 PM PDT 24
Peak memory 201716 kb
Host smart-76f1bc75-b2b6-45f4-ba5b-09123ae07ee1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444996244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.444996244
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4162830363
Short name T682
Test name
Test status
Simulation time 205800568330 ps
CPU time 514.04 seconds
Started Aug 12 06:09:18 PM PDT 24
Finished Aug 12 06:17:52 PM PDT 24
Peak memory 201664 kb
Host smart-c29b22c2-311d-4772-859b-cee028280230
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162830363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4162830363
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3384554821
Short name T673
Test name
Test status
Simulation time 130756705263 ps
CPU time 688.24 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 201932 kb
Host smart-c65ea5ba-60a4-42af-9294-7f396df18c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384554821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3384554821
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3472293613
Short name T612
Test name
Test status
Simulation time 40043271390 ps
CPU time 97.66 seconds
Started Aug 12 06:09:19 PM PDT 24
Finished Aug 12 06:10:56 PM PDT 24
Peak memory 201488 kb
Host smart-6b6a70e6-e462-44a7-a6b4-0c99c92dae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472293613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3472293613
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1389141726
Short name T622
Test name
Test status
Simulation time 2862331144 ps
CPU time 5.46 seconds
Started Aug 12 06:09:19 PM PDT 24
Finished Aug 12 06:09:25 PM PDT 24
Peak memory 201504 kb
Host smart-3422c4f2-1de7-4969-9e7b-17b953e094e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389141726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1389141726
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3021040534
Short name T376
Test name
Test status
Simulation time 5876085143 ps
CPU time 7.05 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:09:17 PM PDT 24
Peak memory 201516 kb
Host smart-dfb0cec5-0419-483e-a969-bf2b195346c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021040534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3021040534
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2963323169
Short name T36
Test name
Test status
Simulation time 9940239221 ps
CPU time 15.32 seconds
Started Aug 12 06:09:14 PM PDT 24
Finished Aug 12 06:09:29 PM PDT 24
Peak memory 210184 kb
Host smart-4edc512e-832d-4ce4-8fb5-5c036328f37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963323169 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2963323169
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.382461657
Short name T468
Test name
Test status
Simulation time 340476341 ps
CPU time 0.89 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:09:18 PM PDT 24
Peak memory 201468 kb
Host smart-556e418f-f261-4581-a4de-dd30894b3466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382461657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.382461657
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3620415450
Short name T305
Test name
Test status
Simulation time 489656417271 ps
CPU time 99.34 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:10:56 PM PDT 24
Peak memory 201752 kb
Host smart-19581038-9f4d-4b50-8eda-4c893b3aaeef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620415450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3620415450
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.338616927
Short name T340
Test name
Test status
Simulation time 166703937116 ps
CPU time 398.79 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:15:54 PM PDT 24
Peak memory 201676 kb
Host smart-fc9af705-223a-427d-bddc-72f7ce6bae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338616927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.338616927
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3066457506
Short name T482
Test name
Test status
Simulation time 334343813920 ps
CPU time 189.46 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:12:27 PM PDT 24
Peak memory 201680 kb
Host smart-44ab7777-a266-45f3-b5b7-5e1afdf231b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066457506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3066457506
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1375150879
Short name T300
Test name
Test status
Simulation time 172160004720 ps
CPU time 42.35 seconds
Started Aug 12 06:09:19 PM PDT 24
Finished Aug 12 06:10:01 PM PDT 24
Peak memory 201668 kb
Host smart-a13e2908-b147-477c-afd6-c343d033e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375150879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1375150879
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3185447148
Short name T419
Test name
Test status
Simulation time 330141771346 ps
CPU time 385.08 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:15:43 PM PDT 24
Peak memory 201656 kb
Host smart-987b890d-f0a8-4a58-840c-5638ba9649b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185447148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3185447148
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2630560643
Short name T339
Test name
Test status
Simulation time 444819118667 ps
CPU time 269.98 seconds
Started Aug 12 06:09:19 PM PDT 24
Finished Aug 12 06:13:49 PM PDT 24
Peak memory 201708 kb
Host smart-6d5bde01-2c68-48b8-9466-ac32d24f20c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630560643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2630560643
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1895499284
Short name T648
Test name
Test status
Simulation time 404044057544 ps
CPU time 120.59 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:11:16 PM PDT 24
Peak memory 201664 kb
Host smart-883173ef-bd95-4b36-b466-1e8ad4a296d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895499284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1895499284
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1869626296
Short name T460
Test name
Test status
Simulation time 117253682281 ps
CPU time 402.04 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:15:59 PM PDT 24
Peak memory 201984 kb
Host smart-27ba41c0-ae9a-4b3c-80eb-48eaf7f99f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869626296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1869626296
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3608813399
Short name T392
Test name
Test status
Simulation time 24370183467 ps
CPU time 60.25 seconds
Started Aug 12 06:09:16 PM PDT 24
Finished Aug 12 06:10:16 PM PDT 24
Peak memory 201472 kb
Host smart-82c7b300-cee8-43f7-8d20-b9f242c6ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608813399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3608813399
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3812800014
Short name T110
Test name
Test status
Simulation time 4695381953 ps
CPU time 6.09 seconds
Started Aug 12 06:09:18 PM PDT 24
Finished Aug 12 06:09:25 PM PDT 24
Peak memory 201512 kb
Host smart-061ef170-b64b-48d9-8087-99f5b0c1707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812800014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3812800014
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.367526337
Short name T8
Test name
Test status
Simulation time 5761340750 ps
CPU time 13.57 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:09:31 PM PDT 24
Peak memory 201488 kb
Host smart-a8eaac28-1b64-4737-9b7c-d864292c4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367526337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.367526337
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2236615912
Short name T15
Test name
Test status
Simulation time 5432561375 ps
CPU time 11.63 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:09:24 PM PDT 24
Peak memory 210020 kb
Host smart-2c144917-b2af-406d-866c-581f2c60cf88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236615912 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2236615912
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1800468528
Short name T705
Test name
Test status
Simulation time 462411700 ps
CPU time 0.91 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:09:18 PM PDT 24
Peak memory 201356 kb
Host smart-80065077-47f3-4677-8588-20dccbef0df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800468528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1800468528
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1120267959
Short name T220
Test name
Test status
Simulation time 190862328936 ps
CPU time 464.75 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:17:00 PM PDT 24
Peak memory 201692 kb
Host smart-a3665182-bfaf-49b8-8930-ca0c47c1343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120267959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1120267959
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1725212068
Short name T88
Test name
Test status
Simulation time 316703630137 ps
CPU time 722.63 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 201700 kb
Host smart-e4347a0d-a850-4f65-8142-361fbe48b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725212068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1725212068
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.537850776
Short name T642
Test name
Test status
Simulation time 160145824274 ps
CPU time 354.74 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:15:11 PM PDT 24
Peak memory 201596 kb
Host smart-ca30ee89-e22e-49b9-b817-7c50d487ff2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537850776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.537850776
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3980234238
Short name T545
Test name
Test status
Simulation time 492778507577 ps
CPU time 1089.26 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:27:24 PM PDT 24
Peak memory 201644 kb
Host smart-7d7c6c58-a98a-4533-9e92-17b28cc4b57d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980234238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3980234238
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3056582085
Short name T338
Test name
Test status
Simulation time 685269652542 ps
CPU time 1627.59 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:36:30 PM PDT 24
Peak memory 201624 kb
Host smart-46b417d0-d6bf-44e9-a81b-97ae68f758da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056582085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3056582085
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3561956948
Short name T470
Test name
Test status
Simulation time 200863118531 ps
CPU time 233.18 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:13:11 PM PDT 24
Peak memory 201740 kb
Host smart-9961273d-fa3a-4eef-8f52-c84e4553a4e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561956948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3561956948
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1040740683
Short name T574
Test name
Test status
Simulation time 37507129928 ps
CPU time 23.12 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:09:45 PM PDT 24
Peak memory 201440 kb
Host smart-49b4ff75-d359-4349-bbfc-c55e5c9353ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040740683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1040740683
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1285677093
Short name T585
Test name
Test status
Simulation time 4488041572 ps
CPU time 9.72 seconds
Started Aug 12 06:09:18 PM PDT 24
Finished Aug 12 06:09:28 PM PDT 24
Peak memory 201476 kb
Host smart-b5c4a250-1e45-4bf5-89ad-0a46df6fc766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285677093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1285677093
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2128006682
Short name T103
Test name
Test status
Simulation time 5992496871 ps
CPU time 3.7 seconds
Started Aug 12 06:09:17 PM PDT 24
Finished Aug 12 06:09:21 PM PDT 24
Peak memory 201468 kb
Host smart-fdf2d6de-cffd-4d5f-8b49-fd9c64319878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128006682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2128006682
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.353697006
Short name T243
Test name
Test status
Simulation time 371355954049 ps
CPU time 842.67 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:23:18 PM PDT 24
Peak memory 201700 kb
Host smart-84bfb1f9-7ba7-4a68-800e-718f2166d3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353697006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
353697006
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1977335139
Short name T35
Test name
Test status
Simulation time 1886350542 ps
CPU time 5.2 seconds
Started Aug 12 06:09:14 PM PDT 24
Finished Aug 12 06:09:19 PM PDT 24
Peak memory 201504 kb
Host smart-a9300240-4087-4062-8d4b-bfe7e73eeeb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977335139 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1977335139
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1011920392
Short name T485
Test name
Test status
Simulation time 449304244 ps
CPU time 1.58 seconds
Started Aug 12 06:09:24 PM PDT 24
Finished Aug 12 06:09:25 PM PDT 24
Peak memory 201440 kb
Host smart-9cb37bd9-26c2-4aa4-85a1-fffd5b4d4316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011920392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1011920392
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1899309080
Short name T697
Test name
Test status
Simulation time 171303743070 ps
CPU time 402.93 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:16:04 PM PDT 24
Peak memory 201664 kb
Host smart-a4fbe9ba-c4b7-4413-8841-f6cc8daf4d40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899309080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1899309080
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.802551260
Short name T298
Test name
Test status
Simulation time 489328072832 ps
CPU time 290.76 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:14:13 PM PDT 24
Peak memory 201576 kb
Host smart-487461c6-d251-48bc-9198-e6975cf67f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802551260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.802551260
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.467636915
Short name T396
Test name
Test status
Simulation time 500965888991 ps
CPU time 581 seconds
Started Aug 12 06:09:16 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 201584 kb
Host smart-8cb2f860-298d-4095-a20a-88e9ae0225d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=467636915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.467636915
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1097499150
Short name T235
Test name
Test status
Simulation time 331522857266 ps
CPU time 719.73 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 201688 kb
Host smart-8128865e-35a1-4b94-a63b-30a4a5cd03c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097499150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1097499150
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3566999333
Short name T464
Test name
Test status
Simulation time 594428588832 ps
CPU time 357.01 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:15:18 PM PDT 24
Peak memory 201604 kb
Host smart-3acbbd75-9ed4-4d05-b05c-36f2a1a84373
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566999333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3566999333
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4087941237
Short name T205
Test name
Test status
Simulation time 110020843678 ps
CPU time 382.92 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:15:45 PM PDT 24
Peak memory 201928 kb
Host smart-e0d50008-27b8-4111-922b-a571893da937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087941237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4087941237
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1615845385
Short name T516
Test name
Test status
Simulation time 31330669324 ps
CPU time 9.25 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:09:38 PM PDT 24
Peak memory 201484 kb
Host smart-727d4cdd-98cd-4b5a-b17f-a8c15acb68f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615845385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1615845385
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2644468090
Short name T427
Test name
Test status
Simulation time 3974765684 ps
CPU time 4.92 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:09:32 PM PDT 24
Peak memory 201456 kb
Host smart-93f9f1e2-d549-4aed-8b0f-ececc14dac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644468090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2644468090
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1745406889
Short name T465
Test name
Test status
Simulation time 5965868425 ps
CPU time 4.44 seconds
Started Aug 12 06:09:15 PM PDT 24
Finished Aug 12 06:09:20 PM PDT 24
Peak memory 201480 kb
Host smart-f672202e-022b-4fbd-9548-4d5fa57b2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745406889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1745406889
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3705580078
Short name T206
Test name
Test status
Simulation time 126110464007 ps
CPU time 669.18 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:20:38 PM PDT 24
Peak memory 201940 kb
Host smart-940abf40-5297-46a3-a5d4-0d0c94c186bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705580078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3705580078
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3508665947
Short name T723
Test name
Test status
Simulation time 14833892630 ps
CPU time 12.38 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:09:34 PM PDT 24
Peak memory 210176 kb
Host smart-6bd02ba6-936e-43ca-954f-8f85facee72b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508665947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3508665947
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.399986504
Short name T744
Test name
Test status
Simulation time 486782813 ps
CPU time 0.9 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:09:31 PM PDT 24
Peak memory 201444 kb
Host smart-4047a5d6-4168-4552-aca7-77c883388f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399986504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.399986504
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.333482616
Short name T312
Test name
Test status
Simulation time 189252633839 ps
CPU time 113.17 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:11:14 PM PDT 24
Peak memory 201728 kb
Host smart-13a90721-1c66-45db-8b6d-6aaf57fe554a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333482616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.333482616
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3100199799
Short name T564
Test name
Test status
Simulation time 201883970405 ps
CPU time 471.69 seconds
Started Aug 12 06:09:20 PM PDT 24
Finished Aug 12 06:17:12 PM PDT 24
Peak memory 201664 kb
Host smart-dc2cb38a-8ae2-47fd-b7ae-25530c428e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100199799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3100199799
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1500021733
Short name T188
Test name
Test status
Simulation time 496152257766 ps
CPU time 271.06 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:13:54 PM PDT 24
Peak memory 201652 kb
Host smart-8151f035-7ed4-42c5-bcad-c194f1053f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500021733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1500021733
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.284519456
Short name T547
Test name
Test status
Simulation time 168497775577 ps
CPU time 87.4 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:10:49 PM PDT 24
Peak memory 201740 kb
Host smart-7c92dc09-61ec-4e58-ab6c-acf2c547ef30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=284519456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.284519456
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2479707547
Short name T190
Test name
Test status
Simulation time 330813975795 ps
CPU time 66.41 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:10:36 PM PDT 24
Peak memory 201672 kb
Host smart-504e9ea7-efac-4ce6-bd36-b33f53e76de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479707547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2479707547
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.676193194
Short name T150
Test name
Test status
Simulation time 489346487054 ps
CPU time 159.36 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:12:05 PM PDT 24
Peak memory 201636 kb
Host smart-4e3fca15-a25f-482c-9666-c0a1aa819348
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676193194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.676193194
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3656679597
Short name T154
Test name
Test status
Simulation time 557101961973 ps
CPU time 1207.87 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:29:29 PM PDT 24
Peak memory 201664 kb
Host smart-464a5181-9637-4eb8-83ca-ed3f99cbf834
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656679597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3656679597
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1266790266
Short name T541
Test name
Test status
Simulation time 610158183295 ps
CPU time 686.05 seconds
Started Aug 12 06:09:22 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 201552 kb
Host smart-8d82aedc-c0b1-432f-b25e-0ac02b86d904
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266790266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1266790266
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.634140395
Short name T505
Test name
Test status
Simulation time 63696782966 ps
CPU time 353.65 seconds
Started Aug 12 06:09:26 PM PDT 24
Finished Aug 12 06:15:20 PM PDT 24
Peak memory 201916 kb
Host smart-4edafd72-bb89-4e11-8e57-10f7fbda07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634140395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.634140395
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2838604760
Short name T360
Test name
Test status
Simulation time 42567783305 ps
CPU time 38.21 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:09:59 PM PDT 24
Peak memory 201508 kb
Host smart-e6b5b914-009f-4c95-a042-372ca37d43ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838604760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2838604760
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3125983112
Short name T597
Test name
Test status
Simulation time 4933789906 ps
CPU time 12.76 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:09:37 PM PDT 24
Peak memory 201508 kb
Host smart-6580971e-3639-4838-8870-5a7c1a24e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125983112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3125983112
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4250055669
Short name T594
Test name
Test status
Simulation time 6153637046 ps
CPU time 15.81 seconds
Started Aug 12 06:09:23 PM PDT 24
Finished Aug 12 06:09:38 PM PDT 24
Peak memory 201436 kb
Host smart-97b116a4-d236-4bc4-880d-d22b0d7ad6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250055669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4250055669
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2888689587
Short name T32
Test name
Test status
Simulation time 340199669329 ps
CPU time 744.41 seconds
Started Aug 12 06:09:23 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 201620 kb
Host smart-5aaa3e7e-736b-45e4-8eb6-9403b8d56e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888689587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2888689587
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.923700773
Short name T27
Test name
Test status
Simulation time 5261912201 ps
CPU time 18.28 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:09:46 PM PDT 24
Peak memory 210120 kb
Host smart-362f3cd9-875c-445c-b7a0-8bff7cd5305b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923700773 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.923700773
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1381193973
Short name T776
Test name
Test status
Simulation time 476201630 ps
CPU time 1.75 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:09:30 PM PDT 24
Peak memory 201452 kb
Host smart-c9be1324-bcd0-4ebd-8fb3-fbb81f535329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381193973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1381193973
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2586905319
Short name T738
Test name
Test status
Simulation time 535279086055 ps
CPU time 1143.9 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:28:33 PM PDT 24
Peak memory 201688 kb
Host smart-d9eb09b7-74d9-4a79-b9c6-b4c6e44063eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586905319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2586905319
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1056796325
Short name T729
Test name
Test status
Simulation time 328412856659 ps
CPU time 706.82 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:21:16 PM PDT 24
Peak memory 201676 kb
Host smart-fa15d316-8818-45c7-8849-13ae7e9713a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056796325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1056796325
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3699913060
Short name T26
Test name
Test status
Simulation time 166988052105 ps
CPU time 358.16 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:15:26 PM PDT 24
Peak memory 201668 kb
Host smart-090996b1-82ab-43e8-a91a-dbbcff817b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699913060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3699913060
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2731019129
Short name T599
Test name
Test status
Simulation time 326054854968 ps
CPU time 702.09 seconds
Started Aug 12 06:09:24 PM PDT 24
Finished Aug 12 06:21:06 PM PDT 24
Peak memory 201676 kb
Host smart-71c8cb7f-7cc7-487d-90c9-d79d04a0103c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731019129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2731019129
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1987969014
Short name T425
Test name
Test status
Simulation time 167903978550 ps
CPU time 105.26 seconds
Started Aug 12 06:09:26 PM PDT 24
Finished Aug 12 06:11:11 PM PDT 24
Peak memory 201628 kb
Host smart-a380cab7-37de-4b82-a196-14e80f6a0a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987969014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1987969014
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4031118853
Short name T531
Test name
Test status
Simulation time 335171414534 ps
CPU time 203.57 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:12:53 PM PDT 24
Peak memory 201680 kb
Host smart-6b651fd4-ec25-4e62-8576-0773b68934d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031118853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4031118853
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4144878156
Short name T751
Test name
Test status
Simulation time 184219902446 ps
CPU time 425.12 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:16:27 PM PDT 24
Peak memory 201660 kb
Host smart-3a7c1367-81aa-40f2-afc1-f3045ff3de9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144878156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4144878156
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.612366983
Short name T193
Test name
Test status
Simulation time 602292013510 ps
CPU time 369.99 seconds
Started Aug 12 06:09:24 PM PDT 24
Finished Aug 12 06:15:34 PM PDT 24
Peak memory 201652 kb
Host smart-9c790f6a-3a36-42f0-85d3-7401dd6d973d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612366983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.612366983
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1272598082
Short name T775
Test name
Test status
Simulation time 125723014663 ps
CPU time 480.77 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:17:22 PM PDT 24
Peak memory 201984 kb
Host smart-f0053bd2-8558-4fcd-970b-f1b9c2d3ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272598082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1272598082
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2671422788
Short name T589
Test name
Test status
Simulation time 37200643176 ps
CPU time 13.47 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:09:39 PM PDT 24
Peak memory 201488 kb
Host smart-eee1e644-7e78-43e5-bafe-5b500b1d6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671422788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2671422788
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3193667302
Short name T638
Test name
Test status
Simulation time 4195920903 ps
CPU time 10.22 seconds
Started Aug 12 06:09:21 PM PDT 24
Finished Aug 12 06:09:31 PM PDT 24
Peak memory 201476 kb
Host smart-4a187b53-3921-4d3d-b8ab-08e9bd9a6300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193667302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3193667302
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1749333273
Short name T629
Test name
Test status
Simulation time 5915886250 ps
CPU time 5.1 seconds
Started Aug 12 06:09:23 PM PDT 24
Finished Aug 12 06:09:28 PM PDT 24
Peak memory 201436 kb
Host smart-134e78cb-8b55-4e44-b081-52763d68589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749333273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1749333273
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3804686004
Short name T588
Test name
Test status
Simulation time 186222724577 ps
CPU time 56.5 seconds
Started Aug 12 06:09:25 PM PDT 24
Finished Aug 12 06:10:22 PM PDT 24
Peak memory 201640 kb
Host smart-14711662-993b-404a-a7f3-3514531f4385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804686004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3804686004
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.978185789
Short name T37
Test name
Test status
Simulation time 1542573998 ps
CPU time 6.01 seconds
Started Aug 12 06:09:23 PM PDT 24
Finished Aug 12 06:09:29 PM PDT 24
Peak memory 201504 kb
Host smart-f266073f-29b9-4343-a29e-df16cb0d05cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978185789 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.978185789
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2080810707
Short name T650
Test name
Test status
Simulation time 516371507 ps
CPU time 1.87 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:09:32 PM PDT 24
Peak memory 201416 kb
Host smart-8bb68372-0ce9-4137-91f8-b0a5708abbdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080810707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2080810707
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1190573852
Short name T279
Test name
Test status
Simulation time 324799166844 ps
CPU time 400.32 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:16:10 PM PDT 24
Peak memory 201600 kb
Host smart-cbe1aeb1-bc03-4358-baae-306b3f7f2ad3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190573852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1190573852
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1255008900
Short name T408
Test name
Test status
Simulation time 160805668890 ps
CPU time 194.03 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:12:45 PM PDT 24
Peak memory 201760 kb
Host smart-c7ab40d9-47f6-4061-b9bf-9a2820e7f999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255008900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1255008900
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2526612278
Short name T5
Test name
Test status
Simulation time 327609557238 ps
CPU time 206.68 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:12:53 PM PDT 24
Peak memory 201648 kb
Host smart-19a68015-7a73-428c-aa05-24a9b150ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526612278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2526612278
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.722601841
Short name T623
Test name
Test status
Simulation time 168553327726 ps
CPU time 162.04 seconds
Started Aug 12 06:09:31 PM PDT 24
Finished Aug 12 06:12:13 PM PDT 24
Peak memory 201636 kb
Host smart-4ea28db5-cf4c-4837-b049-cef43c673a6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722601841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.722601841
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3820166129
Short name T246
Test name
Test status
Simulation time 181658630542 ps
CPU time 107.85 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:11:18 PM PDT 24
Peak memory 201688 kb
Host smart-962d999e-bf6c-4f48-b708-818522b3db7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820166129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3820166129
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3490462358
Short name T105
Test name
Test status
Simulation time 423950201409 ps
CPU time 478.23 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:17:26 PM PDT 24
Peak memory 201660 kb
Host smart-604a6f00-b5ae-4f7f-a493-5051bc6191b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490462358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3490462358
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1230277769
Short name T212
Test name
Test status
Simulation time 71043409835 ps
CPU time 384.72 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:15:55 PM PDT 24
Peak memory 201920 kb
Host smart-a48aee9a-89d5-4cd4-8586-371a7a9894f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230277769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1230277769
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2844296536
Short name T86
Test name
Test status
Simulation time 21978210651 ps
CPU time 54.4 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:10:25 PM PDT 24
Peak memory 201548 kb
Host smart-f0a62f55-faa2-4252-b3ff-5d72cd0db8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844296536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2844296536
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1283137220
Short name T83
Test name
Test status
Simulation time 4193081335 ps
CPU time 2.24 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:09:30 PM PDT 24
Peak memory 201472 kb
Host smart-d737ba79-557d-4712-86e6-a029a6a4c3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283137220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1283137220
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4006103674
Short name T749
Test name
Test status
Simulation time 5872465276 ps
CPU time 3.92 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:09:34 PM PDT 24
Peak memory 201548 kb
Host smart-70c8b335-fe76-40be-b433-73b03e56d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006103674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4006103674
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.322029336
Short name T20
Test name
Test status
Simulation time 3785222130 ps
CPU time 13.46 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:09:44 PM PDT 24
Peak memory 209940 kb
Host smart-202048de-0736-4ff7-ba87-e7f94cf20788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322029336 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.322029336
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1035117786
Short name T478
Test name
Test status
Simulation time 354465976 ps
CPU time 1.36 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:09:35 PM PDT 24
Peak memory 201448 kb
Host smart-9f8e58ae-1cbd-45c0-86a0-4072ced29e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035117786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1035117786
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2082243826
Short name T230
Test name
Test status
Simulation time 187831483064 ps
CPU time 27.58 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:09:55 PM PDT 24
Peak memory 201664 kb
Host smart-36368b2f-da21-48b1-99cb-41201dd73d40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082243826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2082243826
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.912393513
Short name T178
Test name
Test status
Simulation time 242945097787 ps
CPU time 147.5 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:11:56 PM PDT 24
Peak memory 201676 kb
Host smart-9264f678-2108-4426-8d7b-f13b8502250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912393513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.912393513
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.320746224
Short name T632
Test name
Test status
Simulation time 490532806147 ps
CPU time 1061.4 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 201636 kb
Host smart-e84bc001-2949-4cf8-9aad-e664a84951b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=320746224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.320746224
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1814772967
Short name T489
Test name
Test status
Simulation time 490195526739 ps
CPU time 1143.58 seconds
Started Aug 12 06:09:29 PM PDT 24
Finished Aug 12 06:28:33 PM PDT 24
Peak memory 201656 kb
Host smart-576b961b-7f0a-424d-8029-36a1bdcc7609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814772967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1814772967
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1338008133
Short name T389
Test name
Test status
Simulation time 491034054848 ps
CPU time 1176.98 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:29:05 PM PDT 24
Peak memory 201552 kb
Host smart-9c1c7b55-d5b2-4f5c-a3ec-43ba5c4946d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338008133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1338008133
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3482847220
Short name T194
Test name
Test status
Simulation time 488543833664 ps
CPU time 609.35 seconds
Started Aug 12 06:09:26 PM PDT 24
Finished Aug 12 06:19:36 PM PDT 24
Peak memory 201532 kb
Host smart-25e829c3-a667-4e5a-b87b-f58c06d0e29f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482847220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3482847220
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2111875356
Short name T89
Test name
Test status
Simulation time 207214896063 ps
CPU time 221.94 seconds
Started Aug 12 06:09:27 PM PDT 24
Finished Aug 12 06:13:09 PM PDT 24
Peak memory 201680 kb
Host smart-08572567-dc12-44d0-b59a-ae2ed393a833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111875356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2111875356
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1391668612
Short name T218
Test name
Test status
Simulation time 67373353627 ps
CPU time 309.65 seconds
Started Aug 12 06:09:35 PM PDT 24
Finished Aug 12 06:14:45 PM PDT 24
Peak memory 201888 kb
Host smart-f90450f3-d0dd-4217-b451-1c109ecce00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391668612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1391668612
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4234704645
Short name T676
Test name
Test status
Simulation time 36971662957 ps
CPU time 33.72 seconds
Started Aug 12 06:09:36 PM PDT 24
Finished Aug 12 06:10:09 PM PDT 24
Peak memory 201448 kb
Host smart-17eff27a-524c-401c-a716-6ef72857266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234704645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4234704645
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4146856330
Short name T447
Test name
Test status
Simulation time 5214165585 ps
CPU time 12.74 seconds
Started Aug 12 06:09:28 PM PDT 24
Finished Aug 12 06:09:41 PM PDT 24
Peak memory 201424 kb
Host smart-c98ba501-bfe0-4c17-a65b-1869e2200075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146856330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4146856330
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1286526674
Short name T704
Test name
Test status
Simulation time 5820058208 ps
CPU time 4.15 seconds
Started Aug 12 06:09:30 PM PDT 24
Finished Aug 12 06:09:34 PM PDT 24
Peak memory 201448 kb
Host smart-bb2430d2-dcc4-462a-b235-dc224369e137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286526674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1286526674
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1607550995
Short name T519
Test name
Test status
Simulation time 15903821462 ps
CPU time 29.64 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:10:03 PM PDT 24
Peak memory 210184 kb
Host smart-cf7070c5-565b-4a89-a895-647298e4f3a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607550995 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1607550995
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.381923548
Short name T71
Test name
Test status
Simulation time 499078021 ps
CPU time 1.68 seconds
Started Aug 12 06:09:41 PM PDT 24
Finished Aug 12 06:09:43 PM PDT 24
Peak memory 201396 kb
Host smart-85c08d7d-9a03-4cdf-be04-c18ee8ceed89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381923548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.381923548
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.203681059
Short name T788
Test name
Test status
Simulation time 158583493757 ps
CPU time 98.08 seconds
Started Aug 12 06:09:36 PM PDT 24
Finished Aug 12 06:11:14 PM PDT 24
Peak memory 201756 kb
Host smart-1c54e60e-b649-49aa-8278-6dc08dddb51f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203681059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.203681059
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4094719179
Short name T785
Test name
Test status
Simulation time 354225133099 ps
CPU time 52.85 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:10:27 PM PDT 24
Peak memory 201664 kb
Host smart-86a37e3d-ba90-4b20-b359-01de62e6f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094719179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4094719179
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.4078102835
Short name T149
Test name
Test status
Simulation time 490944139994 ps
CPU time 1223.15 seconds
Started Aug 12 06:09:38 PM PDT 24
Finished Aug 12 06:30:01 PM PDT 24
Peak memory 201636 kb
Host smart-371b4f66-9b02-4be8-8ed6-112a147cc067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078102835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.4078102835
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1671063186
Short name T363
Test name
Test status
Simulation time 326233756895 ps
CPU time 356.49 seconds
Started Aug 12 06:09:36 PM PDT 24
Finished Aug 12 06:15:32 PM PDT 24
Peak memory 201684 kb
Host smart-6f735fdb-241e-4cb6-a741-1161728e6e3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671063186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1671063186
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2943653715
Short name T301
Test name
Test status
Simulation time 493155959428 ps
CPU time 278.31 seconds
Started Aug 12 06:09:38 PM PDT 24
Finished Aug 12 06:14:17 PM PDT 24
Peak memory 201672 kb
Host smart-e73ab4aa-dd15-46e1-a998-0a22816d94ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943653715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2943653715
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3606484045
Short name T517
Test name
Test status
Simulation time 171468231174 ps
CPU time 371.25 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:15:45 PM PDT 24
Peak memory 201660 kb
Host smart-138d0264-3f11-4e2d-8013-a458bf31eda0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606484045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3606484045
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3346103041
Short name T316
Test name
Test status
Simulation time 345619526762 ps
CPU time 846.32 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:23:40 PM PDT 24
Peak memory 201620 kb
Host smart-2c3c988d-b5f5-4407-ab7d-df392b22f9b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346103041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3346103041
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3515515732
Short name T609
Test name
Test status
Simulation time 570092691921 ps
CPU time 351.9 seconds
Started Aug 12 06:09:39 PM PDT 24
Finished Aug 12 06:15:31 PM PDT 24
Peak memory 201616 kb
Host smart-e09bc904-0259-4fc0-9cb0-5e75372fde41
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515515732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3515515732
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2784537415
Short name T754
Test name
Test status
Simulation time 100454338816 ps
CPU time 490.89 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:17:45 PM PDT 24
Peak memory 201956 kb
Host smart-dc26e33e-052b-4e0d-80ba-5539ecd4a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784537415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2784537415
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.575949119
Short name T514
Test name
Test status
Simulation time 30742005396 ps
CPU time 19.76 seconds
Started Aug 12 06:09:34 PM PDT 24
Finished Aug 12 06:09:54 PM PDT 24
Peak memory 201492 kb
Host smart-9028cb5f-fff2-4ba8-935a-127cd407e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575949119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.575949119
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3651798186
Short name T437
Test name
Test status
Simulation time 4594650998 ps
CPU time 9.76 seconds
Started Aug 12 06:09:37 PM PDT 24
Finished Aug 12 06:09:47 PM PDT 24
Peak memory 201500 kb
Host smart-6115b1b0-e803-46d3-9262-655a09592e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651798186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3651798186
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1933029547
Short name T554
Test name
Test status
Simulation time 5788916366 ps
CPU time 13.11 seconds
Started Aug 12 06:09:35 PM PDT 24
Finished Aug 12 06:09:48 PM PDT 24
Peak memory 201452 kb
Host smart-3df637e8-3a63-4332-9f6a-69a8372ee448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933029547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1933029547
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1641078162
Short name T217
Test name
Test status
Simulation time 455307492259 ps
CPU time 719.98 seconds
Started Aug 12 06:09:33 PM PDT 24
Finished Aug 12 06:21:33 PM PDT 24
Peak memory 201940 kb
Host smart-47a24e17-0d32-4d80-9914-806088c35317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641078162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1641078162
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4218736911
Short name T287
Test name
Test status
Simulation time 166650744560 ps
CPU time 15.28 seconds
Started Aug 12 06:09:40 PM PDT 24
Finished Aug 12 06:09:55 PM PDT 24
Peak memory 210184 kb
Host smart-1dd5cdf3-302c-405b-9ea9-c20374576339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218736911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4218736911
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1744828967
Short name T487
Test name
Test status
Simulation time 552068024 ps
CPU time 0.74 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:08:49 PM PDT 24
Peak memory 201456 kb
Host smart-de7f9c4d-da5f-4036-8e6b-79b3c60c196c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744828967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1744828967
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4181467070
Short name T294
Test name
Test status
Simulation time 541952894402 ps
CPU time 760.44 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 201560 kb
Host smart-bb93cd36-1886-4cce-b2ab-f22efda8d4e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181467070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4181467070
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4092599392
Short name T307
Test name
Test status
Simulation time 517043141843 ps
CPU time 1244.16 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:29:35 PM PDT 24
Peak memory 201576 kb
Host smart-97014e00-e743-4461-8fe4-a977bf890bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092599392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4092599392
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2078389699
Short name T183
Test name
Test status
Simulation time 326926975523 ps
CPU time 156.25 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:11:32 PM PDT 24
Peak memory 201704 kb
Host smart-82ade16b-0391-4b31-b4d1-c76b5bcfcc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078389699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2078389699
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1585782292
Short name T420
Test name
Test status
Simulation time 166311492869 ps
CPU time 400.62 seconds
Started Aug 12 06:08:47 PM PDT 24
Finished Aug 12 06:15:28 PM PDT 24
Peak memory 201668 kb
Host smart-d5ed0dd1-8ff7-4f09-aecf-620ae5e37979
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585782292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1585782292
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3052531125
Short name T714
Test name
Test status
Simulation time 332090201533 ps
CPU time 751.16 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 201660 kb
Host smart-9a8c165d-3717-4e0f-b9c4-17b7490ffd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052531125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3052531125
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1390520052
Short name T767
Test name
Test status
Simulation time 332332775413 ps
CPU time 190.37 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:11:59 PM PDT 24
Peak memory 201676 kb
Host smart-d2c96e6c-f7a7-4783-a5af-f0c3c4b217ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390520052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1390520052
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1176432264
Short name T303
Test name
Test status
Simulation time 361740170502 ps
CPU time 182.43 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:11:52 PM PDT 24
Peak memory 201632 kb
Host smart-5ba9a3b0-8f39-44e2-8750-86db60d0fb45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176432264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1176432264
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1211951148
Short name T782
Test name
Test status
Simulation time 399048618677 ps
CPU time 247.19 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:12:55 PM PDT 24
Peak memory 201680 kb
Host smart-15a0b506-a65f-4aa3-9f52-0de6436bbae6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211951148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1211951148
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.688223034
Short name T768
Test name
Test status
Simulation time 98931928154 ps
CPU time 495.25 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:17:10 PM PDT 24
Peak memory 201976 kb
Host smart-a7557f68-dd6e-4862-8c0f-90b877328b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688223034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.688223034
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1876784819
Short name T606
Test name
Test status
Simulation time 43615293643 ps
CPU time 52.84 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:09:41 PM PDT 24
Peak memory 201488 kb
Host smart-aca1a621-22ab-41b1-93cc-781e86765fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876784819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1876784819
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4057204210
Short name T90
Test name
Test status
Simulation time 4053151498 ps
CPU time 10.1 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:09:00 PM PDT 24
Peak memory 201436 kb
Host smart-56482a02-a174-4f26-850d-1baf91c5fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057204210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4057204210
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1844988497
Short name T66
Test name
Test status
Simulation time 4734017307 ps
CPU time 3.31 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:08:58 PM PDT 24
Peak memory 217076 kb
Host smart-765b3ef3-f7ef-4ccf-bc47-0b5f8d8e7e87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844988497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1844988497
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.693136612
Short name T402
Test name
Test status
Simulation time 6123771934 ps
CPU time 4.55 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:08:59 PM PDT 24
Peak memory 201464 kb
Host smart-f9e9d79b-efa8-4cc9-9947-32a1d7db1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693136612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.693136612
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1513262104
Short name T480
Test name
Test status
Simulation time 325753806199 ps
CPU time 165.33 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:11:38 PM PDT 24
Peak memory 201600 kb
Host smart-c53bef6a-72c3-4cb5-9ed7-39345c8c8712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513262104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1513262104
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1718129676
Short name T38
Test name
Test status
Simulation time 5865047301 ps
CPU time 13.73 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:09:04 PM PDT 24
Peak memory 210156 kb
Host smart-67b49fda-9eeb-4a1c-a0f5-43bd451a25ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718129676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1718129676
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2974571776
Short name T706
Test name
Test status
Simulation time 340493654 ps
CPU time 1.01 seconds
Started Aug 12 06:09:44 PM PDT 24
Finished Aug 12 06:09:45 PM PDT 24
Peak memory 201428 kb
Host smart-c6b55ca7-cbc6-4bd5-b6c9-170e6eaeb2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974571776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2974571776
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.89418469
Short name T270
Test name
Test status
Simulation time 161767740207 ps
CPU time 27.39 seconds
Started Aug 12 06:09:45 PM PDT 24
Finished Aug 12 06:10:12 PM PDT 24
Peak memory 201616 kb
Host smart-31baf034-0ef5-40b0-98e3-fe6e28ce7e76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89418469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gatin
g.89418469
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.482893593
Short name T229
Test name
Test status
Simulation time 358928654682 ps
CPU time 302.36 seconds
Started Aug 12 06:09:44 PM PDT 24
Finished Aug 12 06:14:46 PM PDT 24
Peak memory 201692 kb
Host smart-2a93c478-1f70-4f30-ac05-254d22630610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482893593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.482893593
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3874559969
Short name T755
Test name
Test status
Simulation time 494855658262 ps
CPU time 565.84 seconds
Started Aug 12 06:09:39 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 201696 kb
Host smart-f5a595af-8c62-4e3b-9ac8-f7bbb4658977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874559969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3874559969
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.955269960
Short name T611
Test name
Test status
Simulation time 163825444054 ps
CPU time 52.8 seconds
Started Aug 12 06:09:36 PM PDT 24
Finished Aug 12 06:10:29 PM PDT 24
Peak memory 201680 kb
Host smart-fcb260b8-2d12-462a-b953-7da32304bde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955269960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.955269960
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3932167120
Short name T364
Test name
Test status
Simulation time 170951731581 ps
CPU time 398.71 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:16:21 PM PDT 24
Peak memory 201576 kb
Host smart-d88bcefd-5c5c-417b-82b2-de0e5641f9bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932167120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3932167120
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2950714284
Short name T476
Test name
Test status
Simulation time 192811496183 ps
CPU time 410.53 seconds
Started Aug 12 06:09:44 PM PDT 24
Finished Aug 12 06:16:34 PM PDT 24
Peak memory 201680 kb
Host smart-55e88863-fe36-4f83-9b6a-d957aa159d9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950714284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2950714284
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.176648620
Short name T603
Test name
Test status
Simulation time 64005997747 ps
CPU time 289.54 seconds
Started Aug 12 06:09:40 PM PDT 24
Finished Aug 12 06:14:30 PM PDT 24
Peak memory 201912 kb
Host smart-f9c7e85c-70ea-4215-b763-9209d3dddbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176648620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.176648620
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1049539199
Short name T791
Test name
Test status
Simulation time 22891191906 ps
CPU time 27.2 seconds
Started Aug 12 06:09:40 PM PDT 24
Finished Aug 12 06:10:07 PM PDT 24
Peak memory 201456 kb
Host smart-a0582f01-8cb5-4585-aa92-8fe10c859cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049539199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1049539199
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3608482003
Short name T708
Test name
Test status
Simulation time 3098067235 ps
CPU time 4.57 seconds
Started Aug 12 06:09:44 PM PDT 24
Finished Aug 12 06:09:48 PM PDT 24
Peak memory 201472 kb
Host smart-6daa5328-8b0f-48f7-956f-b1787555d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608482003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3608482003
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4289759235
Short name T362
Test name
Test status
Simulation time 6018959571 ps
CPU time 13.76 seconds
Started Aug 12 06:09:35 PM PDT 24
Finished Aug 12 06:09:49 PM PDT 24
Peak memory 201484 kb
Host smart-f053a009-498d-4a22-8b10-7c0c3ba01340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289759235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4289759235
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3111624343
Short name T653
Test name
Test status
Simulation time 272799040133 ps
CPU time 609.95 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:19:52 PM PDT 24
Peak memory 210088 kb
Host smart-1cbbcf66-a517-4154-9e94-19037258a3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111624343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3111624343
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4150280560
Short name T19
Test name
Test status
Simulation time 8114101974 ps
CPU time 5.63 seconds
Started Aug 12 06:09:40 PM PDT 24
Finished Aug 12 06:09:45 PM PDT 24
Peak memory 209924 kb
Host smart-4b158f69-0475-42c5-ae28-ab22d861adfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150280560 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4150280560
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3268026718
Short name T646
Test name
Test status
Simulation time 368045083 ps
CPU time 0.85 seconds
Started Aug 12 06:09:49 PM PDT 24
Finished Aug 12 06:09:50 PM PDT 24
Peak memory 201468 kb
Host smart-230c930a-fb7e-4ebf-b37c-4351a75b2d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268026718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3268026718
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.372417170
Short name T136
Test name
Test status
Simulation time 159286825675 ps
CPU time 180.5 seconds
Started Aug 12 06:09:46 PM PDT 24
Finished Aug 12 06:12:47 PM PDT 24
Peak memory 201668 kb
Host smart-7ac4ba98-eb4c-438c-8e72-4620ebbecfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372417170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.372417170
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1858981392
Short name T158
Test name
Test status
Simulation time 162030264462 ps
CPU time 36.61 seconds
Started Aug 12 06:09:43 PM PDT 24
Finished Aug 12 06:10:19 PM PDT 24
Peak memory 201636 kb
Host smart-0f765fca-997f-414a-879c-ede4574ad309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858981392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1858981392
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2320681445
Short name T411
Test name
Test status
Simulation time 160721006834 ps
CPU time 98.67 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:11:21 PM PDT 24
Peak memory 201732 kb
Host smart-27df7f45-4aa9-41c8-9d20-9949d7e8e1ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320681445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2320681445
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.366193291
Short name T138
Test name
Test status
Simulation time 164037227542 ps
CPU time 344.2 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:15:26 PM PDT 24
Peak memory 201692 kb
Host smart-855444a0-f7ef-4a1e-8b72-c4f763ad0b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366193291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.366193291
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2953810108
Short name T692
Test name
Test status
Simulation time 164085593639 ps
CPU time 362.33 seconds
Started Aug 12 06:09:42 PM PDT 24
Finished Aug 12 06:15:45 PM PDT 24
Peak memory 201676 kb
Host smart-6c615dcd-200b-4556-bd46-14eec47e3448
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953810108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2953810108
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.617273681
Short name T635
Test name
Test status
Simulation time 191982783731 ps
CPU time 121.98 seconds
Started Aug 12 06:09:43 PM PDT 24
Finished Aug 12 06:11:45 PM PDT 24
Peak memory 201644 kb
Host smart-bebd09d5-1d54-40b5-8b80-474fd7266f0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617273681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.617273681
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.925142903
Short name T536
Test name
Test status
Simulation time 195306150630 ps
CPU time 478.75 seconds
Started Aug 12 06:09:41 PM PDT 24
Finished Aug 12 06:17:40 PM PDT 24
Peak memory 201656 kb
Host smart-0144870e-50f1-4207-b0f2-2c78b7ae935c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925142903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.925142903
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2715219219
Short name T675
Test name
Test status
Simulation time 92440463832 ps
CPU time 423.2 seconds
Started Aug 12 06:09:49 PM PDT 24
Finished Aug 12 06:16:52 PM PDT 24
Peak memory 201912 kb
Host smart-f93413b8-5624-4158-8b7f-f90c9c9ceb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715219219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2715219219
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4070142520
Short name T686
Test name
Test status
Simulation time 24256549286 ps
CPU time 12.18 seconds
Started Aug 12 06:09:45 PM PDT 24
Finished Aug 12 06:09:58 PM PDT 24
Peak memory 201496 kb
Host smart-ad182ddb-7a68-47bb-a9be-2b02989ca540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070142520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4070142520
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3496090273
Short name T416
Test name
Test status
Simulation time 3082118474 ps
CPU time 2.59 seconds
Started Aug 12 06:09:50 PM PDT 24
Finished Aug 12 06:09:52 PM PDT 24
Peak memory 201476 kb
Host smart-b81dddb9-e5bb-4ee1-ad81-7c2e955ab069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496090273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3496090273
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3318919480
Short name T404
Test name
Test status
Simulation time 5881553362 ps
CPU time 16.24 seconds
Started Aug 12 06:09:43 PM PDT 24
Finished Aug 12 06:10:00 PM PDT 24
Peak memory 201448 kb
Host smart-6e76cc49-06e2-4a11-8791-a58ff1fe6676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318919480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3318919480
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4034340809
Short name T649
Test name
Test status
Simulation time 709686457629 ps
CPU time 976.7 seconds
Started Aug 12 06:09:46 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 212652 kb
Host smart-2d7fdc11-d843-4ff0-8ea6-c866cc58dbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034340809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4034340809
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1642875012
Short name T17
Test name
Test status
Simulation time 2937820759 ps
CPU time 7.78 seconds
Started Aug 12 06:09:46 PM PDT 24
Finished Aug 12 06:09:54 PM PDT 24
Peak memory 201572 kb
Host smart-1eef59b5-bfb7-4ec0-ac92-04dc7943ef4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642875012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1642875012
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.827565399
Short name T787
Test name
Test status
Simulation time 494435141 ps
CPU time 1.71 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:09:56 PM PDT 24
Peak memory 201460 kb
Host smart-64ca1e31-4b61-4aca-aa9f-1787aad58984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827565399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.827565399
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.800953503
Short name T488
Test name
Test status
Simulation time 335734655789 ps
CPU time 63.45 seconds
Started Aug 12 06:09:48 PM PDT 24
Finished Aug 12 06:10:52 PM PDT 24
Peak memory 201708 kb
Host smart-c5d17a3c-35e5-4489-a368-1ebc1496db10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=800953503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.800953503
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2607762127
Short name T326
Test name
Test status
Simulation time 491303749002 ps
CPU time 518.45 seconds
Started Aug 12 06:09:47 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 201684 kb
Host smart-310e08fb-7ac2-4eaa-aba5-21a872123692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607762127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2607762127
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2803840612
Short name T397
Test name
Test status
Simulation time 490502338097 ps
CPU time 1154.78 seconds
Started Aug 12 06:09:47 PM PDT 24
Finished Aug 12 06:29:02 PM PDT 24
Peak memory 201652 kb
Host smart-bf65c0ed-307d-46e1-818d-b1d2cb3a3001
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803840612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2803840612
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1550039432
Short name T414
Test name
Test status
Simulation time 585800277969 ps
CPU time 1450.25 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:34:04 PM PDT 24
Peak memory 201632 kb
Host smart-529b2fd6-d4a3-4e14-96ab-be6604746b24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550039432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1550039432
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2159200709
Short name T52
Test name
Test status
Simulation time 76405117793 ps
CPU time 282.9 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:14:40 PM PDT 24
Peak memory 201916 kb
Host smart-ee7cfeb9-8e52-4de3-913f-1a1cd167f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159200709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2159200709
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2696375249
Short name T501
Test name
Test status
Simulation time 26896353132 ps
CPU time 61.09 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:10:59 PM PDT 24
Peak memory 201472 kb
Host smart-c2af71b6-2d0f-46c6-888d-cd9654ff73d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696375249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2696375249
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3631560474
Short name T512
Test name
Test status
Simulation time 4973356182 ps
CPU time 11.97 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:10:06 PM PDT 24
Peak memory 201480 kb
Host smart-d5eca9a4-59b8-4537-9ec5-d76749f894ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631560474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3631560474
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3699869405
Short name T548
Test name
Test status
Simulation time 5537421839 ps
CPU time 13.33 seconds
Started Aug 12 06:09:47 PM PDT 24
Finished Aug 12 06:10:00 PM PDT 24
Peak memory 201472 kb
Host smart-ee03a104-7460-475e-98f7-4ea8499faf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699869405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3699869405
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1968096077
Short name T707
Test name
Test status
Simulation time 180938563049 ps
CPU time 19.13 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:10:13 PM PDT 24
Peak memory 209928 kb
Host smart-5c2bfc53-8680-4ab2-a00f-6912bbfe8a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968096077 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1968096077
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1704100776
Short name T699
Test name
Test status
Simulation time 541422929 ps
CPU time 0.95 seconds
Started Aug 12 06:09:53 PM PDT 24
Finished Aug 12 06:09:54 PM PDT 24
Peak memory 201460 kb
Host smart-e2872732-4fcf-4019-8f16-ffb154d508e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704100776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1704100776
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3646312545
Short name T552
Test name
Test status
Simulation time 193822624806 ps
CPU time 160.62 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:12:38 PM PDT 24
Peak memory 201676 kb
Host smart-892417bb-38e4-4a6a-91e7-8167cdd9dcf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646312545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3646312545
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.494033005
Short name T293
Test name
Test status
Simulation time 499958506034 ps
CPU time 370.72 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:16:05 PM PDT 24
Peak memory 201656 kb
Host smart-c84cd099-160a-4ab8-b00f-f08b49c920cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494033005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.494033005
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.725239919
Short name T160
Test name
Test status
Simulation time 495716244334 ps
CPU time 197.13 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:13:16 PM PDT 24
Peak memory 201684 kb
Host smart-1fc4d04e-9d77-481e-8efc-df830b7a3869
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=725239919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.725239919
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3262120056
Short name T285
Test name
Test status
Simulation time 164601391033 ps
CPU time 87.33 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:11:25 PM PDT 24
Peak memory 201640 kb
Host smart-73a8fbc7-d885-42b1-82c5-8fd2f770d2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262120056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3262120056
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1180793062
Short name T438
Test name
Test status
Simulation time 163319241600 ps
CPU time 190.89 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:13:10 PM PDT 24
Peak memory 201620 kb
Host smart-26688bf8-a7d0-454b-974a-36485d008ff6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180793062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1180793062
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3549757111
Short name T669
Test name
Test status
Simulation time 416122189642 ps
CPU time 909.05 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 201660 kb
Host smart-c2cdbea9-88e0-4d59-993d-54627beeacab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549757111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3549757111
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4123332762
Short name T484
Test name
Test status
Simulation time 592341068661 ps
CPU time 107.86 seconds
Started Aug 12 06:09:51 PM PDT 24
Finished Aug 12 06:11:39 PM PDT 24
Peak memory 201664 kb
Host smart-c3790321-6872-4299-b586-fdcd2d97a55e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123332762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.4123332762
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2612872638
Short name T106
Test name
Test status
Simulation time 127996682667 ps
CPU time 458.51 seconds
Started Aug 12 06:09:53 PM PDT 24
Finished Aug 12 06:17:31 PM PDT 24
Peak memory 201928 kb
Host smart-6c5d5cca-cbc7-4b2f-859f-a86800d7fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612872638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2612872638
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3074459981
Short name T668
Test name
Test status
Simulation time 31200837920 ps
CPU time 67.7 seconds
Started Aug 12 06:09:54 PM PDT 24
Finished Aug 12 06:11:02 PM PDT 24
Peak memory 201488 kb
Host smart-68ca0af5-8600-4c33-878f-17d83972764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074459981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3074459981
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.114088554
Short name T736
Test name
Test status
Simulation time 5220884777 ps
CPU time 12.09 seconds
Started Aug 12 06:09:55 PM PDT 24
Finished Aug 12 06:10:07 PM PDT 24
Peak memory 201432 kb
Host smart-8a184f16-2039-4856-9b39-7d7be4fcd743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114088554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.114088554
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1255288080
Short name T621
Test name
Test status
Simulation time 6022376256 ps
CPU time 8.16 seconds
Started Aug 12 06:09:52 PM PDT 24
Finished Aug 12 06:10:00 PM PDT 24
Peak memory 201500 kb
Host smart-09ec5d44-efa4-49c2-a857-ea1e7075ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255288080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1255288080
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.74026933
Short name T199
Test name
Test status
Simulation time 6033928194 ps
CPU time 7.12 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:10:04 PM PDT 24
Peak memory 201508 kb
Host smart-07921a66-1cb6-494a-8700-285fcbf480a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74026933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.74026933
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3123767361
Short name T794
Test name
Test status
Simulation time 1595959641 ps
CPU time 4.61 seconds
Started Aug 12 06:09:53 PM PDT 24
Finished Aug 12 06:09:58 PM PDT 24
Peak memory 201532 kb
Host smart-5c2ad06b-a401-4b70-ae97-89b5a1496be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123767361 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3123767361
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1293250039
Short name T496
Test name
Test status
Simulation time 366022303 ps
CPU time 1.33 seconds
Started Aug 12 06:10:03 PM PDT 24
Finished Aug 12 06:10:05 PM PDT 24
Peak memory 201440 kb
Host smart-b6217085-017b-401d-8bdc-223ca99c3bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293250039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1293250039
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2348544908
Short name T164
Test name
Test status
Simulation time 491647872175 ps
CPU time 1100.06 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:28:19 PM PDT 24
Peak memory 201668 kb
Host smart-60867db5-ffa6-4800-bac1-97219fa815ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348544908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2348544908
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3971716264
Short name T9
Test name
Test status
Simulation time 487041900613 ps
CPU time 1064.46 seconds
Started Aug 12 06:10:04 PM PDT 24
Finished Aug 12 06:27:49 PM PDT 24
Peak memory 201716 kb
Host smart-8e6c1587-0c4e-4871-bf0c-053c4248aa45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971716264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3971716264
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1617813876
Short name T168
Test name
Test status
Simulation time 486939456189 ps
CPU time 275.11 seconds
Started Aug 12 06:09:57 PM PDT 24
Finished Aug 12 06:14:33 PM PDT 24
Peak memory 201700 kb
Host smart-6218a278-221f-41f5-880c-247bc0b0d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617813876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1617813876
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3637750788
Short name T459
Test name
Test status
Simulation time 161318938781 ps
CPU time 92.83 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:11:32 PM PDT 24
Peak memory 201664 kb
Host smart-36da13f1-4b23-4f7e-93ab-3efd78b12282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637750788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3637750788
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1376835678
Short name T286
Test name
Test status
Simulation time 177024342228 ps
CPU time 104.3 seconds
Started Aug 12 06:10:02 PM PDT 24
Finished Aug 12 06:11:46 PM PDT 24
Peak memory 201656 kb
Host smart-bc779213-0f83-44c8-a8ed-1c0e3e35487c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376835678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1376835678
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.52226470
Short name T566
Test name
Test status
Simulation time 201648279052 ps
CPU time 435.12 seconds
Started Aug 12 06:10:00 PM PDT 24
Finished Aug 12 06:17:15 PM PDT 24
Peak memory 201664 kb
Host smart-df480e3c-4792-44aa-a079-2d31e10978a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52226470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
dc_ctrl_filters_wakeup_fixed.52226470
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4054525555
Short name T529
Test name
Test status
Simulation time 86485358520 ps
CPU time 370.75 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:16:10 PM PDT 24
Peak memory 201920 kb
Host smart-56af21f6-adb7-4f48-8193-28ee51486641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054525555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4054525555
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2797021
Short name T726
Test name
Test status
Simulation time 30747544518 ps
CPU time 34.89 seconds
Started Aug 12 06:10:00 PM PDT 24
Finished Aug 12 06:10:35 PM PDT 24
Peak memory 201488 kb
Host smart-0cf2eba5-6fd5-46eb-ab90-164da347ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2797021
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1465736218
Short name T556
Test name
Test status
Simulation time 3219472153 ps
CPU time 1.86 seconds
Started Aug 12 06:10:01 PM PDT 24
Finished Aug 12 06:10:03 PM PDT 24
Peak memory 201492 kb
Host smart-81967ae4-ac2d-41c0-9bc0-ccf2e7c1e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465736218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1465736218
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2984576372
Short name T789
Test name
Test status
Simulation time 5705448237 ps
CPU time 6.88 seconds
Started Aug 12 06:09:55 PM PDT 24
Finished Aug 12 06:10:02 PM PDT 24
Peak memory 201460 kb
Host smart-5f33eafe-d772-47c7-b1c8-6be59087d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984576372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2984576372
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1027597639
Short name T39
Test name
Test status
Simulation time 39580808454 ps
CPU time 10.84 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:10:10 PM PDT 24
Peak memory 210200 kb
Host smart-6f3d78d4-e28d-4ba3-ac67-e7528062edf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027597639 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1027597639
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1178137006
Short name T467
Test name
Test status
Simulation time 297774508 ps
CPU time 1.01 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:10:07 PM PDT 24
Peak memory 201452 kb
Host smart-796ffea4-1b11-414e-a538-ba704d20f87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178137006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1178137006
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.894132755
Short name T710
Test name
Test status
Simulation time 407882664556 ps
CPU time 321.83 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:15:28 PM PDT 24
Peak memory 201556 kb
Host smart-abf86dd1-560d-4f2a-8f57-aeba5a46d4a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894132755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.894132755
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1884417167
Short name T325
Test name
Test status
Simulation time 187885012349 ps
CPU time 113.64 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:12:00 PM PDT 24
Peak memory 201652 kb
Host smart-7629e69f-6ed9-42cf-b410-dcb6cd458d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884417167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1884417167
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2656350268
Short name T735
Test name
Test status
Simulation time 163957729661 ps
CPU time 342.43 seconds
Started Aug 12 06:10:05 PM PDT 24
Finished Aug 12 06:15:48 PM PDT 24
Peak memory 201636 kb
Host smart-928d4c94-de4a-4713-b286-5c6057737dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656350268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2656350268
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4165267864
Short name T161
Test name
Test status
Simulation time 157706814446 ps
CPU time 67.17 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:11:14 PM PDT 24
Peak memory 201664 kb
Host smart-cc1ca409-8ae2-4fbf-a8f4-22ddc9d8d06f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165267864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4165267864
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3883522617
Short name T737
Test name
Test status
Simulation time 171423865388 ps
CPU time 209.97 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:13:29 PM PDT 24
Peak memory 201644 kb
Host smart-064e9d3c-177e-4df6-9866-74f5ddc99d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883522617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3883522617
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.488855253
Short name T515
Test name
Test status
Simulation time 489690949057 ps
CPU time 1108.12 seconds
Started Aug 12 06:10:05 PM PDT 24
Finished Aug 12 06:28:33 PM PDT 24
Peak memory 201632 kb
Host smart-00f0e44f-f013-45eb-8ad0-dbc714b892b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=488855253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.488855253
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2892491905
Short name T295
Test name
Test status
Simulation time 370512190222 ps
CPU time 863.67 seconds
Started Aug 12 06:10:11 PM PDT 24
Finished Aug 12 06:24:35 PM PDT 24
Peak memory 201628 kb
Host smart-092ca46b-4945-4156-a460-bc1fb9646acb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892491905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2892491905
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3828738722
Short name T421
Test name
Test status
Simulation time 201272246926 ps
CPU time 119.58 seconds
Started Aug 12 06:10:09 PM PDT 24
Finished Aug 12 06:12:09 PM PDT 24
Peak memory 201656 kb
Host smart-07960ef9-0e2b-442f-af59-241adec9d6d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828738722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3828738722
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3675831753
Short name T349
Test name
Test status
Simulation time 100651242081 ps
CPU time 473.34 seconds
Started Aug 12 06:10:09 PM PDT 24
Finished Aug 12 06:18:03 PM PDT 24
Peak memory 201900 kb
Host smart-6668cb79-734b-45cc-884f-a23018fbb87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675831753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3675831753
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.917910889
Short name T636
Test name
Test status
Simulation time 28094735743 ps
CPU time 19.48 seconds
Started Aug 12 06:10:08 PM PDT 24
Finished Aug 12 06:10:28 PM PDT 24
Peak memory 201448 kb
Host smart-fc8189f6-c17d-4a27-a774-7b0b04e0c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917910889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.917910889
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3194976845
Short name T641
Test name
Test status
Simulation time 3678369028 ps
CPU time 2.94 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:10:09 PM PDT 24
Peak memory 201432 kb
Host smart-f1aeb7c0-47b0-4802-80c5-02748d40613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194976845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3194976845
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1072811512
Short name T393
Test name
Test status
Simulation time 6076675899 ps
CPU time 8.03 seconds
Started Aug 12 06:09:59 PM PDT 24
Finished Aug 12 06:10:07 PM PDT 24
Peak memory 201488 kb
Host smart-edf81d0a-0bee-433c-a0e9-8484dfae3b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072811512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1072811512
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3290163438
Short name T141
Test name
Test status
Simulation time 338976389901 ps
CPU time 771.67 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:22:58 PM PDT 24
Peak memory 201696 kb
Host smart-57f799c0-a6d2-4f7e-82f5-fe3dd42ff3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290163438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3290163438
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.393700880
Short name T353
Test name
Test status
Simulation time 110187797790 ps
CPU time 12.58 seconds
Started Aug 12 06:10:06 PM PDT 24
Finished Aug 12 06:10:19 PM PDT 24
Peak memory 210012 kb
Host smart-1655e7ee-bfe6-413d-a163-55e8a27c6f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393700880 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.393700880
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1774922557
Short name T601
Test name
Test status
Simulation time 433321814 ps
CPU time 0.82 seconds
Started Aug 12 06:10:12 PM PDT 24
Finished Aug 12 06:10:13 PM PDT 24
Peak memory 201460 kb
Host smart-579f98b1-33fd-4641-b74d-cc9ed12488e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774922557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1774922557
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.787276906
Short name T148
Test name
Test status
Simulation time 330706732029 ps
CPU time 374.2 seconds
Started Aug 12 06:10:11 PM PDT 24
Finished Aug 12 06:16:25 PM PDT 24
Peak memory 201632 kb
Host smart-2283f370-7ab5-4fbc-bb6b-6b2fd0ca18a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787276906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.787276906
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3957564618
Short name T466
Test name
Test status
Simulation time 328672543854 ps
CPU time 731.47 seconds
Started Aug 12 06:10:09 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 201736 kb
Host smart-73f0e39b-da1d-42d5-88a5-f00ebc0b9f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957564618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3957564618
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3655152692
Short name T167
Test name
Test status
Simulation time 489292282168 ps
CPU time 613.78 seconds
Started Aug 12 06:10:10 PM PDT 24
Finished Aug 12 06:20:24 PM PDT 24
Peak memory 201684 kb
Host smart-e556bcec-46d9-4f6e-ad6c-65455bf3a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655152692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3655152692
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3669181091
Short name T778
Test name
Test status
Simulation time 331124082958 ps
CPU time 781.06 seconds
Started Aug 12 06:10:10 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 201648 kb
Host smart-4286ca2c-304f-49dc-87c7-c0062b31e9b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669181091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3669181091
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3120613654
Short name T535
Test name
Test status
Simulation time 198736207321 ps
CPU time 223.34 seconds
Started Aug 12 06:10:08 PM PDT 24
Finished Aug 12 06:13:52 PM PDT 24
Peak memory 201660 kb
Host smart-4b115f57-2468-4eed-b4ce-56abc182a5eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120613654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3120613654
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.91515603
Short name T711
Test name
Test status
Simulation time 32921574672 ps
CPU time 73.29 seconds
Started Aug 12 06:10:12 PM PDT 24
Finished Aug 12 06:11:26 PM PDT 24
Peak memory 201472 kb
Host smart-dd0c7377-128d-41f8-80fd-8671aa5fa368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91515603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.91515603
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.157137587
Short name T709
Test name
Test status
Simulation time 4370240002 ps
CPU time 3.16 seconds
Started Aug 12 06:10:16 PM PDT 24
Finished Aug 12 06:10:20 PM PDT 24
Peak memory 201476 kb
Host smart-257986a1-20ff-4744-8bf1-00f99ac08a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157137587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.157137587
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.657251943
Short name T753
Test name
Test status
Simulation time 5873861508 ps
CPU time 14.01 seconds
Started Aug 12 06:10:08 PM PDT 24
Finished Aug 12 06:10:22 PM PDT 24
Peak memory 201508 kb
Host smart-6e08ff20-cdcc-4c4b-ace1-87c7e40615fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657251943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.657251943
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.708898983
Short name T333
Test name
Test status
Simulation time 386111972437 ps
CPU time 148.98 seconds
Started Aug 12 06:10:16 PM PDT 24
Finished Aug 12 06:12:45 PM PDT 24
Peak memory 201708 kb
Host smart-c5331f2c-a6e0-49db-be6f-a99c41f5e165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708898983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
708898983
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2587629529
Short name T727
Test name
Test status
Simulation time 2133612047 ps
CPU time 4.48 seconds
Started Aug 12 06:10:15 PM PDT 24
Finished Aug 12 06:10:20 PM PDT 24
Peak memory 201516 kb
Host smart-69859055-8a98-4cb5-b65c-3a7f1b7c1344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587629529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2587629529
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1430975552
Short name T431
Test name
Test status
Simulation time 519384967 ps
CPU time 1.18 seconds
Started Aug 12 06:10:21 PM PDT 24
Finished Aug 12 06:10:23 PM PDT 24
Peak memory 201416 kb
Host smart-7efe625c-3508-4f97-ae2c-6083ecc28498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430975552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1430975552
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.723879038
Short name T82
Test name
Test status
Simulation time 331791468422 ps
CPU time 195.74 seconds
Started Aug 12 06:10:11 PM PDT 24
Finished Aug 12 06:13:27 PM PDT 24
Peak memory 201736 kb
Host smart-4647b66e-7f55-4b9c-a595-87f67168237f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=723879038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.723879038
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.430305362
Short name T142
Test name
Test status
Simulation time 335071070523 ps
CPU time 264.94 seconds
Started Aug 12 06:10:12 PM PDT 24
Finished Aug 12 06:14:37 PM PDT 24
Peak memory 201616 kb
Host smart-d975f2fe-f9da-42a8-9a0e-85d6ab600b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430305362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.430305362
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2707650022
Short name T671
Test name
Test status
Simulation time 326430731373 ps
CPU time 103.36 seconds
Started Aug 12 06:10:15 PM PDT 24
Finished Aug 12 06:11:58 PM PDT 24
Peak memory 201636 kb
Host smart-4445e791-25e2-4a28-b0fa-2fc982021b61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707650022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2707650022
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.317171258
Short name T474
Test name
Test status
Simulation time 392275181635 ps
CPU time 235.17 seconds
Started Aug 12 06:10:15 PM PDT 24
Finished Aug 12 06:14:10 PM PDT 24
Peak memory 201640 kb
Host smart-cd388184-c5a3-4634-91f7-e59049c9dbbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317171258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.317171258
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2664135400
Short name T471
Test name
Test status
Simulation time 205028877978 ps
CPU time 467.57 seconds
Started Aug 12 06:10:16 PM PDT 24
Finished Aug 12 06:18:04 PM PDT 24
Peak memory 201656 kb
Host smart-c7e6f587-0422-4516-b957-c13875283d62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664135400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2664135400
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1522519323
Short name T49
Test name
Test status
Simulation time 111961566989 ps
CPU time 576.16 seconds
Started Aug 12 06:10:20 PM PDT 24
Finished Aug 12 06:19:57 PM PDT 24
Peak memory 201984 kb
Host smart-e9824ae9-cb74-4c9d-86c1-85083e63c5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522519323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1522519323
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2355990539
Short name T534
Test name
Test status
Simulation time 44805052994 ps
CPU time 25.61 seconds
Started Aug 12 06:10:20 PM PDT 24
Finished Aug 12 06:10:46 PM PDT 24
Peak memory 201500 kb
Host smart-31e08bc2-19b1-484d-aa12-8452f985d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355990539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2355990539
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3562123031
Short name T400
Test name
Test status
Simulation time 4158256979 ps
CPU time 2.84 seconds
Started Aug 12 06:10:18 PM PDT 24
Finished Aug 12 06:10:21 PM PDT 24
Peak memory 201504 kb
Host smart-f99c3be3-1686-47a1-9a98-f34eb1baf28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562123031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3562123031
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4089122557
Short name T586
Test name
Test status
Simulation time 5803340328 ps
CPU time 1.56 seconds
Started Aug 12 06:10:12 PM PDT 24
Finished Aug 12 06:10:14 PM PDT 24
Peak memory 201492 kb
Host smart-9afb5701-1554-4593-96a2-e0586c13c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089122557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4089122557
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3854842556
Short name T570
Test name
Test status
Simulation time 4643576280 ps
CPU time 6.78 seconds
Started Aug 12 06:10:17 PM PDT 24
Finished Aug 12 06:10:24 PM PDT 24
Peak memory 201544 kb
Host smart-63f00699-0a52-432f-9cc0-f90bb1a51884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854842556 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3854842556
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3869105929
Short name T652
Test name
Test status
Simulation time 303123292 ps
CPU time 0.82 seconds
Started Aug 12 06:10:24 PM PDT 24
Finished Aug 12 06:10:25 PM PDT 24
Peak memory 201396 kb
Host smart-4bf76715-57e2-4cb1-b7fa-27f1d5b57a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869105929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3869105929
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1938048569
Short name T334
Test name
Test status
Simulation time 558856988461 ps
CPU time 644.14 seconds
Started Aug 12 06:10:24 PM PDT 24
Finished Aug 12 06:21:09 PM PDT 24
Peak memory 201676 kb
Host smart-49f2e78a-1aaa-4aef-914f-20471a641992
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938048569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1938048569
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3716958882
Short name T159
Test name
Test status
Simulation time 491099914991 ps
CPU time 260.35 seconds
Started Aug 12 06:10:25 PM PDT 24
Finished Aug 12 06:14:45 PM PDT 24
Peak memory 201656 kb
Host smart-d2349af2-43a7-4a4a-8293-03c8dc8b97d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716958882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3716958882
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3472615386
Short name T313
Test name
Test status
Simulation time 326991856924 ps
CPU time 205.03 seconds
Started Aug 12 06:10:19 PM PDT 24
Finished Aug 12 06:13:45 PM PDT 24
Peak memory 201608 kb
Host smart-9a5fe456-b6a0-4f94-a87a-f0c8107ee1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472615386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3472615386
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2168738097
Short name T493
Test name
Test status
Simulation time 324747323983 ps
CPU time 169.34 seconds
Started Aug 12 06:10:19 PM PDT 24
Finished Aug 12 06:13:09 PM PDT 24
Peak memory 201668 kb
Host smart-ce5556a1-07a4-4370-be67-95ea7fc6fb9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168738097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2168738097
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1759670067
Short name T491
Test name
Test status
Simulation time 189435557229 ps
CPU time 444.14 seconds
Started Aug 12 06:10:26 PM PDT 24
Finished Aug 12 06:17:50 PM PDT 24
Peak memory 201688 kb
Host smart-a3845f99-c110-4621-ab8b-748be2416b20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759670067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1759670067
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1029581021
Short name T718
Test name
Test status
Simulation time 197102553751 ps
CPU time 112.72 seconds
Started Aug 12 06:10:25 PM PDT 24
Finished Aug 12 06:12:18 PM PDT 24
Peak memory 201624 kb
Host smart-8203d5aa-fac1-440f-aab6-d013a0f51023
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029581021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1029581021
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.386786477
Short name T660
Test name
Test status
Simulation time 37988125585 ps
CPU time 90.76 seconds
Started Aug 12 06:10:24 PM PDT 24
Finished Aug 12 06:11:55 PM PDT 24
Peak memory 201396 kb
Host smart-00bce03c-1da9-4226-a75d-b4c277ca2a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386786477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.386786477
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1245279894
Short name T463
Test name
Test status
Simulation time 4961416962 ps
CPU time 12.1 seconds
Started Aug 12 06:10:25 PM PDT 24
Finished Aug 12 06:10:37 PM PDT 24
Peak memory 201488 kb
Host smart-53abe9a2-4af8-4918-a546-0797904720f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245279894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1245279894
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3758206309
Short name T455
Test name
Test status
Simulation time 5609093694 ps
CPU time 12.87 seconds
Started Aug 12 06:10:21 PM PDT 24
Finished Aug 12 06:10:34 PM PDT 24
Peak memory 201540 kb
Host smart-41612ff3-5772-4050-830b-f4305658c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758206309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3758206309
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3779036939
Short name T139
Test name
Test status
Simulation time 356993145379 ps
CPU time 1119.53 seconds
Started Aug 12 06:10:24 PM PDT 24
Finished Aug 12 06:29:04 PM PDT 24
Peak memory 210072 kb
Host smart-1509fff1-981e-4f33-b22a-78a698d0e9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779036939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3779036939
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.396652859
Short name T752
Test name
Test status
Simulation time 60209768198 ps
CPU time 11.47 seconds
Started Aug 12 06:10:26 PM PDT 24
Finished Aug 12 06:10:38 PM PDT 24
Peak memory 209852 kb
Host smart-1d96f629-f8e3-424a-9bf6-fffb591e88dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396652859 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.396652859
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.964378837
Short name T429
Test name
Test status
Simulation time 489511717 ps
CPU time 0.75 seconds
Started Aug 12 06:10:34 PM PDT 24
Finished Aug 12 06:10:34 PM PDT 24
Peak memory 201460 kb
Host smart-89db78b2-61eb-4a00-a58d-558cb9f6ca63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964378837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.964378837
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3879905413
Short name T741
Test name
Test status
Simulation time 562746591219 ps
CPU time 1403.69 seconds
Started Aug 12 06:10:32 PM PDT 24
Finished Aug 12 06:33:56 PM PDT 24
Peak memory 201664 kb
Host smart-4b932b91-73f6-448b-ba6f-79ed8e11a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879905413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3879905413
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3716505564
Short name T521
Test name
Test status
Simulation time 335398558297 ps
CPU time 404.85 seconds
Started Aug 12 06:10:32 PM PDT 24
Finished Aug 12 06:17:17 PM PDT 24
Peak memory 201636 kb
Host smart-9d004588-6116-4d87-95b4-5da3be3e4739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716505564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3716505564
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2712320069
Short name T492
Test name
Test status
Simulation time 491955686547 ps
CPU time 610.7 seconds
Started Aug 12 06:10:33 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 201716 kb
Host smart-6dcb68a4-540a-4b9b-8d86-de8f9b2b83fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712320069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2712320069
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2855146201
Short name T112
Test name
Test status
Simulation time 166586968531 ps
CPU time 379.47 seconds
Started Aug 12 06:10:34 PM PDT 24
Finished Aug 12 06:16:53 PM PDT 24
Peak memory 201724 kb
Host smart-f3e14446-2b9c-4464-bed5-faba122a4082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855146201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2855146201
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.984389183
Short name T633
Test name
Test status
Simulation time 495357953385 ps
CPU time 558.65 seconds
Started Aug 12 06:10:33 PM PDT 24
Finished Aug 12 06:19:52 PM PDT 24
Peak memory 201668 kb
Host smart-5fe33c59-f805-49cb-8ac0-ad58fcbefb43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=984389183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.984389183
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.386161937
Short name T29
Test name
Test status
Simulation time 514443228632 ps
CPU time 127.69 seconds
Started Aug 12 06:10:31 PM PDT 24
Finished Aug 12 06:12:39 PM PDT 24
Peak memory 201640 kb
Host smart-7191d926-12c2-4432-a18f-d0cdf74d837f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386161937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.386161937
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3357204662
Short name T426
Test name
Test status
Simulation time 405243424539 ps
CPU time 871.25 seconds
Started Aug 12 06:10:30 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 201664 kb
Host smart-1d2d54c4-613d-4528-b972-3e5a366d7ade
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357204662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3357204662
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2482978552
Short name T693
Test name
Test status
Simulation time 38611382205 ps
CPU time 47.94 seconds
Started Aug 12 06:10:31 PM PDT 24
Finished Aug 12 06:11:19 PM PDT 24
Peak memory 201472 kb
Host smart-e7ca1658-11a9-484a-b1dc-36125ee726bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482978552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2482978552
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1430421069
Short name T762
Test name
Test status
Simulation time 4859312645 ps
CPU time 2.67 seconds
Started Aug 12 06:10:30 PM PDT 24
Finished Aug 12 06:10:33 PM PDT 24
Peak memory 201500 kb
Host smart-d68102de-f77f-46e6-8b30-c2b39174d899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430421069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1430421069
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2612552085
Short name T507
Test name
Test status
Simulation time 5729883497 ps
CPU time 2.86 seconds
Started Aug 12 06:10:24 PM PDT 24
Finished Aug 12 06:10:27 PM PDT 24
Peak memory 201484 kb
Host smart-548931bd-87d1-47fa-bb90-a3265c87bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612552085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2612552085
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4015198142
Short name T783
Test name
Test status
Simulation time 366659226530 ps
CPU time 832.54 seconds
Started Aug 12 06:10:34 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 201708 kb
Host smart-ebaa2f21-2aff-41f8-8cad-0561fd86a02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015198142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4015198142
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3047902287
Short name T771
Test name
Test status
Simulation time 1210953149 ps
CPU time 5.26 seconds
Started Aug 12 06:10:36 PM PDT 24
Finished Aug 12 06:10:42 PM PDT 24
Peak memory 201724 kb
Host smart-2b6b8fba-8ffb-4fbb-8ab7-cf3e1c991bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047902287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3047902287
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3015078034
Short name T494
Test name
Test status
Simulation time 449983278 ps
CPU time 1.62 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:08:51 PM PDT 24
Peak memory 201448 kb
Host smart-9e6ecb28-6e6d-4538-ab66-6a319966edef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015078034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3015078034
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.167803667
Short name T558
Test name
Test status
Simulation time 341602187494 ps
CPU time 334.78 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:14:30 PM PDT 24
Peak memory 201680 kb
Host smart-53beb7a5-2bdd-49af-b49b-10adc23f1752
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167803667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.167803667
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2044361201
Short name T93
Test name
Test status
Simulation time 329324886202 ps
CPU time 722.22 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 201668 kb
Host smart-08466678-d22d-4e50-8c81-8ed27f0bd6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044361201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2044361201
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1155073737
Short name T523
Test name
Test status
Simulation time 494746863055 ps
CPU time 297.01 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:13:46 PM PDT 24
Peak memory 201632 kb
Host smart-b95b57fe-8a9b-4e31-ae00-30435954c330
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155073737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1155073737
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3600544195
Short name T627
Test name
Test status
Simulation time 329089947757 ps
CPU time 202 seconds
Started Aug 12 06:08:48 PM PDT 24
Finished Aug 12 06:12:10 PM PDT 24
Peak memory 201664 kb
Host smart-cdb09968-2907-45ae-8aad-d2e028a65efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600544195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3600544195
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1122340297
Short name T684
Test name
Test status
Simulation time 324133160191 ps
CPU time 715.19 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:20:51 PM PDT 24
Peak memory 201696 kb
Host smart-7111be46-61c9-465a-979d-fbc36383d323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122340297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1122340297
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2266318962
Short name T527
Test name
Test status
Simulation time 401942211039 ps
CPU time 226 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:12:42 PM PDT 24
Peak memory 201656 kb
Host smart-f579465f-f977-49cc-a46a-1e89e99029d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266318962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2266318962
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1964181628
Short name T797
Test name
Test status
Simulation time 102531253478 ps
CPU time 405.74 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:15:42 PM PDT 24
Peak memory 201924 kb
Host smart-b47072d8-f094-4cef-a5af-4339fd77acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964181628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1964181628
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3755552690
Short name T366
Test name
Test status
Simulation time 33087291729 ps
CPU time 17.99 seconds
Started Aug 12 06:08:50 PM PDT 24
Finished Aug 12 06:09:08 PM PDT 24
Peak memory 201432 kb
Host smart-d6919f63-6e6b-473e-a3a7-2fad4fa7d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755552690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3755552690
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3795041502
Short name T454
Test name
Test status
Simulation time 4332203612 ps
CPU time 12.02 seconds
Started Aug 12 06:08:51 PM PDT 24
Finished Aug 12 06:09:03 PM PDT 24
Peak memory 201500 kb
Host smart-02d01397-1709-4843-af68-fcb0bfb64eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795041502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3795041502
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.967970115
Short name T65
Test name
Test status
Simulation time 4294504101 ps
CPU time 3.93 seconds
Started Aug 12 06:08:49 PM PDT 24
Finished Aug 12 06:08:53 PM PDT 24
Peak memory 217088 kb
Host smart-341ff5a9-bf0d-4d7f-ac6e-6163a6290955
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967970115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.967970115
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2456312761
Short name T557
Test name
Test status
Simulation time 5973778357 ps
CPU time 15.16 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:09:07 PM PDT 24
Peak memory 201452 kb
Host smart-c94f2923-304a-4cf5-91e5-211d61186022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456312761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2456312761
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.148634029
Short name T543
Test name
Test status
Simulation time 20434697378 ps
CPU time 4.39 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:08:56 PM PDT 24
Peak memory 209924 kb
Host smart-5d5aea83-fe83-465e-9d9d-0bbb73a2d838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148634029 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.148634029
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.703880503
Short name T745
Test name
Test status
Simulation time 371179596 ps
CPU time 1.42 seconds
Started Aug 12 06:10:44 PM PDT 24
Finished Aug 12 06:10:45 PM PDT 24
Peak memory 201444 kb
Host smart-5edffe4f-3187-4f30-90b9-556c445080a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703880503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.703880503
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2842131774
Short name T336
Test name
Test status
Simulation time 374275899672 ps
CPU time 874.46 seconds
Started Aug 12 06:10:38 PM PDT 24
Finished Aug 12 06:25:13 PM PDT 24
Peak memory 201696 kb
Host smart-41c9ed60-e68c-43e1-83ec-19153f76b499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842131774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2842131774
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2005014579
Short name T237
Test name
Test status
Simulation time 166898107013 ps
CPU time 382.25 seconds
Started Aug 12 06:10:38 PM PDT 24
Finished Aug 12 06:17:00 PM PDT 24
Peak memory 201652 kb
Host smart-c33b6a77-78de-4385-ae49-9dccf7d4bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005014579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2005014579
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.790368189
Short name T185
Test name
Test status
Simulation time 164971939612 ps
CPU time 94.93 seconds
Started Aug 12 06:10:38 PM PDT 24
Finished Aug 12 06:12:13 PM PDT 24
Peak memory 201676 kb
Host smart-44f9d21e-ea8a-4745-b551-e8625e45349e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=790368189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.790368189
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2267227660
Short name T314
Test name
Test status
Simulation time 483782339049 ps
CPU time 1015.11 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:27:39 PM PDT 24
Peak memory 201680 kb
Host smart-525804e3-754e-4da3-8d99-5bc9daa62aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267227660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2267227660
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1321376255
Short name T473
Test name
Test status
Simulation time 331722435311 ps
CPU time 203.73 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:14:07 PM PDT 24
Peak memory 201684 kb
Host smart-c3651441-ce62-445c-b610-4e4a3d6e7825
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321376255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1321376255
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2523328987
Short name T244
Test name
Test status
Simulation time 191326361616 ps
CPU time 115.8 seconds
Started Aug 12 06:10:41 PM PDT 24
Finished Aug 12 06:12:37 PM PDT 24
Peak memory 201648 kb
Host smart-c35e5dbe-efc2-4dd2-99c5-a2a1cbe343a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523328987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2523328987
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2993877371
Short name T615
Test name
Test status
Simulation time 202364680798 ps
CPU time 111 seconds
Started Aug 12 06:10:39 PM PDT 24
Finished Aug 12 06:12:30 PM PDT 24
Peak memory 201636 kb
Host smart-299088cd-f8cf-49d8-bb1d-c1926a6a40b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993877371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2993877371
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3455280054
Short name T53
Test name
Test status
Simulation time 133253986243 ps
CPU time 631.36 seconds
Started Aug 12 06:10:37 PM PDT 24
Finished Aug 12 06:21:09 PM PDT 24
Peak memory 201976 kb
Host smart-1840b3d5-a0be-4da3-b8ed-93ae94557aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455280054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3455280054
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3736336667
Short name T765
Test name
Test status
Simulation time 27051965656 ps
CPU time 65.13 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:11:49 PM PDT 24
Peak memory 201512 kb
Host smart-6f434571-fbbe-486e-b99f-e2c5e051c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736336667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3736336667
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3214047639
Short name T691
Test name
Test status
Simulation time 3361559327 ps
CPU time 4.56 seconds
Started Aug 12 06:10:40 PM PDT 24
Finished Aug 12 06:10:45 PM PDT 24
Peak memory 201512 kb
Host smart-e5bec7c8-a326-44e8-bec3-cbe4e8970cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214047639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3214047639
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1043014122
Short name T370
Test name
Test status
Simulation time 5737660391 ps
CPU time 14.75 seconds
Started Aug 12 06:10:38 PM PDT 24
Finished Aug 12 06:10:53 PM PDT 24
Peak memory 201452 kb
Host smart-4401afc6-6ea3-445e-b613-af48dd2a2399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043014122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1043014122
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3214988840
Short name T472
Test name
Test status
Simulation time 1742708442998 ps
CPU time 1375.37 seconds
Started Aug 12 06:10:42 PM PDT 24
Finished Aug 12 06:33:37 PM PDT 24
Peak memory 210048 kb
Host smart-b5169905-0171-4d28-b343-2b50ef4af059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214988840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3214988840
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1120025042
Short name T276
Test name
Test status
Simulation time 10257970643 ps
CPU time 13.24 seconds
Started Aug 12 06:10:37 PM PDT 24
Finished Aug 12 06:10:50 PM PDT 24
Peak memory 218344 kb
Host smart-1d84c11c-957b-4db3-bdd5-d907dce3649b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120025042 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1120025042
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3650507993
Short name T698
Test name
Test status
Simulation time 291927370 ps
CPU time 1.01 seconds
Started Aug 12 06:10:45 PM PDT 24
Finished Aug 12 06:10:46 PM PDT 24
Peak memory 201416 kb
Host smart-3eb9dd8e-49fe-4f54-9f09-6649a4aa7042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650507993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3650507993
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1826450058
Short name T620
Test name
Test status
Simulation time 167027601094 ps
CPU time 26.48 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:11:09 PM PDT 24
Peak memory 201732 kb
Host smart-74b83b89-ae4f-439f-84c5-861fcda688b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826450058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1826450058
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.186084902
Short name T265
Test name
Test status
Simulation time 166748522693 ps
CPU time 54.98 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:11:38 PM PDT 24
Peak memory 201724 kb
Host smart-e9514606-43b9-445b-8289-52635139801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186084902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.186084902
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2820697527
Short name T262
Test name
Test status
Simulation time 333029548144 ps
CPU time 747.41 seconds
Started Aug 12 06:10:47 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 201676 kb
Host smart-4753c86f-999d-40ed-842f-79cc1fae24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820697527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2820697527
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2882875681
Short name T375
Test name
Test status
Simulation time 488050282451 ps
CPU time 920.06 seconds
Started Aug 12 06:10:45 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 201752 kb
Host smart-b73ac495-8a03-4464-a0b1-961dc8e263ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882875681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2882875681
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2746289272
Short name T191
Test name
Test status
Simulation time 333999311619 ps
CPU time 119.01 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:12:42 PM PDT 24
Peak memory 201600 kb
Host smart-04991c2d-4c43-4052-b6c2-edc98c5516c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746289272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2746289272
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2532625625
Short name T387
Test name
Test status
Simulation time 319035405008 ps
CPU time 205.19 seconds
Started Aug 12 06:10:45 PM PDT 24
Finished Aug 12 06:14:10 PM PDT 24
Peak memory 201656 kb
Host smart-b36f07c0-c274-44e9-8d6f-d16f7c8e5d51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532625625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2532625625
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.853483188
Short name T240
Test name
Test status
Simulation time 542444349436 ps
CPU time 676.8 seconds
Started Aug 12 06:10:46 PM PDT 24
Finished Aug 12 06:22:03 PM PDT 24
Peak memory 201656 kb
Host smart-213cf056-d0cb-46cf-8e1f-a4b7be0be03e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853483188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.853483188
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3528629429
Short name T398
Test name
Test status
Simulation time 584061902902 ps
CPU time 694.26 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 201716 kb
Host smart-a3d7d238-c4f4-4f83-a266-87e202fcc7aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528629429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3528629429
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2742150708
Short name T743
Test name
Test status
Simulation time 79075638331 ps
CPU time 266.34 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:15:10 PM PDT 24
Peak memory 201980 kb
Host smart-7bfafaa1-2240-4b10-80b2-f3d116e43868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742150708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2742150708
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2256038390
Short name T643
Test name
Test status
Simulation time 42855515229 ps
CPU time 25.95 seconds
Started Aug 12 06:10:54 PM PDT 24
Finished Aug 12 06:11:20 PM PDT 24
Peak memory 201596 kb
Host smart-5685bb89-f1a1-40d5-96a2-07f031f77b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256038390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2256038390
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1182578472
Short name T462
Test name
Test status
Simulation time 3371155411 ps
CPU time 2.86 seconds
Started Aug 12 06:10:43 PM PDT 24
Finished Aug 12 06:10:46 PM PDT 24
Peak memory 201460 kb
Host smart-7bbfbfe0-6d77-40d9-9e87-fca39185af75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182578472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1182578472
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4146468448
Short name T728
Test name
Test status
Simulation time 5933308464 ps
CPU time 3.19 seconds
Started Aug 12 06:10:45 PM PDT 24
Finished Aug 12 06:10:48 PM PDT 24
Peak memory 201444 kb
Host smart-613553b2-d103-4bc2-b8af-58a1dd400ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146468448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4146468448
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4027373758
Short name T257
Test name
Test status
Simulation time 55810682514 ps
CPU time 12.96 seconds
Started Aug 12 06:10:54 PM PDT 24
Finished Aug 12 06:11:07 PM PDT 24
Peak memory 210300 kb
Host smart-21a1457b-b942-42ff-b284-4d0c59ee7c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027373758 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4027373758
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2822967329
Short name T94
Test name
Test status
Simulation time 395013646 ps
CPU time 0.84 seconds
Started Aug 12 06:10:55 PM PDT 24
Finished Aug 12 06:10:56 PM PDT 24
Peak memory 201456 kb
Host smart-7b4dddba-1d0f-4ca4-b79f-7b4e7e5dd19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822967329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2822967329
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2567095709
Short name T499
Test name
Test status
Simulation time 159746687876 ps
CPU time 361.07 seconds
Started Aug 12 06:10:51 PM PDT 24
Finished Aug 12 06:16:52 PM PDT 24
Peak memory 201676 kb
Host smart-b595c864-8cd4-48e2-98ac-46bfef7f61f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567095709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2567095709
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2181036473
Short name T3
Test name
Test status
Simulation time 496223250797 ps
CPU time 304.77 seconds
Started Aug 12 06:10:52 PM PDT 24
Finished Aug 12 06:15:57 PM PDT 24
Peak memory 201612 kb
Host smart-b138dc82-599d-47d5-90e7-3c359ead0393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181036473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2181036473
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2778151301
Short name T637
Test name
Test status
Simulation time 486340860684 ps
CPU time 99.6 seconds
Started Aug 12 06:10:50 PM PDT 24
Finished Aug 12 06:12:29 PM PDT 24
Peak memory 201624 kb
Host smart-8882fbc4-ceb8-41be-8e69-d43f79185c0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778151301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2778151301
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2863342819
Short name T299
Test name
Test status
Simulation time 487989671850 ps
CPU time 515.67 seconds
Started Aug 12 06:10:54 PM PDT 24
Finished Aug 12 06:19:29 PM PDT 24
Peak memory 201800 kb
Host smart-0068bdfc-c104-4240-87cc-3bb31f6b0295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863342819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2863342819
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1459045788
Short name T2
Test name
Test status
Simulation time 162360544887 ps
CPU time 365.47 seconds
Started Aug 12 06:10:42 PM PDT 24
Finished Aug 12 06:16:48 PM PDT 24
Peak memory 201644 kb
Host smart-4ff61b33-64ae-4676-b7b0-2a8a60cb34f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459045788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1459045788
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.122640473
Short name T184
Test name
Test status
Simulation time 174289452351 ps
CPU time 414.88 seconds
Started Aug 12 06:10:52 PM PDT 24
Finished Aug 12 06:17:47 PM PDT 24
Peak memory 201656 kb
Host smart-681dd988-c066-4938-bcf1-18eebeac6cc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122640473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.122640473
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.34349572
Short name T7
Test name
Test status
Simulation time 608997709475 ps
CPU time 691.14 seconds
Started Aug 12 06:10:53 PM PDT 24
Finished Aug 12 06:22:25 PM PDT 24
Peak memory 201652 kb
Host smart-70606ceb-9faa-46d0-a4b0-4a18222ecaf8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.34349572
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3879723444
Short name T352
Test name
Test status
Simulation time 69238639190 ps
CPU time 329.81 seconds
Started Aug 12 06:10:59 PM PDT 24
Finished Aug 12 06:16:29 PM PDT 24
Peak memory 202052 kb
Host smart-eaa493df-7b1e-4180-9651-7d35be3981cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879723444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3879723444
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1405677718
Short name T386
Test name
Test status
Simulation time 24600375051 ps
CPU time 54 seconds
Started Aug 12 06:10:49 PM PDT 24
Finished Aug 12 06:11:43 PM PDT 24
Peak memory 201484 kb
Host smart-94550c57-b866-4310-98b6-f7a99cc89df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405677718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1405677718
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1103770750
Short name T766
Test name
Test status
Simulation time 4067722439 ps
CPU time 9.58 seconds
Started Aug 12 06:10:52 PM PDT 24
Finished Aug 12 06:11:02 PM PDT 24
Peak memory 201452 kb
Host smart-e5801bd4-b3c2-4f04-b987-bde8977ad5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103770750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1103770750
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1788845860
Short name T587
Test name
Test status
Simulation time 6126882459 ps
CPU time 7.68 seconds
Started Aug 12 06:10:46 PM PDT 24
Finished Aug 12 06:10:54 PM PDT 24
Peak memory 201488 kb
Host smart-4beaa049-e61e-4d2f-9fb2-7a3b601fb6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788845860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1788845860
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1092002917
Short name T13
Test name
Test status
Simulation time 80461600848 ps
CPU time 24.3 seconds
Started Aug 12 06:10:57 PM PDT 24
Finished Aug 12 06:11:22 PM PDT 24
Peak memory 217620 kb
Host smart-b9fcb525-96de-4581-b710-aea5aea58755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092002917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1092002917
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2413086003
Short name T750
Test name
Test status
Simulation time 517491783 ps
CPU time 1.32 seconds
Started Aug 12 06:11:04 PM PDT 24
Finished Aug 12 06:11:05 PM PDT 24
Peak memory 201440 kb
Host smart-1da814d8-71f9-49d5-ad7b-70947e224c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413086003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2413086003
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.596834691
Short name T111
Test name
Test status
Simulation time 323113516940 ps
CPU time 608.29 seconds
Started Aug 12 06:11:06 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 201816 kb
Host smart-3a3bb5f0-f14e-4003-a5d4-b3d9024db538
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596834691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.596834691
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3933611113
Short name T172
Test name
Test status
Simulation time 502259984123 ps
CPU time 299.36 seconds
Started Aug 12 06:11:06 PM PDT 24
Finished Aug 12 06:16:05 PM PDT 24
Peak memory 201812 kb
Host smart-2edd7873-b2ed-4adc-9cc9-66a95d2997d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933611113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3933611113
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.977367483
Short name T746
Test name
Test status
Simulation time 323123831541 ps
CPU time 719.86 seconds
Started Aug 12 06:11:05 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 201788 kb
Host smart-f80b1023-6f95-489e-9a69-8eac0799830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977367483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.977367483
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1739484311
Short name T550
Test name
Test status
Simulation time 167144762701 ps
CPU time 383.93 seconds
Started Aug 12 06:11:06 PM PDT 24
Finished Aug 12 06:17:30 PM PDT 24
Peak memory 201848 kb
Host smart-f51bc594-009e-4dbd-8860-60162fe86a53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739484311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1739484311
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2260956597
Short name T551
Test name
Test status
Simulation time 332042343066 ps
CPU time 749.51 seconds
Started Aug 12 06:10:56 PM PDT 24
Finished Aug 12 06:23:26 PM PDT 24
Peak memory 201644 kb
Host smart-d7661ec0-ac03-4144-9c6c-c2c786e6948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260956597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2260956597
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1017375964
Short name T502
Test name
Test status
Simulation time 163902778975 ps
CPU time 173.54 seconds
Started Aug 12 06:10:59 PM PDT 24
Finished Aug 12 06:13:52 PM PDT 24
Peak memory 201660 kb
Host smart-dc167fda-4f10-4c47-9256-5401db376d48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017375964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1017375964
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2727881737
Short name T196
Test name
Test status
Simulation time 198261516205 ps
CPU time 106.56 seconds
Started Aug 12 06:10:57 PM PDT 24
Finished Aug 12 06:12:44 PM PDT 24
Peak memory 201668 kb
Host smart-291f940a-9956-4ac1-bbc5-c5270db88205
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727881737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2727881737
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3991733943
Short name T443
Test name
Test status
Simulation time 195656638656 ps
CPU time 112.41 seconds
Started Aug 12 06:10:56 PM PDT 24
Finished Aug 12 06:12:48 PM PDT 24
Peak memory 201696 kb
Host smart-a56f70cf-8293-48a6-b2e8-13978efa74c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991733943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3991733943
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1625122212
Short name T358
Test name
Test status
Simulation time 117756314551 ps
CPU time 381.11 seconds
Started Aug 12 06:11:01 PM PDT 24
Finished Aug 12 06:17:23 PM PDT 24
Peak memory 201932 kb
Host smart-84955089-f8a4-4bf5-a3dd-2476c79174c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625122212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1625122212
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.779681142
Short name T374
Test name
Test status
Simulation time 32524783666 ps
CPU time 21.03 seconds
Started Aug 12 06:11:04 PM PDT 24
Finished Aug 12 06:11:25 PM PDT 24
Peak memory 201544 kb
Host smart-713d3e9b-1e7e-42f6-ad4c-d10092a393ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779681142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.779681142
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2547450026
Short name T619
Test name
Test status
Simulation time 4492354744 ps
CPU time 6.03 seconds
Started Aug 12 06:11:05 PM PDT 24
Finished Aug 12 06:11:12 PM PDT 24
Peak memory 201512 kb
Host smart-c3095434-272a-4add-9a68-36b0084c1feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547450026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2547450026
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.778726235
Short name T655
Test name
Test status
Simulation time 5964043321 ps
CPU time 14.13 seconds
Started Aug 12 06:10:58 PM PDT 24
Finished Aug 12 06:11:12 PM PDT 24
Peak memory 201488 kb
Host smart-0e308b6b-dbdd-4bcc-b1ef-6b95b6aeeaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778726235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.778726235
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3414168939
Short name T155
Test name
Test status
Simulation time 331860390929 ps
CPU time 812.27 seconds
Started Aug 12 06:11:02 PM PDT 24
Finished Aug 12 06:24:35 PM PDT 24
Peak memory 201644 kb
Host smart-cc68a342-dbd6-43a4-b88b-a7d36bf6025e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414168939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3414168939
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1250764709
Short name T91
Test name
Test status
Simulation time 64685688081 ps
CPU time 8.93 seconds
Started Aug 12 06:11:03 PM PDT 24
Finished Aug 12 06:11:12 PM PDT 24
Peak memory 209976 kb
Host smart-634bd25c-c48c-45cc-87d5-42c79391a049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250764709 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1250764709
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3462027877
Short name T79
Test name
Test status
Simulation time 434045479 ps
CPU time 0.83 seconds
Started Aug 12 06:11:09 PM PDT 24
Finished Aug 12 06:11:10 PM PDT 24
Peak memory 201440 kb
Host smart-b7e56e69-d195-461e-afce-cd55d8146fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462027877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3462027877
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3432538383
Short name T618
Test name
Test status
Simulation time 343766172808 ps
CPU time 213.53 seconds
Started Aug 12 06:11:10 PM PDT 24
Finished Aug 12 06:14:44 PM PDT 24
Peak memory 201684 kb
Host smart-d85600ea-7e8e-4a84-8858-a0ac3ad0e55b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432538383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3432538383
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1634718940
Short name T654
Test name
Test status
Simulation time 563390117865 ps
CPU time 103.86 seconds
Started Aug 12 06:11:10 PM PDT 24
Finished Aug 12 06:12:54 PM PDT 24
Peak memory 201716 kb
Host smart-3fc6adf0-6d1f-4552-b8e1-37710d107767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634718940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1634718940
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1758884827
Short name T236
Test name
Test status
Simulation time 487787790347 ps
CPU time 299.27 seconds
Started Aug 12 06:11:01 PM PDT 24
Finished Aug 12 06:16:01 PM PDT 24
Peak memory 201632 kb
Host smart-0ee4a3e2-847b-49f5-9ae3-2ad8a01294bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758884827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1758884827
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3718838195
Short name T98
Test name
Test status
Simulation time 500703126936 ps
CPU time 1242.04 seconds
Started Aug 12 06:11:10 PM PDT 24
Finished Aug 12 06:31:52 PM PDT 24
Peak memory 201676 kb
Host smart-f9bf228c-67d8-4cc8-9d8a-ad58a6d54fee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718838195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3718838195
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.791759616
Short name T252
Test name
Test status
Simulation time 328163468607 ps
CPU time 342.49 seconds
Started Aug 12 06:11:03 PM PDT 24
Finished Aug 12 06:16:45 PM PDT 24
Peak memory 201648 kb
Host smart-bd433cc3-f0e3-4b39-b1af-e83fc709bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791759616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.791759616
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2693777693
Short name T432
Test name
Test status
Simulation time 483508391460 ps
CPU time 1146.88 seconds
Started Aug 12 06:11:05 PM PDT 24
Finished Aug 12 06:30:12 PM PDT 24
Peak memory 201680 kb
Host smart-5503bc7b-00b5-4686-9a9d-93dc65e74f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693777693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2693777693
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.638687630
Short name T99
Test name
Test status
Simulation time 171001410767 ps
CPU time 425.35 seconds
Started Aug 12 06:11:09 PM PDT 24
Finished Aug 12 06:18:14 PM PDT 24
Peak memory 201644 kb
Host smart-19c26e0c-f2b5-4264-b670-c26dc67ff80d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638687630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.638687630
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.76913934
Short name T600
Test name
Test status
Simulation time 197799951783 ps
CPU time 241.48 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:15:13 PM PDT 24
Peak memory 201676 kb
Host smart-f61e608a-c2dc-415c-8f96-de144d1f2083
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76913934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
dc_ctrl_filters_wakeup_fixed.76913934
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2540291937
Short name T219
Test name
Test status
Simulation time 104702283329 ps
CPU time 545.97 seconds
Started Aug 12 06:11:09 PM PDT 24
Finished Aug 12 06:20:15 PM PDT 24
Peak memory 201912 kb
Host smart-b5726d40-eb91-4299-b440-7ad64d9909be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540291937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2540291937
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2945711508
Short name T97
Test name
Test status
Simulation time 31499019595 ps
CPU time 77.37 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:12:29 PM PDT 24
Peak memory 201488 kb
Host smart-a4cad778-d7cc-4818-a276-f8742616cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945711508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2945711508
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.24019867
Short name T368
Test name
Test status
Simulation time 4948033469 ps
CPU time 3.62 seconds
Started Aug 12 06:11:10 PM PDT 24
Finished Aug 12 06:11:14 PM PDT 24
Peak memory 201496 kb
Host smart-f614b787-10a2-4837-ae6b-1d4713fcac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24019867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.24019867
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3381172577
Short name T661
Test name
Test status
Simulation time 5757778544 ps
CPU time 6.86 seconds
Started Aug 12 06:11:00 PM PDT 24
Finished Aug 12 06:11:07 PM PDT 24
Peak memory 201492 kb
Host smart-c9f4852f-7c3e-4daf-97ce-9e095f0c4846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381172577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3381172577
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1860515827
Short name T780
Test name
Test status
Simulation time 288864783257 ps
CPU time 404.78 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:17:56 PM PDT 24
Peak memory 201956 kb
Host smart-ec6ca62a-4f71-400d-8338-203df99b6caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860515827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1860515827
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4172376373
Short name T21
Test name
Test status
Simulation time 96198684554 ps
CPU time 5.53 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:11:17 PM PDT 24
Peak memory 201756 kb
Host smart-55520799-94e8-4ebb-a40e-513f9655b4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172376373 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4172376373
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.316818828
Short name T614
Test name
Test status
Simulation time 497981631 ps
CPU time 0.89 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:11:23 PM PDT 24
Peak memory 201444 kb
Host smart-25617d1d-0f28-497e-b754-4f0a26e15317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316818828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.316818828
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.849797080
Short name T332
Test name
Test status
Simulation time 374734826888 ps
CPU time 844.26 seconds
Started Aug 12 06:11:19 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 201676 kb
Host smart-c3b43f69-2095-40dc-84dc-0982e246e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849797080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.849797080
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.624805815
Short name T137
Test name
Test status
Simulation time 495340444315 ps
CPU time 288.65 seconds
Started Aug 12 06:11:23 PM PDT 24
Finished Aug 12 06:16:12 PM PDT 24
Peak memory 201644 kb
Host smart-b7ab75b7-97fc-4d47-b66e-1bad3ffaf8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624805815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.624805815
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1521299801
Short name T108
Test name
Test status
Simulation time 502916204471 ps
CPU time 582.24 seconds
Started Aug 12 06:11:23 PM PDT 24
Finished Aug 12 06:21:05 PM PDT 24
Peak memory 201732 kb
Host smart-e215e616-f184-477b-8cb8-201f98d2bdae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521299801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1521299801
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4250967025
Short name T146
Test name
Test status
Simulation time 334584959512 ps
CPU time 795.31 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:24:26 PM PDT 24
Peak memory 201628 kb
Host smart-2245bc0b-9b2b-41de-b990-5b6af7c49c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250967025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4250967025
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2674657892
Short name T591
Test name
Test status
Simulation time 163700091143 ps
CPU time 389.06 seconds
Started Aug 12 06:11:11 PM PDT 24
Finished Aug 12 06:17:41 PM PDT 24
Peak memory 201668 kb
Host smart-e5373dd5-9718-46b4-ac90-eb4a28ba6ca3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674657892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2674657892
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3118729393
Short name T84
Test name
Test status
Simulation time 366519760324 ps
CPU time 790.24 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:24:32 PM PDT 24
Peak memory 201616 kb
Host smart-be3bf738-b544-457f-b634-b8df273589f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118729393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3118729393
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3971966372
Short name T688
Test name
Test status
Simulation time 396889981961 ps
CPU time 215.69 seconds
Started Aug 12 06:11:21 PM PDT 24
Finished Aug 12 06:14:57 PM PDT 24
Peak memory 201660 kb
Host smart-bef1219a-bbfa-419c-a23f-9c90af00cf6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971966372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3971966372
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2766505687
Short name T562
Test name
Test status
Simulation time 84675525693 ps
CPU time 272.98 seconds
Started Aug 12 06:11:19 PM PDT 24
Finished Aug 12 06:15:52 PM PDT 24
Peak memory 201928 kb
Host smart-fe491c24-0800-4d02-8296-928796804b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766505687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2766505687
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3487726170
Short name T382
Test name
Test status
Simulation time 38600344832 ps
CPU time 21.77 seconds
Started Aug 12 06:11:20 PM PDT 24
Finished Aug 12 06:11:42 PM PDT 24
Peak memory 201492 kb
Host smart-393ae0b8-fb1f-46a6-ae45-7fadac62aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487726170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3487726170
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1993654556
Short name T415
Test name
Test status
Simulation time 3405093826 ps
CPU time 8.45 seconds
Started Aug 12 06:11:20 PM PDT 24
Finished Aug 12 06:11:29 PM PDT 24
Peak memory 201424 kb
Host smart-59ce331c-a670-443b-9972-510b155e0999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993654556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1993654556
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3708654503
Short name T406
Test name
Test status
Simulation time 5844146642 ps
CPU time 7.85 seconds
Started Aug 12 06:11:10 PM PDT 24
Finished Aug 12 06:11:18 PM PDT 24
Peak memory 201448 kb
Host smart-f6c9840f-2acd-4b3c-b0b9-06979ded295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708654503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3708654503
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1582257537
Short name T255
Test name
Test status
Simulation time 71633426485 ps
CPU time 10.98 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:11:33 PM PDT 24
Peak memory 201820 kb
Host smart-fada7e19-0a27-4974-b7ed-27f93dab1b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582257537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1582257537
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1822995391
Short name T779
Test name
Test status
Simulation time 505882053 ps
CPU time 1.77 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:11:31 PM PDT 24
Peak memory 201404 kb
Host smart-1b34edd3-0aad-4164-b11e-bf1df7298cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822995391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1822995391
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2273860873
Short name T742
Test name
Test status
Simulation time 507156370083 ps
CPU time 1118.06 seconds
Started Aug 12 06:11:24 PM PDT 24
Finished Aug 12 06:30:02 PM PDT 24
Peak memory 201620 kb
Host smart-a402e8d6-c68a-45ef-a838-a2a49ccebe1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273860873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2273860873
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3668825043
Short name T430
Test name
Test status
Simulation time 324459912195 ps
CPU time 793.25 seconds
Started Aug 12 06:11:24 PM PDT 24
Finished Aug 12 06:24:37 PM PDT 24
Peak memory 201696 kb
Host smart-01495b1e-34fe-4be9-875d-0f59fdcdfba6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668825043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3668825043
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1566502969
Short name T442
Test name
Test status
Simulation time 161330409306 ps
CPU time 333.44 seconds
Started Aug 12 06:11:21 PM PDT 24
Finished Aug 12 06:16:55 PM PDT 24
Peak memory 201680 kb
Host smart-e22e9a5d-2010-4b3e-bc30-489d5aae8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566502969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1566502969
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.495253579
Short name T457
Test name
Test status
Simulation time 497761303198 ps
CPU time 223.3 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:15:06 PM PDT 24
Peak memory 201664 kb
Host smart-bc472051-f347-4eaf-a4ad-2e5968a55d14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=495253579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.495253579
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.803953231
Short name T258
Test name
Test status
Simulation time 410792303964 ps
CPU time 743 seconds
Started Aug 12 06:11:21 PM PDT 24
Finished Aug 12 06:23:44 PM PDT 24
Peak memory 201676 kb
Host smart-56228390-1a6c-42f7-b269-f5789d9033f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803953231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.803953231
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3857416510
Short name T567
Test name
Test status
Simulation time 193694117732 ps
CPU time 108.12 seconds
Started Aug 12 06:11:23 PM PDT 24
Finished Aug 12 06:13:11 PM PDT 24
Peak memory 201692 kb
Host smart-b3294a7f-8830-498c-a70a-380ffe790b7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857416510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3857416510
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4278722021
Short name T210
Test name
Test status
Simulation time 103813469329 ps
CPU time 388.62 seconds
Started Aug 12 06:11:31 PM PDT 24
Finished Aug 12 06:17:59 PM PDT 24
Peak memory 201984 kb
Host smart-2b010ab7-afb3-41c9-827b-48b924b05afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278722021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4278722021
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3970603143
Short name T359
Test name
Test status
Simulation time 26196334896 ps
CPU time 27.97 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:11:57 PM PDT 24
Peak memory 201484 kb
Host smart-175cc88f-b135-4efa-845c-378b7b076abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970603143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3970603143
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3035242705
Short name T681
Test name
Test status
Simulation time 5024258036 ps
CPU time 13.23 seconds
Started Aug 12 06:11:20 PM PDT 24
Finished Aug 12 06:11:33 PM PDT 24
Peak memory 201436 kb
Host smart-8917710b-4ca4-4e01-860f-a51dfb786b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035242705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3035242705
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1714511092
Short name T713
Test name
Test status
Simulation time 5922590191 ps
CPU time 7.55 seconds
Started Aug 12 06:11:22 PM PDT 24
Finished Aug 12 06:11:29 PM PDT 24
Peak memory 201492 kb
Host smart-98622f66-33ac-4c89-8448-60643ff594a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714511092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1714511092
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2823769708
Short name T575
Test name
Test status
Simulation time 410450853594 ps
CPU time 978.86 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:27:48 PM PDT 24
Peak memory 201680 kb
Host smart-650e4ce4-07ff-493c-98f0-d4cc8a1c34f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823769708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2823769708
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2304178031
Short name T581
Test name
Test status
Simulation time 12356958845 ps
CPU time 8.32 seconds
Started Aug 12 06:11:28 PM PDT 24
Finished Aug 12 06:11:36 PM PDT 24
Peak memory 209944 kb
Host smart-0debda2f-81c1-444b-a533-ae450beceba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304178031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2304178031
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1695074966
Short name T759
Test name
Test status
Simulation time 362080972 ps
CPU time 1.38 seconds
Started Aug 12 06:11:33 PM PDT 24
Finished Aug 12 06:11:35 PM PDT 24
Peak memory 201448 kb
Host smart-26e407ca-7aab-4250-85be-645ac489eb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695074966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1695074966
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.304436003
Short name T232
Test name
Test status
Simulation time 170794894099 ps
CPU time 48.56 seconds
Started Aug 12 06:11:30 PM PDT 24
Finished Aug 12 06:12:18 PM PDT 24
Peak memory 201676 kb
Host smart-be5e0eb3-cbe9-429e-99e3-3efce0aa4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304436003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.304436003
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2747908809
Short name T171
Test name
Test status
Simulation time 485161027327 ps
CPU time 213.7 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:15:03 PM PDT 24
Peak memory 201612 kb
Host smart-76b4d439-0e57-4459-aa16-1cd5e2b3e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747908809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2747908809
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3093897792
Short name T617
Test name
Test status
Simulation time 165889144204 ps
CPU time 175.57 seconds
Started Aug 12 06:11:31 PM PDT 24
Finished Aug 12 06:14:27 PM PDT 24
Peak memory 201696 kb
Host smart-cf9939fb-8ed1-4ad7-8d65-65e5e2e05a3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093897792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3093897792
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.817774194
Short name T342
Test name
Test status
Simulation time 324560455697 ps
CPU time 365.71 seconds
Started Aug 12 06:11:30 PM PDT 24
Finished Aug 12 06:17:36 PM PDT 24
Peak memory 201664 kb
Host smart-9b17153a-eafe-4081-8451-94a7b09523e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817774194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.817774194
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.330815009
Short name T793
Test name
Test status
Simulation time 500273686013 ps
CPU time 1032.7 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:28:42 PM PDT 24
Peak memory 201680 kb
Host smart-c5b65557-9f40-4523-864c-0d20b2589e46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=330815009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.330815009
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.768587034
Short name T195
Test name
Test status
Simulation time 357682732470 ps
CPU time 393.59 seconds
Started Aug 12 06:11:29 PM PDT 24
Finished Aug 12 06:18:03 PM PDT 24
Peak memory 201620 kb
Host smart-379bbe83-7815-42d7-808a-48b1bcd78dda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768587034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.768587034
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.866176720
Short name T592
Test name
Test status
Simulation time 395790917427 ps
CPU time 436.89 seconds
Started Aug 12 06:11:30 PM PDT 24
Finished Aug 12 06:18:47 PM PDT 24
Peak memory 201660 kb
Host smart-5b27e286-1d28-48b0-9008-c649162b375b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866176720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.866176720
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.50035309
Short name T351
Test name
Test status
Simulation time 102594391715 ps
CPU time 357.3 seconds
Started Aug 12 06:11:33 PM PDT 24
Finished Aug 12 06:17:31 PM PDT 24
Peak memory 201940 kb
Host smart-dea6d140-dfc2-4280-97e9-eebc7f39733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50035309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.50035309
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3537113456
Short name T631
Test name
Test status
Simulation time 40803399096 ps
CPU time 25.35 seconds
Started Aug 12 06:11:33 PM PDT 24
Finished Aug 12 06:11:59 PM PDT 24
Peak memory 201492 kb
Host smart-318de9cd-ce37-47ce-a13c-074ff56cec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537113456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3537113456
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1190642864
Short name T439
Test name
Test status
Simulation time 3808319054 ps
CPU time 8.62 seconds
Started Aug 12 06:11:30 PM PDT 24
Finished Aug 12 06:11:38 PM PDT 24
Peak memory 201452 kb
Host smart-247027f7-91fb-4d1a-b61f-a5051919a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190642864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1190642864
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.596420276
Short name T572
Test name
Test status
Simulation time 5969761068 ps
CPU time 15.89 seconds
Started Aug 12 06:11:26 PM PDT 24
Finished Aug 12 06:11:42 PM PDT 24
Peak memory 201508 kb
Host smart-d490a748-3c5d-416f-9751-d0f95edc4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596420276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.596420276
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3649135585
Short name T321
Test name
Test status
Simulation time 174505405737 ps
CPU time 178.1 seconds
Started Aug 12 06:11:41 PM PDT 24
Finished Aug 12 06:14:39 PM PDT 24
Peak memory 201648 kb
Host smart-d29e4539-e53b-4f9b-9ee3-481739f3ad13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649135585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3649135585
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1891379214
Short name T761
Test name
Test status
Simulation time 5374666766 ps
CPU time 7.03 seconds
Started Aug 12 06:11:41 PM PDT 24
Finished Aug 12 06:11:48 PM PDT 24
Peak memory 201584 kb
Host smart-f2cee2f0-4b88-408b-bd36-5672d37749b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891379214 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1891379214
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3834692813
Short name T394
Test name
Test status
Simulation time 529643552 ps
CPU time 1.17 seconds
Started Aug 12 06:11:46 PM PDT 24
Finished Aug 12 06:11:47 PM PDT 24
Peak memory 201452 kb
Host smart-c9ac5bb4-de19-44c4-b3d6-591055b82a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834692813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3834692813
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2802659807
Short name T790
Test name
Test status
Simulation time 176962467440 ps
CPU time 411.57 seconds
Started Aug 12 06:11:41 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 201732 kb
Host smart-ed9f975a-42c9-43da-afb9-66b757a3c182
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802659807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2802659807
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3695213075
Short name T327
Test name
Test status
Simulation time 329319783778 ps
CPU time 709.51 seconds
Started Aug 12 06:11:34 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 201696 kb
Host smart-adf3256d-f384-4763-9eef-6533108a351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695213075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3695213075
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.375157564
Short name T702
Test name
Test status
Simulation time 488312839767 ps
CPU time 563.58 seconds
Started Aug 12 06:11:38 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 201692 kb
Host smart-7fad0aa7-26cf-4c7e-95db-35125230aeb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=375157564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.375157564
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3346455098
Short name T412
Test name
Test status
Simulation time 167371388681 ps
CPU time 185.58 seconds
Started Aug 12 06:11:39 PM PDT 24
Finished Aug 12 06:14:45 PM PDT 24
Peak memory 201644 kb
Host smart-f3a6c519-e724-440e-8ed4-7eb2cbfe3424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346455098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3346455098
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2694001544
Short name T577
Test name
Test status
Simulation time 497804280249 ps
CPU time 1197.44 seconds
Started Aug 12 06:11:41 PM PDT 24
Finished Aug 12 06:31:38 PM PDT 24
Peak memory 201644 kb
Host smart-930e4780-e9c0-4808-9860-8de621357c28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694001544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2694001544
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3936372795
Short name T4
Test name
Test status
Simulation time 545399929705 ps
CPU time 1308.4 seconds
Started Aug 12 06:11:39 PM PDT 24
Finished Aug 12 06:33:28 PM PDT 24
Peak memory 201640 kb
Host smart-85e2302b-969c-4978-9cdc-c8fcf539e993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936372795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3936372795
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1679129790
Short name T722
Test name
Test status
Simulation time 622252914908 ps
CPU time 372.75 seconds
Started Aug 12 06:11:39 PM PDT 24
Finished Aug 12 06:17:52 PM PDT 24
Peak memory 201644 kb
Host smart-2ce6065a-3115-4950-ab73-ca3af01e49af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679129790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1679129790
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.95596166
Short name T207
Test name
Test status
Simulation time 79416814488 ps
CPU time 280.57 seconds
Started Aug 12 06:11:38 PM PDT 24
Finished Aug 12 06:16:19 PM PDT 24
Peak memory 201912 kb
Host smart-165ad7cf-cf67-4a30-a9d0-b93e964ed00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95596166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.95596166
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3510788834
Short name T423
Test name
Test status
Simulation time 21822281578 ps
CPU time 23.95 seconds
Started Aug 12 06:11:41 PM PDT 24
Finished Aug 12 06:12:06 PM PDT 24
Peak memory 201480 kb
Host smart-cc415bed-60b9-4463-8d97-9746f1e70f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510788834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3510788834
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.435719050
Short name T734
Test name
Test status
Simulation time 3173464570 ps
CPU time 2.42 seconds
Started Aug 12 06:11:42 PM PDT 24
Finished Aug 12 06:11:44 PM PDT 24
Peak memory 201448 kb
Host smart-c590cb88-454b-4b5d-b4d8-66c76d3bc09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435719050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.435719050
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1503272134
Short name T508
Test name
Test status
Simulation time 5814447559 ps
CPU time 2.86 seconds
Started Aug 12 06:11:35 PM PDT 24
Finished Aug 12 06:11:38 PM PDT 24
Peak memory 201508 kb
Host smart-abb9923f-2e2d-44da-99ff-ce3c494b927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503272134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1503272134
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3031355967
Short name T361
Test name
Test status
Simulation time 11337328169 ps
CPU time 7.69 seconds
Started Aug 12 06:11:46 PM PDT 24
Finished Aug 12 06:11:54 PM PDT 24
Peak memory 201644 kb
Host smart-0a4b4dff-a2d3-419b-b9e1-c7f9a6382257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031355967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3031355967
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1132960631
Short name T18
Test name
Test status
Simulation time 2141748164 ps
CPU time 2.72 seconds
Started Aug 12 06:11:45 PM PDT 24
Finished Aug 12 06:11:48 PM PDT 24
Peak memory 201532 kb
Host smart-463537b0-fffe-4949-9fc1-f4ffa649539a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132960631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1132960631
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2379538858
Short name T651
Test name
Test status
Simulation time 364562369 ps
CPU time 0.8 seconds
Started Aug 12 06:11:50 PM PDT 24
Finished Aug 12 06:11:51 PM PDT 24
Peak memory 201384 kb
Host smart-e5fa5459-337a-4dd0-8575-7b4ef17b91d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379538858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2379538858
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2478396309
Short name T680
Test name
Test status
Simulation time 318637379467 ps
CPU time 439.49 seconds
Started Aug 12 06:11:44 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 201688 kb
Host smart-1e6875cd-62e2-4f35-a3e0-4d3a869abada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478396309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2478396309
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1411243759
Short name T268
Test name
Test status
Simulation time 323751165349 ps
CPU time 774.1 seconds
Started Aug 12 06:11:46 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 201668 kb
Host smart-5d0c8e0c-4842-4155-b30b-6d29ab3f7f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411243759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1411243759
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2020301771
Short name T373
Test name
Test status
Simulation time 498524799225 ps
CPU time 1147.43 seconds
Started Aug 12 06:11:46 PM PDT 24
Finished Aug 12 06:30:53 PM PDT 24
Peak memory 201732 kb
Host smart-b60e4778-232f-4d9c-9c51-e6395b21e358
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020301771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2020301771
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1531931963
Short name T323
Test name
Test status
Simulation time 328710580660 ps
CPU time 262.52 seconds
Started Aug 12 06:11:46 PM PDT 24
Finished Aug 12 06:16:08 PM PDT 24
Peak memory 201660 kb
Host smart-9edd9d28-df73-46cf-b9d8-68862aa5325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531931963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1531931963
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3035892258
Short name T689
Test name
Test status
Simulation time 330175309930 ps
CPU time 202.46 seconds
Started Aug 12 06:11:49 PM PDT 24
Finished Aug 12 06:15:12 PM PDT 24
Peak memory 201676 kb
Host smart-e061f037-9fe6-45a2-a7d7-55016c70e322
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035892258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3035892258
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3662048555
Short name T41
Test name
Test status
Simulation time 617071391936 ps
CPU time 1444.25 seconds
Started Aug 12 06:11:44 PM PDT 24
Finished Aug 12 06:35:49 PM PDT 24
Peak memory 201672 kb
Host smart-14505ff3-568a-485d-a1cc-9dd8ce421242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662048555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3662048555
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3011011796
Short name T418
Test name
Test status
Simulation time 590887597538 ps
CPU time 1451.08 seconds
Started Aug 12 06:11:48 PM PDT 24
Finished Aug 12 06:35:59 PM PDT 24
Peak memory 201660 kb
Host smart-994c3ac4-b970-4cec-8c5d-45da1c2dc1ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011011796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3011011796
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.182080274
Short name T434
Test name
Test status
Simulation time 125526552160 ps
CPU time 409.96 seconds
Started Aug 12 06:11:50 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 201956 kb
Host smart-e6e047c3-34d8-4217-941b-74e988fc85a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182080274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.182080274
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.317874626
Short name T770
Test name
Test status
Simulation time 31975445296 ps
CPU time 19.53 seconds
Started Aug 12 06:11:51 PM PDT 24
Finished Aug 12 06:12:11 PM PDT 24
Peak memory 201488 kb
Host smart-9adfe79d-f5a1-441c-9799-49033adfe93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317874626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.317874626
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3266235695
Short name T568
Test name
Test status
Simulation time 3769956372 ps
CPU time 8.82 seconds
Started Aug 12 06:11:53 PM PDT 24
Finished Aug 12 06:12:01 PM PDT 24
Peak memory 201504 kb
Host smart-5649e865-1a70-495c-a882-70901defa563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266235695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3266235695
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2708492541
Short name T687
Test name
Test status
Simulation time 5818610722 ps
CPU time 14.05 seconds
Started Aug 12 06:11:48 PM PDT 24
Finished Aug 12 06:12:02 PM PDT 24
Peak memory 201504 kb
Host smart-856475f0-59b2-4a29-b351-8fdc810f4399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708492541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2708492541
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2833601992
Short name T656
Test name
Test status
Simulation time 5688937505 ps
CPU time 4.15 seconds
Started Aug 12 06:11:53 PM PDT 24
Finished Aug 12 06:11:57 PM PDT 24
Peak memory 201564 kb
Host smart-1fd6841a-efb1-4fb0-ad37-2961bb68aec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833601992 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2833601992
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3010814222
Short name T380
Test name
Test status
Simulation time 395189607 ps
CPU time 1.44 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:08:56 PM PDT 24
Peak memory 201460 kb
Host smart-7edf3527-72c2-4480-855f-815544e9440a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010814222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3010814222
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3106239448
Short name T162
Test name
Test status
Simulation time 342382200237 ps
CPU time 153.51 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:11:31 PM PDT 24
Peak memory 201656 kb
Host smart-b71e8633-9116-4930-89e4-d5d5c14ace90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106239448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3106239448
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2729831308
Short name T225
Test name
Test status
Simulation time 185326245417 ps
CPU time 109.74 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:10:44 PM PDT 24
Peak memory 201676 kb
Host smart-b79d0a9d-7fee-49e8-bebc-5d4e360b56ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729831308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2729831308
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2459125104
Short name T720
Test name
Test status
Simulation time 161132804887 ps
CPU time 90.83 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:10:32 PM PDT 24
Peak memory 201660 kb
Host smart-2b223d0d-8fd8-44e8-9db5-e9ff32a5a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459125104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2459125104
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2742103281
Short name T440
Test name
Test status
Simulation time 493803004542 ps
CPU time 616.12 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:19:18 PM PDT 24
Peak memory 201732 kb
Host smart-ed2717a9-f5e9-47d0-8f81-d6237dd312af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742103281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2742103281
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4061014993
Short name T335
Test name
Test status
Simulation time 324543316331 ps
CPU time 199.76 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:12:16 PM PDT 24
Peak memory 201644 kb
Host smart-c88134f7-cc00-4954-b27a-c0dc95ff5fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061014993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4061014993
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2823493700
Short name T781
Test name
Test status
Simulation time 328867374900 ps
CPU time 442.88 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:16:17 PM PDT 24
Peak memory 201640 kb
Host smart-931d23d7-483f-44b0-8376-c1ab7309af9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823493700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2823493700
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1278119136
Short name T458
Test name
Test status
Simulation time 181233221311 ps
CPU time 421.8 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:15:53 PM PDT 24
Peak memory 201632 kb
Host smart-e9670c55-77f7-47e2-81f3-ad92b5448250
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278119136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1278119136
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.851814465
Short name T565
Test name
Test status
Simulation time 577103968848 ps
CPU time 1282.22 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:30:17 PM PDT 24
Peak memory 201600 kb
Host smart-c5f7bb4e-5367-47cb-8ff6-eb7d92302afc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851814465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.851814465
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2641027604
Short name T203
Test name
Test status
Simulation time 126779888659 ps
CPU time 471.39 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:16:44 PM PDT 24
Peak memory 201912 kb
Host smart-69030d2b-aaf7-4e61-ac04-884fa48efa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641027604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2641027604
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.433938604
Short name T518
Test name
Test status
Simulation time 43646927455 ps
CPU time 95.24 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:10:32 PM PDT 24
Peak memory 201496 kb
Host smart-6d8c723f-d35b-48fa-bf29-c72d9eb5ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433938604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.433938604
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1794898187
Short name T378
Test name
Test status
Simulation time 5315653933 ps
CPU time 13.38 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:09:09 PM PDT 24
Peak memory 201476 kb
Host smart-95334c88-b747-42f3-9dda-eed5e128ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794898187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1794898187
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1820108345
Short name T81
Test name
Test status
Simulation time 4023177335 ps
CPU time 2.95 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:08:59 PM PDT 24
Peak memory 217036 kb
Host smart-3c179370-fd28-4bf8-b1e8-525697f3bf09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820108345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1820108345
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3999659321
Short name T101
Test name
Test status
Simulation time 5755213017 ps
CPU time 2.01 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:08:58 PM PDT 24
Peak memory 201536 kb
Host smart-076b279f-eea2-45d7-8424-e85fb8601525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999659321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3999659321
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4006602850
Short name T200
Test name
Test status
Simulation time 363213881136 ps
CPU time 1405.42 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:32:20 PM PDT 24
Peak memory 201860 kb
Host smart-dce1458b-d682-4268-ace8-cf25aa128d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006602850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4006602850
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2788453005
Short name T14
Test name
Test status
Simulation time 11999380350 ps
CPU time 26.39 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:09:19 PM PDT 24
Peak memory 210224 kb
Host smart-2cbce332-8beb-4514-80c2-794ae2913296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788453005 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2788453005
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.926063038
Short name T513
Test name
Test status
Simulation time 302175673 ps
CPU time 1.36 seconds
Started Aug 12 06:12:02 PM PDT 24
Finished Aug 12 06:12:03 PM PDT 24
Peak memory 201448 kb
Host smart-b7ed0f6e-c2e9-478e-a249-0b640b5bcd70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926063038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.926063038
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1830547354
Short name T227
Test name
Test status
Simulation time 542188929116 ps
CPU time 312.71 seconds
Started Aug 12 06:12:00 PM PDT 24
Finished Aug 12 06:17:13 PM PDT 24
Peak memory 201656 kb
Host smart-3e436685-a36b-41c3-9ea6-d6843b857f98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830547354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1830547354
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2760207
Short name T504
Test name
Test status
Simulation time 172060263165 ps
CPU time 108.18 seconds
Started Aug 12 06:11:56 PM PDT 24
Finished Aug 12 06:13:45 PM PDT 24
Peak memory 201660 kb
Host smart-d22c382e-eef7-4e5e-9a65-f9f8ffdbfc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2760207
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.750579006
Short name T540
Test name
Test status
Simulation time 162366766774 ps
CPU time 102.43 seconds
Started Aug 12 06:11:57 PM PDT 24
Finished Aug 12 06:13:39 PM PDT 24
Peak memory 201656 kb
Host smart-32af63af-a8af-4bde-bc18-738b41ca0d5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=750579006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.750579006
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.381362397
Short name T144
Test name
Test status
Simulation time 499338020794 ps
CPU time 1136.1 seconds
Started Aug 12 06:11:52 PM PDT 24
Finished Aug 12 06:30:48 PM PDT 24
Peak memory 201668 kb
Host smart-94416c1f-0cce-4d09-8211-766004381373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381362397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.381362397
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3687978156
Short name T486
Test name
Test status
Simulation time 491442923544 ps
CPU time 550.88 seconds
Started Aug 12 06:11:53 PM PDT 24
Finished Aug 12 06:21:04 PM PDT 24
Peak memory 201612 kb
Host smart-a1be367a-3003-49f7-9bca-65d2ca29a802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687978156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3687978156
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.208071462
Short name T310
Test name
Test status
Simulation time 166072817008 ps
CPU time 178.74 seconds
Started Aug 12 06:11:58 PM PDT 24
Finished Aug 12 06:14:57 PM PDT 24
Peak memory 201640 kb
Host smart-bfb3acb2-fba9-41a3-9577-4fd33071c1b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208071462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.208071462
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.923020877
Short name T530
Test name
Test status
Simulation time 394970276945 ps
CPU time 903.52 seconds
Started Aug 12 06:11:58 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 201724 kb
Host smart-ebabe265-dd4b-4bfb-9959-78e29b47ce35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923020877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.923020877
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4254338598
Short name T659
Test name
Test status
Simulation time 25938501086 ps
CPU time 3.91 seconds
Started Aug 12 06:12:00 PM PDT 24
Finished Aug 12 06:12:04 PM PDT 24
Peak memory 201620 kb
Host smart-d5d84daa-b289-4ef0-8819-aa85e96f1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254338598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4254338598
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2168037147
Short name T784
Test name
Test status
Simulation time 5087720527 ps
CPU time 6.64 seconds
Started Aug 12 06:11:58 PM PDT 24
Finished Aug 12 06:12:05 PM PDT 24
Peak memory 201488 kb
Host smart-fa2f966c-ac85-44c8-861a-86989e13dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168037147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2168037147
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3307637645
Short name T674
Test name
Test status
Simulation time 5662496892 ps
CPU time 13.21 seconds
Started Aug 12 06:11:50 PM PDT 24
Finished Aug 12 06:12:04 PM PDT 24
Peak memory 201508 kb
Host smart-6283b044-1bc3-4480-a268-4da16469f569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307637645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3307637645
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2812132000
Short name T573
Test name
Test status
Simulation time 42413191809 ps
CPU time 16.78 seconds
Started Aug 12 06:12:05 PM PDT 24
Finished Aug 12 06:12:22 PM PDT 24
Peak memory 209900 kb
Host smart-51ec09a9-9e6c-43d3-a325-67e6238a2752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812132000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2812132000
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.309472262
Short name T537
Test name
Test status
Simulation time 364484285 ps
CPU time 0.77 seconds
Started Aug 12 06:12:15 PM PDT 24
Finished Aug 12 06:12:15 PM PDT 24
Peak memory 201404 kb
Host smart-21ccf63f-ec64-4f3a-a244-5334cf10ca66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309472262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.309472262
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2977671716
Short name T289
Test name
Test status
Simulation time 343486477048 ps
CPU time 823.48 seconds
Started Aug 12 06:12:10 PM PDT 24
Finished Aug 12 06:25:53 PM PDT 24
Peak memory 201680 kb
Host smart-0197fd49-9113-4d95-b49d-f82154475823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977671716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2977671716
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1447373376
Short name T446
Test name
Test status
Simulation time 326708895485 ps
CPU time 362.69 seconds
Started Aug 12 06:12:03 PM PDT 24
Finished Aug 12 06:18:06 PM PDT 24
Peak memory 201604 kb
Host smart-20aff5c1-8dfa-4078-9d16-a5bdfb77534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447373376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1447373376
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.627548253
Short name T546
Test name
Test status
Simulation time 326825130831 ps
CPU time 203.16 seconds
Started Aug 12 06:12:01 PM PDT 24
Finished Aug 12 06:15:25 PM PDT 24
Peak memory 201656 kb
Host smart-da2594eb-c562-4ce7-929f-7bb08dedde4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=627548253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.627548253
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4036293064
Short name T6
Test name
Test status
Simulation time 492692637577 ps
CPU time 1091.84 seconds
Started Aug 12 06:12:01 PM PDT 24
Finished Aug 12 06:30:13 PM PDT 24
Peak memory 201720 kb
Host smart-66552338-a3ea-4983-8e66-2f81036e1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036293064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4036293064
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.4227831520
Short name T559
Test name
Test status
Simulation time 490227408071 ps
CPU time 508.3 seconds
Started Aug 12 06:12:05 PM PDT 24
Finished Aug 12 06:20:34 PM PDT 24
Peak memory 201696 kb
Host smart-f0db8600-eae1-4da9-aa11-42a0ac602fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227831520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.4227831520
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1424490318
Short name T716
Test name
Test status
Simulation time 171758160024 ps
CPU time 94.03 seconds
Started Aug 12 06:12:13 PM PDT 24
Finished Aug 12 06:13:47 PM PDT 24
Peak memory 201656 kb
Host smart-2f174762-9176-4f04-9379-45a921b5f2ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424490318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1424490318
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3138657440
Short name T700
Test name
Test status
Simulation time 385894537363 ps
CPU time 895.21 seconds
Started Aug 12 06:12:08 PM PDT 24
Finished Aug 12 06:27:03 PM PDT 24
Peak memory 201656 kb
Host smart-f9aad59f-ec8d-4311-b820-e61ddb965029
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138657440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3138657440
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1790835948
Short name T435
Test name
Test status
Simulation time 99788133522 ps
CPU time 529.91 seconds
Started Aug 12 06:12:11 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 201912 kb
Host smart-9ac7d361-0105-4647-bca6-70504969dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790835948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1790835948
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3768614214
Short name T532
Test name
Test status
Simulation time 33722959252 ps
CPU time 18.2 seconds
Started Aug 12 06:12:11 PM PDT 24
Finished Aug 12 06:12:29 PM PDT 24
Peak memory 201472 kb
Host smart-21d44cee-2e7d-4635-bd1b-12f28b7ed59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768614214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3768614214
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.136286526
Short name T47
Test name
Test status
Simulation time 4817138718 ps
CPU time 6.61 seconds
Started Aug 12 06:12:10 PM PDT 24
Finished Aug 12 06:12:17 PM PDT 24
Peak memory 201440 kb
Host smart-d911ed46-6460-4a0a-9474-77d6845cf22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136286526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.136286526
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1074587864
Short name T107
Test name
Test status
Simulation time 5984289962 ps
CPU time 3.56 seconds
Started Aug 12 06:12:01 PM PDT 24
Finished Aug 12 06:12:05 PM PDT 24
Peak memory 201444 kb
Host smart-da4ffb5a-04d8-41a3-bc06-ca7f0907d0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074587864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1074587864
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2434723364
Short name T223
Test name
Test status
Simulation time 336405708356 ps
CPU time 97.13 seconds
Started Aug 12 06:12:10 PM PDT 24
Finished Aug 12 06:13:47 PM PDT 24
Peak memory 201688 kb
Host smart-7b0b3ba6-5368-43f6-ad6c-65deae4ce1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434723364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2434723364
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2886474119
Short name T645
Test name
Test status
Simulation time 1164639789 ps
CPU time 3.41 seconds
Started Aug 12 06:12:13 PM PDT 24
Finished Aug 12 06:12:16 PM PDT 24
Peak memory 201532 kb
Host smart-6d7368f4-706d-47d3-858b-d36f24b68d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886474119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2886474119
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.754147549
Short name T701
Test name
Test status
Simulation time 530175568 ps
CPU time 1.73 seconds
Started Aug 12 06:12:16 PM PDT 24
Finished Aug 12 06:12:18 PM PDT 24
Peak memory 201460 kb
Host smart-e82e5dcf-bf25-4f3a-8e18-473566263e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754147549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.754147549
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4040405490
Short name T269
Test name
Test status
Simulation time 333707480446 ps
CPU time 48.84 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:13:03 PM PDT 24
Peak memory 201672 kb
Host smart-a3e6a2d9-338e-4715-b987-319467bffe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040405490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4040405490
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.492551428
Short name T135
Test name
Test status
Simulation time 166223894688 ps
CPU time 387.43 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:18:41 PM PDT 24
Peak memory 201600 kb
Host smart-f98a8460-9e47-464e-8348-298fa4dab6cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=492551428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.492551428
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2299679574
Short name T176
Test name
Test status
Simulation time 336666016110 ps
CPU time 78.05 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:13:32 PM PDT 24
Peak memory 201620 kb
Host smart-2ff69884-57c4-4650-8dc6-c90c5f86995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299679574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2299679574
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4093085904
Short name T733
Test name
Test status
Simulation time 338770947826 ps
CPU time 752.23 seconds
Started Aug 12 06:12:16 PM PDT 24
Finished Aug 12 06:24:48 PM PDT 24
Peak memory 201680 kb
Host smart-f0cfc058-1b28-43c7-bf37-6c66d2f0b93b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093085904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4093085904
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2050971511
Short name T763
Test name
Test status
Simulation time 599305524829 ps
CPU time 339.61 seconds
Started Aug 12 06:12:17 PM PDT 24
Finished Aug 12 06:17:57 PM PDT 24
Peak memory 201660 kb
Host smart-57ded929-9020-4826-b297-4b46945f17cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050971511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2050971511
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1346638369
Short name T670
Test name
Test status
Simulation time 112061338477 ps
CPU time 599.53 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 201924 kb
Host smart-f46f6e14-541e-4486-b88c-89a4ba234987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346638369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1346638369
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.4201299344
Short name T407
Test name
Test status
Simulation time 39758513391 ps
CPU time 23.13 seconds
Started Aug 12 06:12:16 PM PDT 24
Finished Aug 12 06:12:39 PM PDT 24
Peak memory 201472 kb
Host smart-e4e8d384-5167-4460-bd7c-952dbcd8334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201299344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.4201299344
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3997585544
Short name T134
Test name
Test status
Simulation time 4215657444 ps
CPU time 9.37 seconds
Started Aug 12 06:12:15 PM PDT 24
Finished Aug 12 06:12:25 PM PDT 24
Peak memory 201500 kb
Host smart-8e93b2fb-2752-4f3f-a25f-b56ecb8e0251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997585544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3997585544
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3111836397
Short name T525
Test name
Test status
Simulation time 5763994222 ps
CPU time 7.43 seconds
Started Aug 12 06:12:14 PM PDT 24
Finished Aug 12 06:12:22 PM PDT 24
Peak memory 201508 kb
Host smart-84fad462-6ef4-4f09-b742-e506bf68a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111836397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3111836397
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3851054966
Short name T337
Test name
Test status
Simulation time 1264678387817 ps
CPU time 1074.99 seconds
Started Aug 12 06:12:15 PM PDT 24
Finished Aug 12 06:30:10 PM PDT 24
Peak memory 210104 kb
Host smart-b7066865-7865-4b81-a73d-96f2508c7cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851054966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3851054966
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.428602902
Short name T695
Test name
Test status
Simulation time 305072112 ps
CPU time 0.8 seconds
Started Aug 12 06:12:26 PM PDT 24
Finished Aug 12 06:12:27 PM PDT 24
Peak memory 201464 kb
Host smart-20943fd4-00cd-4c6f-b69f-5b32f3270654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428602902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.428602902
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3739424711
Short name T683
Test name
Test status
Simulation time 167613521083 ps
CPU time 174.85 seconds
Started Aug 12 06:12:22 PM PDT 24
Finished Aug 12 06:15:17 PM PDT 24
Peak memory 201672 kb
Host smart-b7dc7160-cf63-4908-9600-5370855b0b61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739424711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3739424711
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3625368666
Short name T311
Test name
Test status
Simulation time 490070809317 ps
CPU time 1067.32 seconds
Started Aug 12 06:12:21 PM PDT 24
Finished Aug 12 06:30:08 PM PDT 24
Peak memory 201660 kb
Host smart-1979d3de-99f0-4d58-8d02-ecc69382ae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625368666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3625368666
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2939388514
Short name T231
Test name
Test status
Simulation time 168177086312 ps
CPU time 180.55 seconds
Started Aug 12 06:12:22 PM PDT 24
Finished Aug 12 06:15:23 PM PDT 24
Peak memory 201612 kb
Host smart-2cb71c8f-54ef-44f5-a4d0-fddc2d61e9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939388514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2939388514
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3798829575
Short name T555
Test name
Test status
Simulation time 495514648125 ps
CPU time 1126.35 seconds
Started Aug 12 06:12:21 PM PDT 24
Finished Aug 12 06:31:08 PM PDT 24
Peak memory 201632 kb
Host smart-607891cb-8580-451e-87f6-b9e3819bccf0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798829575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3798829575
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1959246228
Short name T677
Test name
Test status
Simulation time 495858789094 ps
CPU time 1173.98 seconds
Started Aug 12 06:12:20 PM PDT 24
Finished Aug 12 06:31:54 PM PDT 24
Peak memory 201672 kb
Host smart-636dd70f-e025-40ef-a2b5-4b8dbf3a60e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959246228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1959246228
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2401899755
Short name T315
Test name
Test status
Simulation time 169367896895 ps
CPU time 98.3 seconds
Started Aug 12 06:12:19 PM PDT 24
Finished Aug 12 06:13:58 PM PDT 24
Peak memory 201656 kb
Host smart-c5c4fb24-d8ba-4520-a2e0-89b04cd9339f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401899755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2401899755
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1512186704
Short name T381
Test name
Test status
Simulation time 406811806354 ps
CPU time 214.91 seconds
Started Aug 12 06:12:22 PM PDT 24
Finished Aug 12 06:15:57 PM PDT 24
Peak memory 201648 kb
Host smart-9ba1eb9d-4fa5-4be6-ba68-1855307e6433
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512186704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1512186704
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1665461590
Short name T209
Test name
Test status
Simulation time 103773238593 ps
CPU time 386.92 seconds
Started Aug 12 06:12:22 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 201884 kb
Host smart-13de9023-6c72-4121-aa46-566985cc8e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665461590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1665461590
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.435212320
Short name T719
Test name
Test status
Simulation time 41616422478 ps
CPU time 42.28 seconds
Started Aug 12 06:12:20 PM PDT 24
Finished Aug 12 06:13:02 PM PDT 24
Peak memory 201488 kb
Host smart-c08234c4-6a68-4b43-bb95-799445eb9ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435212320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.435212320
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.639984638
Short name T769
Test name
Test status
Simulation time 4289668802 ps
CPU time 9.92 seconds
Started Aug 12 06:12:19 PM PDT 24
Finished Aug 12 06:12:29 PM PDT 24
Peak memory 201372 kb
Host smart-ab866656-9e59-4221-b090-fba04549f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639984638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.639984638
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1969786301
Short name T578
Test name
Test status
Simulation time 6089161699 ps
CPU time 8.02 seconds
Started Aug 12 06:12:17 PM PDT 24
Finished Aug 12 06:12:25 PM PDT 24
Peak memory 201448 kb
Host smart-ac9bf498-8b9a-4ccc-b36a-7093805cbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969786301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1969786301
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2027614752
Short name T510
Test name
Test status
Simulation time 30255380045 ps
CPU time 19.68 seconds
Started Aug 12 06:12:21 PM PDT 24
Finished Aug 12 06:12:41 PM PDT 24
Peak memory 201516 kb
Host smart-6fddf781-bf80-412c-929e-f9cc1f06c07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027614752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2027614752
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3207444423
Short name T584
Test name
Test status
Simulation time 13928788070 ps
CPU time 17.18 seconds
Started Aug 12 06:12:23 PM PDT 24
Finished Aug 12 06:12:40 PM PDT 24
Peak memory 210224 kb
Host smart-4bf7f9bf-7968-456d-a3e6-649fe2c76bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207444423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3207444423
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2957684975
Short name T371
Test name
Test status
Simulation time 600811806 ps
CPU time 0.73 seconds
Started Aug 12 06:12:35 PM PDT 24
Finished Aug 12 06:12:36 PM PDT 24
Peak memory 201456 kb
Host smart-17418b7a-c665-42e4-93a1-96116df9cc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957684975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2957684975
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.945835670
Short name T795
Test name
Test status
Simulation time 179272823292 ps
CPU time 212.48 seconds
Started Aug 12 06:12:34 PM PDT 24
Finished Aug 12 06:16:07 PM PDT 24
Peak memory 201728 kb
Host smart-8d5cb010-4464-4f87-9280-b4495b3df5a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945835670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.945835670
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3526725339
Short name T245
Test name
Test status
Simulation time 370436635916 ps
CPU time 540.94 seconds
Started Aug 12 06:12:36 PM PDT 24
Finished Aug 12 06:21:37 PM PDT 24
Peak memory 201668 kb
Host smart-7b799eb7-d6ef-4640-ba26-ec1971ef35cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526725339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3526725339
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3783477208
Short name T678
Test name
Test status
Simulation time 163389565240 ps
CPU time 194.48 seconds
Started Aug 12 06:12:28 PM PDT 24
Finished Aug 12 06:15:43 PM PDT 24
Peak memory 201688 kb
Host smart-f5b55710-1324-4d06-a431-20bf71b2397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783477208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3783477208
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1495429164
Short name T383
Test name
Test status
Simulation time 328207184912 ps
CPU time 214.37 seconds
Started Aug 12 06:12:27 PM PDT 24
Finished Aug 12 06:16:02 PM PDT 24
Peak memory 201604 kb
Host smart-c3ee6aa2-4655-488c-8f7f-30dfca64db76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495429164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1495429164
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1939669597
Short name T324
Test name
Test status
Simulation time 324054453547 ps
CPU time 185.17 seconds
Started Aug 12 06:12:28 PM PDT 24
Finished Aug 12 06:15:33 PM PDT 24
Peak memory 201660 kb
Host smart-508b9228-8e5e-41e5-b040-e61b0bd8df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939669597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1939669597
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3520687410
Short name T539
Test name
Test status
Simulation time 324629257095 ps
CPU time 428.38 seconds
Started Aug 12 06:12:29 PM PDT 24
Finished Aug 12 06:19:38 PM PDT 24
Peak memory 201648 kb
Host smart-0760b23d-9169-4d55-8b42-1c8b73b45c53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520687410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3520687410
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2555752388
Short name T758
Test name
Test status
Simulation time 179594274709 ps
CPU time 192.98 seconds
Started Aug 12 06:12:28 PM PDT 24
Finished Aug 12 06:15:41 PM PDT 24
Peak memory 201656 kb
Host smart-ac377ed0-aaeb-4c29-b4d7-00299286ee9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555752388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2555752388
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.752114401
Short name T42
Test name
Test status
Simulation time 606501943939 ps
CPU time 639.28 seconds
Started Aug 12 06:12:29 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 201668 kb
Host smart-4f2135a7-2059-462a-a3c8-ecf1d672a068
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752114401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.752114401
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1309327960
Short name T50
Test name
Test status
Simulation time 84344541168 ps
CPU time 258.44 seconds
Started Aug 12 06:12:36 PM PDT 24
Finished Aug 12 06:16:55 PM PDT 24
Peak memory 201924 kb
Host smart-a24fb122-fad5-44f4-944f-5472d0dab4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309327960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1309327960
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.458398613
Short name T379
Test name
Test status
Simulation time 29528421597 ps
CPU time 9.79 seconds
Started Aug 12 06:12:34 PM PDT 24
Finished Aug 12 06:12:44 PM PDT 24
Peak memory 201480 kb
Host smart-0569f0e0-8410-4493-a926-dc4e95a95e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458398613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.458398613
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1133545027
Short name T509
Test name
Test status
Simulation time 3907829052 ps
CPU time 9.99 seconds
Started Aug 12 06:12:36 PM PDT 24
Finished Aug 12 06:12:46 PM PDT 24
Peak memory 201456 kb
Host smart-7ba0f704-4a2f-4202-90fa-4d4ece5927d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133545027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1133545027
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.348083352
Short name T481
Test name
Test status
Simulation time 5944766513 ps
CPU time 7.75 seconds
Started Aug 12 06:12:28 PM PDT 24
Finished Aug 12 06:12:36 PM PDT 24
Peak memory 201388 kb
Host smart-e3f25660-1587-459a-9127-27e21c352f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348083352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.348083352
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.109649180
Short name T732
Test name
Test status
Simulation time 332579888865 ps
CPU time 53.87 seconds
Started Aug 12 06:12:36 PM PDT 24
Finished Aug 12 06:13:30 PM PDT 24
Peak memory 201708 kb
Host smart-32c63bb6-7187-4945-bf87-71aef679dfe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109649180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
109649180
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.118574177
Short name T369
Test name
Test status
Simulation time 367741646 ps
CPU time 1.49 seconds
Started Aug 12 06:12:45 PM PDT 24
Finished Aug 12 06:12:47 PM PDT 24
Peak memory 201448 kb
Host smart-a1cfe659-d110-4f88-a0ed-d17d785dc440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118574177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.118574177
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.186726200
Short name T251
Test name
Test status
Simulation time 196049085789 ps
CPU time 135.15 seconds
Started Aug 12 06:12:45 PM PDT 24
Finished Aug 12 06:15:00 PM PDT 24
Peak memory 201716 kb
Host smart-10400c44-a213-439f-a69c-0a3e1f21a756
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186726200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.186726200
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.220146319
Short name T721
Test name
Test status
Simulation time 325461530675 ps
CPU time 750.26 seconds
Started Aug 12 06:12:35 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 201588 kb
Host smart-e2cd16d4-9ba1-453e-bba0-e8ac58a23dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220146319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.220146319
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1784060547
Short name T456
Test name
Test status
Simulation time 487468935786 ps
CPU time 183.58 seconds
Started Aug 12 06:12:42 PM PDT 24
Finished Aug 12 06:15:46 PM PDT 24
Peak memory 201640 kb
Host smart-a9057784-4942-48ca-b42d-b75306be17dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784060547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1784060547
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.109224517
Short name T777
Test name
Test status
Simulation time 159826727250 ps
CPU time 88.62 seconds
Started Aug 12 06:12:38 PM PDT 24
Finished Aug 12 06:14:07 PM PDT 24
Peak memory 201628 kb
Host smart-4d27baa5-364d-4fc1-9fb1-318bfd552d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109224517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.109224517
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2199967251
Short name T399
Test name
Test status
Simulation time 164962670829 ps
CPU time 372.18 seconds
Started Aug 12 06:12:35 PM PDT 24
Finished Aug 12 06:18:48 PM PDT 24
Peak memory 201644 kb
Host smart-f8ebabac-563d-499f-8b2d-effa8a3c4b86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199967251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2199967251
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.540699917
Short name T497
Test name
Test status
Simulation time 240321332427 ps
CPU time 587.86 seconds
Started Aug 12 06:12:42 PM PDT 24
Finished Aug 12 06:22:30 PM PDT 24
Peak memory 201624 kb
Host smart-e11b8558-9d56-4907-8e1b-1fa092e90c97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540699917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.540699917
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.519192454
Short name T725
Test name
Test status
Simulation time 608612305532 ps
CPU time 97.26 seconds
Started Aug 12 06:12:41 PM PDT 24
Finished Aug 12 06:14:18 PM PDT 24
Peak memory 201656 kb
Host smart-ff3eec58-e700-4aba-a673-3895e203f0c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519192454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.519192454
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3981450366
Short name T208
Test name
Test status
Simulation time 124910299824 ps
CPU time 477.29 seconds
Started Aug 12 06:12:44 PM PDT 24
Finished Aug 12 06:20:41 PM PDT 24
Peak memory 201960 kb
Host smart-02fa6d84-b3e2-4af1-8995-4c752ac3ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981450366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3981450366
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1112285892
Short name T576
Test name
Test status
Simulation time 22554810567 ps
CPU time 14.39 seconds
Started Aug 12 06:12:41 PM PDT 24
Finished Aug 12 06:12:56 PM PDT 24
Peak memory 201476 kb
Host smart-c1f50e22-fb9d-4b97-aa34-dd42c8bfa1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112285892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1112285892
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.592730264
Short name T663
Test name
Test status
Simulation time 3528110655 ps
CPU time 9.03 seconds
Started Aug 12 06:12:43 PM PDT 24
Finished Aug 12 06:12:52 PM PDT 24
Peak memory 201504 kb
Host smart-00253134-0a30-4f13-846d-7b5c6a29e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592730264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.592730264
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.550460753
Short name T528
Test name
Test status
Simulation time 5685448276 ps
CPU time 13.36 seconds
Started Aug 12 06:12:33 PM PDT 24
Finished Aug 12 06:12:47 PM PDT 24
Peak memory 201508 kb
Host smart-6019eddd-817a-4b9c-84fa-71b1bbb02524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550460753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.550460753
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3418125784
Short name T304
Test name
Test status
Simulation time 627300211911 ps
CPU time 1084.62 seconds
Started Aug 12 06:12:44 PM PDT 24
Finished Aug 12 06:30:49 PM PDT 24
Peak memory 201880 kb
Host smart-07a41113-7a2f-44e6-94aa-bd60473f37d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418125784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3418125784
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3113548828
Short name T640
Test name
Test status
Simulation time 37762993036 ps
CPU time 11 seconds
Started Aug 12 06:12:42 PM PDT 24
Finished Aug 12 06:12:53 PM PDT 24
Peak memory 209788 kb
Host smart-9ed3d10f-41aa-40be-ad29-888702c7d6f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113548828 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3113548828
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1006554939
Short name T451
Test name
Test status
Simulation time 465103452 ps
CPU time 1.11 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:12:51 PM PDT 24
Peak memory 201448 kb
Host smart-17d4c54a-c5ca-478e-90fe-4bee5de69832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006554939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1006554939
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3185403847
Short name T189
Test name
Test status
Simulation time 507895594106 ps
CPU time 230.56 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:16:40 PM PDT 24
Peak memory 201732 kb
Host smart-389707e3-f8d6-45bc-ae27-0f21cf0ee06d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185403847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3185403847
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.598278052
Short name T690
Test name
Test status
Simulation time 333742905803 ps
CPU time 680.87 seconds
Started Aug 12 06:12:48 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 201628 kb
Host smart-8ee864bb-ad3a-4d35-a781-23e19d1c62b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598278052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.598278052
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.97141800
Short name T166
Test name
Test status
Simulation time 499472110600 ps
CPU time 1227.84 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:33:17 PM PDT 24
Peak memory 201716 kb
Host smart-de92d1aa-6235-49c1-bfec-593f958ca4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97141800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.97141800
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4243383754
Short name T428
Test name
Test status
Simulation time 167772881016 ps
CPU time 403.71 seconds
Started Aug 12 06:12:48 PM PDT 24
Finished Aug 12 06:19:32 PM PDT 24
Peak memory 201696 kb
Host smart-64c27b48-4c61-4e73-a79c-d01ee9c26824
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243383754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4243383754
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1927107314
Short name T672
Test name
Test status
Simulation time 327136291976 ps
CPU time 198.47 seconds
Started Aug 12 06:12:48 PM PDT 24
Finished Aug 12 06:16:07 PM PDT 24
Peak memory 201660 kb
Host smart-0f8540dd-264c-4f17-8066-f07b71189e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927107314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1927107314
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2343875071
Short name T605
Test name
Test status
Simulation time 159071798539 ps
CPU time 358.67 seconds
Started Aug 12 06:12:51 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 201692 kb
Host smart-2ce7c492-4e7e-400f-9113-5a9ad5c2b3b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343875071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2343875071
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.313403377
Short name T624
Test name
Test status
Simulation time 207455712545 ps
CPU time 452.67 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:20:22 PM PDT 24
Peak memory 201636 kb
Host smart-c5e93415-5f16-45a3-9a48-8b836dc40fd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313403377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.313403377
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1136543779
Short name T549
Test name
Test status
Simulation time 197971025916 ps
CPU time 222.59 seconds
Started Aug 12 06:12:51 PM PDT 24
Finished Aug 12 06:16:33 PM PDT 24
Peak memory 201648 kb
Host smart-6685e5d5-4e03-446d-baee-4db57a5980ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136543779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1136543779
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.332737854
Short name T503
Test name
Test status
Simulation time 28321291898 ps
CPU time 16.6 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:13:06 PM PDT 24
Peak memory 201396 kb
Host smart-2daea983-1e1f-4fc9-a6d7-5cb819a9bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332737854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.332737854
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2620297911
Short name T384
Test name
Test status
Simulation time 3448108932 ps
CPU time 8.39 seconds
Started Aug 12 06:12:48 PM PDT 24
Finished Aug 12 06:12:56 PM PDT 24
Peak memory 201480 kb
Host smart-29838d1d-1c50-4023-97fc-a481e6fc7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620297911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2620297911
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3221046417
Short name T561
Test name
Test status
Simulation time 5990342996 ps
CPU time 14.39 seconds
Started Aug 12 06:12:45 PM PDT 24
Finished Aug 12 06:13:00 PM PDT 24
Peak memory 201476 kb
Host smart-9a91af9a-d73a-436f-8dc2-bcb0b7dc5d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221046417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3221046417
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.334002709
Short name T616
Test name
Test status
Simulation time 368443920784 ps
CPU time 699.71 seconds
Started Aug 12 06:12:49 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 201624 kb
Host smart-2d414609-0aee-45f7-a6f4-4e4832fffc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334002709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
334002709
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3071641214
Short name T773
Test name
Test status
Simulation time 300508931 ps
CPU time 0.8 seconds
Started Aug 12 06:13:00 PM PDT 24
Finished Aug 12 06:13:01 PM PDT 24
Peak memory 201404 kb
Host smart-176f71e2-6d78-4ba0-8a98-8c1fe1e81d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071641214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3071641214
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1504713083
Short name T740
Test name
Test status
Simulation time 175165846726 ps
CPU time 397.7 seconds
Started Aug 12 06:12:55 PM PDT 24
Finished Aug 12 06:19:33 PM PDT 24
Peak memory 201732 kb
Host smart-2212f4b1-12a6-4c02-89fa-ccb708934827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504713083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1504713083
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.16115603
Short name T186
Test name
Test status
Simulation time 331728107030 ps
CPU time 53.34 seconds
Started Aug 12 06:12:47 PM PDT 24
Finished Aug 12 06:13:41 PM PDT 24
Peak memory 201716 kb
Host smart-5d964a62-5001-4e6a-9410-a7ecc71939fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16115603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.16115603
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3794298123
Short name T395
Test name
Test status
Simulation time 505459066253 ps
CPU time 1116.18 seconds
Started Aug 12 06:12:55 PM PDT 24
Finished Aug 12 06:31:31 PM PDT 24
Peak memory 201748 kb
Host smart-17916e64-3847-4fcf-a62c-a5cd511da416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794298123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3794298123
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1327764422
Short name T238
Test name
Test status
Simulation time 500249407262 ps
CPU time 1156.99 seconds
Started Aug 12 06:12:48 PM PDT 24
Finished Aug 12 06:32:06 PM PDT 24
Peak memory 201660 kb
Host smart-45306482-60ed-48c8-b45b-07b078d0afa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327764422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1327764422
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1056603199
Short name T583
Test name
Test status
Simulation time 164549904299 ps
CPU time 360.09 seconds
Started Aug 12 06:12:47 PM PDT 24
Finished Aug 12 06:18:48 PM PDT 24
Peak memory 201680 kb
Host smart-7b5e70d0-3a97-42bb-aae5-aa120d44e3c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056603199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1056603199
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.210941449
Short name T679
Test name
Test status
Simulation time 194720548988 ps
CPU time 451.07 seconds
Started Aug 12 06:12:56 PM PDT 24
Finished Aug 12 06:20:27 PM PDT 24
Peak memory 201696 kb
Host smart-9a817cf7-02dd-41f7-9fba-b0c05f50ee11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210941449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.210941449
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.453105742
Short name T469
Test name
Test status
Simulation time 77334122080 ps
CPU time 429.85 seconds
Started Aug 12 06:12:54 PM PDT 24
Finished Aug 12 06:20:04 PM PDT 24
Peak memory 201908 kb
Host smart-7c93a460-d487-4e41-b7bb-6a57560a0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453105742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.453105742
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3674334083
Short name T422
Test name
Test status
Simulation time 43922516714 ps
CPU time 46.94 seconds
Started Aug 12 06:12:58 PM PDT 24
Finished Aug 12 06:13:45 PM PDT 24
Peak memory 201484 kb
Host smart-8b0a6388-d7f3-4e5b-97ec-2e29ae124478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674334083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3674334083
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4218621675
Short name T377
Test name
Test status
Simulation time 5182085439 ps
CPU time 4.02 seconds
Started Aug 12 06:12:58 PM PDT 24
Finished Aug 12 06:13:02 PM PDT 24
Peak memory 201508 kb
Host smart-5cfcdae5-051b-43d5-95f6-ba9baddaf53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218621675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4218621675
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2394977842
Short name T490
Test name
Test status
Simulation time 6096911366 ps
CPU time 3.8 seconds
Started Aug 12 06:12:50 PM PDT 24
Finished Aug 12 06:12:54 PM PDT 24
Peak memory 201476 kb
Host smart-7efb4850-cf34-410a-839a-50e82a0add78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394977842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2394977842
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.394987420
Short name T153
Test name
Test status
Simulation time 199835796251 ps
CPU time 447.02 seconds
Started Aug 12 06:12:57 PM PDT 24
Finished Aug 12 06:20:24 PM PDT 24
Peak memory 201652 kb
Host smart-0576a3ec-8690-4874-b244-5ef1c02092c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394987420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
394987420
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.848997878
Short name T774
Test name
Test status
Simulation time 208209290193 ps
CPU time 10.37 seconds
Started Aug 12 06:12:56 PM PDT 24
Finished Aug 12 06:13:06 PM PDT 24
Peak memory 218080 kb
Host smart-0454dfea-e371-4887-9b99-850f04bf31bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848997878 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.848997878
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.908507652
Short name T520
Test name
Test status
Simulation time 279989260 ps
CPU time 1.3 seconds
Started Aug 12 06:13:01 PM PDT 24
Finished Aug 12 06:13:02 PM PDT 24
Peak memory 201448 kb
Host smart-9b01c167-923c-4602-aa0b-86a82a52d790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908507652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.908507652
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.171351966
Short name T475
Test name
Test status
Simulation time 162089551172 ps
CPU time 373.59 seconds
Started Aug 12 06:13:01 PM PDT 24
Finished Aug 12 06:19:15 PM PDT 24
Peak memory 201548 kb
Host smart-e32249f4-d108-4f1b-b312-7274c9d902e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171351966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.171351966
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2511337756
Short name T272
Test name
Test status
Simulation time 375952426190 ps
CPU time 190.47 seconds
Started Aug 12 06:13:01 PM PDT 24
Finished Aug 12 06:16:11 PM PDT 24
Peak memory 201636 kb
Host smart-c2657440-791d-465f-a80f-5abdce4add13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511337756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2511337756
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1234023744
Short name T563
Test name
Test status
Simulation time 161705645158 ps
CPU time 364.8 seconds
Started Aug 12 06:12:58 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 201668 kb
Host smart-c37ed0e3-4efb-4dc2-a50e-0031cff23e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234023744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1234023744
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3845670966
Short name T664
Test name
Test status
Simulation time 483361417737 ps
CPU time 778.34 seconds
Started Aug 12 06:13:02 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 201648 kb
Host smart-d2d5c4c2-8150-484d-8bc3-a062276d2f8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845670966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3845670966
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2248261477
Short name T140
Test name
Test status
Simulation time 160783346444 ps
CPU time 99.62 seconds
Started Aug 12 06:12:54 PM PDT 24
Finished Aug 12 06:14:33 PM PDT 24
Peak memory 201632 kb
Host smart-f618da4c-004c-44da-b675-6bbbc1049157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248261477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2248261477
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3328653312
Short name T483
Test name
Test status
Simulation time 163885542777 ps
CPU time 110.22 seconds
Started Aug 12 06:13:00 PM PDT 24
Finished Aug 12 06:14:51 PM PDT 24
Peak memory 201616 kb
Host smart-9a513228-7213-46b6-b433-2c0313a6803b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328653312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3328653312
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.872869042
Short name T259
Test name
Test status
Simulation time 351917917363 ps
CPU time 216.98 seconds
Started Aug 12 06:13:05 PM PDT 24
Finished Aug 12 06:16:42 PM PDT 24
Peak memory 201728 kb
Host smart-8cd6f502-78d4-4388-b1a8-b152cc814c75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872869042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.872869042
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3720662185
Short name T658
Test name
Test status
Simulation time 194877785059 ps
CPU time 215.76 seconds
Started Aug 12 06:13:02 PM PDT 24
Finished Aug 12 06:16:38 PM PDT 24
Peak memory 201644 kb
Host smart-78efe11d-3411-4c8e-bf64-4088294649e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720662185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3720662185
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2728367557
Short name T215
Test name
Test status
Simulation time 74574659781 ps
CPU time 329.06 seconds
Started Aug 12 06:13:03 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 201960 kb
Host smart-3f9f0403-5495-4326-b809-a60b0c7baad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728367557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2728367557
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3987677553
Short name T628
Test name
Test status
Simulation time 25965645495 ps
CPU time 54.57 seconds
Started Aug 12 06:13:02 PM PDT 24
Finished Aug 12 06:13:56 PM PDT 24
Peak memory 201488 kb
Host smart-e68db803-e7df-41a0-8db9-4def651c01c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987677553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3987677553
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2383302355
Short name T95
Test name
Test status
Simulation time 4999715414 ps
CPU time 3.61 seconds
Started Aug 12 06:13:00 PM PDT 24
Finished Aug 12 06:13:04 PM PDT 24
Peak memory 201432 kb
Host smart-e78c50e6-912c-44b0-8527-1088636d0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383302355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2383302355
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3482801914
Short name T444
Test name
Test status
Simulation time 6067273266 ps
CPU time 15.46 seconds
Started Aug 12 06:13:00 PM PDT 24
Finished Aug 12 06:13:16 PM PDT 24
Peak memory 201436 kb
Host smart-cc79239f-696e-44e8-9fb0-db761a587659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482801914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3482801914
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.903653691
Short name T506
Test name
Test status
Simulation time 194100136734 ps
CPU time 100.34 seconds
Started Aug 12 06:13:02 PM PDT 24
Finished Aug 12 06:14:42 PM PDT 24
Peak memory 201684 kb
Host smart-950c9927-573a-4174-afe2-8ff4f45d29f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903653691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
903653691
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2961831146
Short name T34
Test name
Test status
Simulation time 1970561747 ps
CPU time 5.39 seconds
Started Aug 12 06:13:01 PM PDT 24
Finished Aug 12 06:13:07 PM PDT 24
Peak memory 201504 kb
Host smart-0cf55b4f-04fb-41e4-b3a0-194016b051d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961831146 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2961831146
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3895502219
Short name T40
Test name
Test status
Simulation time 349927424 ps
CPU time 0.82 seconds
Started Aug 12 06:13:09 PM PDT 24
Finished Aug 12 06:13:10 PM PDT 24
Peak memory 201352 kb
Host smart-1df5a8e6-5dca-4c1e-8bf8-956b088bb58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895502219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3895502219
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1364364132
Short name T165
Test name
Test status
Simulation time 351444555577 ps
CPU time 6.09 seconds
Started Aug 12 06:13:09 PM PDT 24
Finished Aug 12 06:13:15 PM PDT 24
Peak memory 201660 kb
Host smart-1fd44a29-87a8-4949-ac92-59088a64f298
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364364132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1364364132
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1350236661
Short name T330
Test name
Test status
Simulation time 486738103510 ps
CPU time 110.89 seconds
Started Aug 12 06:13:12 PM PDT 24
Finished Aug 12 06:15:03 PM PDT 24
Peak memory 200320 kb
Host smart-483aaf95-5ca9-4f3b-ae51-93de9926a46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350236661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1350236661
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3698781468
Short name T666
Test name
Test status
Simulation time 322039983733 ps
CPU time 199.77 seconds
Started Aug 12 06:13:12 PM PDT 24
Finished Aug 12 06:16:32 PM PDT 24
Peak memory 200360 kb
Host smart-308eef08-3f39-4e7a-b70c-fbd7451910a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698781468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3698781468
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3431618048
Short name T328
Test name
Test status
Simulation time 328097358283 ps
CPU time 715.18 seconds
Started Aug 12 06:13:10 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 201688 kb
Host smart-e7888304-cd7b-49d6-ba86-aec0edfc4e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431618048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3431618048
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2465396833
Short name T602
Test name
Test status
Simulation time 161722639834 ps
CPU time 358.79 seconds
Started Aug 12 06:13:11 PM PDT 24
Finished Aug 12 06:19:10 PM PDT 24
Peak memory 201636 kb
Host smart-ed053f20-78fc-4761-a5f8-765665bc4266
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465396833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2465396833
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3802662087
Short name T553
Test name
Test status
Simulation time 612963742882 ps
CPU time 372.27 seconds
Started Aug 12 06:13:11 PM PDT 24
Finished Aug 12 06:19:23 PM PDT 24
Peak memory 201704 kb
Host smart-71c311ad-f06b-4278-b7c0-c5d992a89bbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802662087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3802662087
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2509285577
Short name T452
Test name
Test status
Simulation time 99361591459 ps
CPU time 617.65 seconds
Started Aug 12 06:13:10 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 201956 kb
Host smart-78a20512-d68d-4643-a241-e32e119b78f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509285577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2509285577
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.811097421
Short name T403
Test name
Test status
Simulation time 33064067597 ps
CPU time 19.74 seconds
Started Aug 12 06:13:08 PM PDT 24
Finished Aug 12 06:13:28 PM PDT 24
Peak memory 201492 kb
Host smart-d2fe6894-2c49-40fd-9238-9920b403e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811097421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.811097421
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1999921116
Short name T747
Test name
Test status
Simulation time 4692865408 ps
CPU time 6.35 seconds
Started Aug 12 06:13:09 PM PDT 24
Finished Aug 12 06:13:15 PM PDT 24
Peak memory 201428 kb
Host smart-f61aa2db-442b-4073-b04d-01dd9a6b32d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999921116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1999921116
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2364132163
Short name T365
Test name
Test status
Simulation time 6079212106 ps
CPU time 3.25 seconds
Started Aug 12 06:13:00 PM PDT 24
Finished Aug 12 06:13:03 PM PDT 24
Peak memory 201480 kb
Host smart-ca24be44-b08b-4e0f-99da-319ac0303225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364132163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2364132163
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4204730551
Short name T764
Test name
Test status
Simulation time 500857704097 ps
CPU time 696.99 seconds
Started Aug 12 06:13:10 PM PDT 24
Finished Aug 12 06:24:47 PM PDT 24
Peak memory 201696 kb
Host smart-33692358-20ca-4b65-b6b3-cabb6500d5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204730551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4204730551
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1864076113
Short name T560
Test name
Test status
Simulation time 15723170112 ps
CPU time 10.77 seconds
Started Aug 12 06:13:13 PM PDT 24
Finished Aug 12 06:13:24 PM PDT 24
Peak memory 218076 kb
Host smart-9b42ce93-9ba8-4a9e-9ac5-491743730f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864076113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1864076113
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.778946213
Short name T538
Test name
Test status
Simulation time 514627694 ps
CPU time 1.8 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:08:56 PM PDT 24
Peak memory 201440 kb
Host smart-79bf1a58-9353-40b2-b343-19c8af8f5db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778946213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.778946213
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.795208578
Short name T173
Test name
Test status
Simulation time 431868146180 ps
CPU time 55.38 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:09:47 PM PDT 24
Peak memory 201628 kb
Host smart-dc3327b7-e98b-4570-a369-e945e545b1fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795208578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.795208578
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.393025801
Short name T87
Test name
Test status
Simulation time 199041806763 ps
CPU time 119.87 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:10:53 PM PDT 24
Peak memory 201684 kb
Host smart-71d05117-e35a-4ba6-b2ff-a7095309f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393025801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.393025801
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3440060223
Short name T192
Test name
Test status
Simulation time 332617191488 ps
CPU time 203.02 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:12:18 PM PDT 24
Peak memory 201664 kb
Host smart-e0622bad-1e7a-4989-8459-15cd60cc7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440060223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3440060223
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2392990041
Short name T449
Test name
Test status
Simulation time 324357266771 ps
CPU time 730.98 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:21:05 PM PDT 24
Peak memory 201664 kb
Host smart-c264936a-c6d4-4cf2-8149-97e06e5b35b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392990041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2392990041
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1697580294
Short name T163
Test name
Test status
Simulation time 331939819029 ps
CPU time 207.3 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:12:23 PM PDT 24
Peak memory 201652 kb
Host smart-f4829a92-e76c-444e-8d8e-c778e3a41657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697580294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1697580294
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2744536202
Short name T607
Test name
Test status
Simulation time 495088929513 ps
CPU time 350.49 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:14:44 PM PDT 24
Peak memory 201648 kb
Host smart-c28b5750-39ae-4774-95a6-c04c35923c34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744536202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2744536202
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2693109825
Short name T197
Test name
Test status
Simulation time 211510448281 ps
CPU time 211.22 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:12:33 PM PDT 24
Peak memory 201728 kb
Host smart-fb7c94b6-5020-46be-92a2-7b9740b626f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693109825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2693109825
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3897486935
Short name T450
Test name
Test status
Simulation time 390195844592 ps
CPU time 879.86 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 201680 kb
Host smart-34f8a9c8-899b-4bc4-ae27-d5ee5db19a96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897486935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3897486935
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1727674602
Short name T48
Test name
Test status
Simulation time 131398325235 ps
CPU time 435.83 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:16:13 PM PDT 24
Peak memory 201972 kb
Host smart-c03360d5-4030-4f37-bfcd-b84c015593fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727674602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1727674602
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.46236180
Short name T772
Test name
Test status
Simulation time 39216312034 ps
CPU time 73.94 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:10:09 PM PDT 24
Peak memory 200136 kb
Host smart-a81a7e26-9bff-4a84-bc18-581bb873b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46236180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.46236180
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1793352018
Short name T712
Test name
Test status
Simulation time 3653000320 ps
CPU time 9.42 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:09:06 PM PDT 24
Peak memory 201432 kb
Host smart-751345f7-9a3a-4812-95a3-9073e41148c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793352018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1793352018
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2839614455
Short name T104
Test name
Test status
Simulation time 5823672600 ps
CPU time 4.24 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:09:01 PM PDT 24
Peak memory 201520 kb
Host smart-67999549-31e3-4ce5-a5d0-84e620ca12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839614455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2839614455
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3436128090
Short name T696
Test name
Test status
Simulation time 6589329547 ps
CPU time 12.43 seconds
Started Aug 12 06:08:52 PM PDT 24
Finished Aug 12 06:09:05 PM PDT 24
Peak memory 201516 kb
Host smart-ef6b78c5-c22b-4fd0-9fa4-4d7baffae992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436128090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3436128090
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1614324003
Short name T60
Test name
Test status
Simulation time 6813550139 ps
CPU time 14.78 seconds
Started Aug 12 06:08:53 PM PDT 24
Finished Aug 12 06:09:08 PM PDT 24
Peak memory 210228 kb
Host smart-77880bab-80e8-4f22-ab9c-fa5deac99608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614324003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1614324003
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1854921972
Short name T665
Test name
Test status
Simulation time 318352642 ps
CPU time 0.8 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:09:08 PM PDT 24
Peak memory 201448 kb
Host smart-b63e2b14-20da-4305-9245-84ec7926c26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854921972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1854921972
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3403313571
Short name T317
Test name
Test status
Simulation time 360261430824 ps
CPU time 404.16 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:15:42 PM PDT 24
Peak memory 201712 kb
Host smart-e3b60846-d97a-46aa-8d18-17f92516a448
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403313571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3403313571
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2047270579
Short name T786
Test name
Test status
Simulation time 162988515803 ps
CPU time 104.83 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:10:42 PM PDT 24
Peak memory 201676 kb
Host smart-ef93d632-3d6d-4688-942c-1884fb26bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047270579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2047270579
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3160378615
Short name T522
Test name
Test status
Simulation time 168798635385 ps
CPU time 364.57 seconds
Started Aug 12 06:09:00 PM PDT 24
Finished Aug 12 06:15:04 PM PDT 24
Peak memory 201660 kb
Host smart-8b4f7329-f69a-4d68-9fc7-6ad410c694f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160378615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3160378615
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3401740984
Short name T23
Test name
Test status
Simulation time 332478484914 ps
CPU time 829 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 201660 kb
Host smart-b6f5d303-5ac5-46d5-8dd2-e5ac6726d489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401740984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3401740984
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3350842596
Short name T306
Test name
Test status
Simulation time 494583925877 ps
CPU time 179.55 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:11:57 PM PDT 24
Peak memory 201668 kb
Host smart-43d20a7d-19b2-4cb3-af33-b7c61e910388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350842596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3350842596
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2446564660
Short name T433
Test name
Test status
Simulation time 490514761666 ps
CPU time 1085.01 seconds
Started Aug 12 06:08:57 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 201700 kb
Host smart-12b7f7de-6e7e-46fb-b3f5-48fa38a9e9c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446564660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2446564660
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1317046583
Short name T181
Test name
Test status
Simulation time 329298026483 ps
CPU time 189.87 seconds
Started Aug 12 06:08:54 PM PDT 24
Finished Aug 12 06:12:04 PM PDT 24
Peak memory 201660 kb
Host smart-624db00c-397f-4387-b86e-a88586fe034f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317046583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1317046583
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2866359398
Short name T401
Test name
Test status
Simulation time 597099868494 ps
CPU time 370.98 seconds
Started Aug 12 06:08:55 PM PDT 24
Finished Aug 12 06:15:06 PM PDT 24
Peak memory 201636 kb
Host smart-add50caf-02d4-48ec-9a18-590c500d339f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866359398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2866359398
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2494079719
Short name T524
Test name
Test status
Simulation time 67142195844 ps
CPU time 247.03 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:13:09 PM PDT 24
Peak memory 201984 kb
Host smart-cd253035-f8b5-46f6-9ff1-411b95b2a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494079719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2494079719
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3713453587
Short name T748
Test name
Test status
Simulation time 29510624585 ps
CPU time 37.3 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:09:39 PM PDT 24
Peak memory 201500 kb
Host smart-214105bb-dcf7-4f0c-bc88-cf2251510e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713453587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3713453587
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.831756205
Short name T571
Test name
Test status
Simulation time 5273810917 ps
CPU time 11.8 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:09:16 PM PDT 24
Peak memory 201480 kb
Host smart-6e7b1ec3-9735-4bf7-9f0f-b787a3e344b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831756205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.831756205
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1995928414
Short name T498
Test name
Test status
Simulation time 5975942225 ps
CPU time 4.61 seconds
Started Aug 12 06:08:56 PM PDT 24
Finished Aug 12 06:09:01 PM PDT 24
Peak memory 201436 kb
Host smart-a6346490-c074-4300-abd8-dbaa00e7f4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995928414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1995928414
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1383391422
Short name T445
Test name
Test status
Simulation time 10133678546 ps
CPU time 12.33 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:09:15 PM PDT 24
Peak memory 201504 kb
Host smart-8fb2b827-c057-4538-9f82-d454dcaf4c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383391422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1383391422
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2281083438
Short name T16
Test name
Test status
Simulation time 2948141637 ps
CPU time 8.07 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:09:11 PM PDT 24
Peak memory 209956 kb
Host smart-e3043f1f-8302-49b2-b9dc-088002ec9b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281083438 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2281083438
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4119908270
Short name T410
Test name
Test status
Simulation time 445520116 ps
CPU time 0.87 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:09:02 PM PDT 24
Peak memory 201388 kb
Host smart-8ab01135-4461-4ec5-a5c1-87fd3a8ae787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119908270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4119908270
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2270158401
Short name T604
Test name
Test status
Simulation time 170425256969 ps
CPU time 206.9 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:12:30 PM PDT 24
Peak memory 201612 kb
Host smart-e48e689c-0ba5-428f-9a26-9deb26b96381
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270158401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2270158401
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1247936750
Short name T175
Test name
Test status
Simulation time 169537282185 ps
CPU time 91.03 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:10:36 PM PDT 24
Peak memory 201716 kb
Host smart-8b1feb54-aa00-4f65-aeb6-547c8e747183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247936750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1247936750
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.559293643
Short name T424
Test name
Test status
Simulation time 163373675119 ps
CPU time 103.48 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:10:48 PM PDT 24
Peak memory 201652 kb
Host smart-b18537c7-184e-4a9e-b710-d1aca03abe2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=559293643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.559293643
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3977738978
Short name T331
Test name
Test status
Simulation time 481854777137 ps
CPU time 843.91 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 201584 kb
Host smart-b5d852e4-11f8-4ccf-88e9-9e058fde5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977738978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3977738978
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.151877783
Short name T662
Test name
Test status
Simulation time 165904104657 ps
CPU time 204.39 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:12:27 PM PDT 24
Peak memory 201624 kb
Host smart-eccc8621-d334-46e6-8a9d-1e6eb345cca6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151877783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.151877783
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1229686752
Short name T344
Test name
Test status
Simulation time 361929319134 ps
CPU time 184.82 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:12:08 PM PDT 24
Peak memory 201648 kb
Host smart-e4d5cef1-5e9c-4275-9b12-67b52fd9447d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229686752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1229686752
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2608067987
Short name T372
Test name
Test status
Simulation time 398081942256 ps
CPU time 223.74 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:12:47 PM PDT 24
Peak memory 201668 kb
Host smart-0a271bb1-6a5d-4ebf-878b-0afec5fa3953
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608067987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2608067987
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1055240842
Short name T350
Test name
Test status
Simulation time 126413960346 ps
CPU time 684.93 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:20:28 PM PDT 24
Peak memory 201932 kb
Host smart-763c7702-e326-4ac6-9418-2f7f83e03ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055240842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1055240842
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.372237519
Short name T526
Test name
Test status
Simulation time 45457580528 ps
CPU time 106.62 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:10:49 PM PDT 24
Peak memory 201456 kb
Host smart-3749be4d-09d6-45cb-9326-af6b81700e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372237519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.372237519
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.110853759
Short name T367
Test name
Test status
Simulation time 4713900709 ps
CPU time 3.29 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:09:06 PM PDT 24
Peak memory 201488 kb
Host smart-ddd57a84-e8ba-4cb7-bce8-43eb12f9bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110853759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.110853759
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.436620918
Short name T477
Test name
Test status
Simulation time 5997036204 ps
CPU time 15.15 seconds
Started Aug 12 06:09:04 PM PDT 24
Finished Aug 12 06:09:19 PM PDT 24
Peak memory 201500 kb
Host smart-82795a42-901a-4102-ba4b-1efcc87054c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436620918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.436620918
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3071417531
Short name T590
Test name
Test status
Simulation time 205566183588 ps
CPU time 133.81 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:11:16 PM PDT 24
Peak memory 201672 kb
Host smart-e349d17c-eca9-43a6-8948-36f527cfc488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071417531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3071417531
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2767244431
Short name T292
Test name
Test status
Simulation time 731851152112 ps
CPU time 64.85 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:10:08 PM PDT 24
Peak memory 210200 kb
Host smart-2401deda-a30c-4a31-ba4c-c218fc3d3169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767244431 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2767244431
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3639789532
Short name T388
Test name
Test status
Simulation time 479035202 ps
CPU time 1.87 seconds
Started Aug 12 06:09:09 PM PDT 24
Finished Aug 12 06:09:11 PM PDT 24
Peak memory 201452 kb
Host smart-d2acb580-7811-4e84-a31d-7ff99ec97e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639789532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3639789532
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.44971904
Short name T625
Test name
Test status
Simulation time 489762237544 ps
CPU time 264.01 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:13:26 PM PDT 24
Peak memory 201652 kb
Host smart-775dc052-fef9-471a-b55c-9a998de0602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44971904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.44971904
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1365902082
Short name T100
Test name
Test status
Simulation time 160245144092 ps
CPU time 106.03 seconds
Started Aug 12 06:09:05 PM PDT 24
Finished Aug 12 06:10:51 PM PDT 24
Peak memory 201680 kb
Host smart-21824590-7aef-4185-b16c-39e93fe20db3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365902082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1365902082
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1255521821
Short name T639
Test name
Test status
Simulation time 332266928428 ps
CPU time 762.14 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:21:43 PM PDT 24
Peak memory 201704 kb
Host smart-7e355fb2-5b98-4d63-84fa-370519e7aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255521821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1255521821
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1841606529
Short name T626
Test name
Test status
Simulation time 486952063034 ps
CPU time 1129.54 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 201592 kb
Host smart-4bd20e2f-eacd-444b-856f-9a410a017b6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841606529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1841606529
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.980878774
Short name T448
Test name
Test status
Simulation time 198738738292 ps
CPU time 160.07 seconds
Started Aug 12 06:09:01 PM PDT 24
Finished Aug 12 06:11:41 PM PDT 24
Peak memory 201692 kb
Host smart-a864e39d-7884-4000-9d38-2d4d48a56c7a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980878774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.980878774
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2020446117
Short name T569
Test name
Test status
Simulation time 98812795196 ps
CPU time 369.2 seconds
Started Aug 12 06:09:05 PM PDT 24
Finished Aug 12 06:15:14 PM PDT 24
Peak memory 201908 kb
Host smart-660a12c2-226f-4e9d-9fbc-a5da72f2c74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020446117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2020446117
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.628928199
Short name T461
Test name
Test status
Simulation time 26327504593 ps
CPU time 64.18 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:10:07 PM PDT 24
Peak memory 201480 kb
Host smart-f8c529b4-6731-460e-860f-fdc01da134b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628928199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.628928199
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4081605577
Short name T441
Test name
Test status
Simulation time 3201057960 ps
CPU time 4.71 seconds
Started Aug 12 06:09:02 PM PDT 24
Finished Aug 12 06:09:06 PM PDT 24
Peak memory 201476 kb
Host smart-96a3e799-45d6-4af7-9bb5-f841c56cbc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081605577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4081605577
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3298998367
Short name T405
Test name
Test status
Simulation time 5619596339 ps
CPU time 4.18 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:09:08 PM PDT 24
Peak memory 201480 kb
Host smart-1dce2b47-6e00-4c8a-a0c3-ff42a40853e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298998367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3298998367
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3184581239
Short name T356
Test name
Test status
Simulation time 117754573586 ps
CPU time 382.86 seconds
Started Aug 12 06:09:09 PM PDT 24
Finished Aug 12 06:15:32 PM PDT 24
Peak memory 218204 kb
Host smart-ddbc498f-5fd4-4649-bfa8-a5990e8724ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184581239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3184581239
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3589020478
Short name T613
Test name
Test status
Simulation time 13815920468 ps
CPU time 37.32 seconds
Started Aug 12 06:09:03 PM PDT 24
Finished Aug 12 06:09:41 PM PDT 24
Peak memory 210224 kb
Host smart-cd424fac-9e18-4656-80ac-a9a9c1e6d6d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589020478 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3589020478
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.952372871
Short name T596
Test name
Test status
Simulation time 433759793 ps
CPU time 1.73 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:09:09 PM PDT 24
Peak memory 201440 kb
Host smart-46903fc4-6fc6-46cc-825e-408c134594a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952372871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.952372871
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2878614855
Short name T756
Test name
Test status
Simulation time 339859028163 ps
CPU time 840.72 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 201720 kb
Host smart-a124ada5-da11-4acb-ab70-780ede799291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878614855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2878614855
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3741677344
Short name T580
Test name
Test status
Simulation time 164108571447 ps
CPU time 182.24 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:12:14 PM PDT 24
Peak memory 201620 kb
Host smart-a932dfc4-e679-438e-8b57-7753338b35a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741677344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3741677344
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2264430124
Short name T180
Test name
Test status
Simulation time 324198942440 ps
CPU time 149.89 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:11:38 PM PDT 24
Peak memory 201652 kb
Host smart-a4fcbb0c-ee27-4fa6-bb8c-92d95883d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264430124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2264430124
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1798836353
Short name T593
Test name
Test status
Simulation time 324320796670 ps
CPU time 186.29 seconds
Started Aug 12 06:09:08 PM PDT 24
Finished Aug 12 06:12:15 PM PDT 24
Peak memory 201652 kb
Host smart-13dd5aff-b312-4d63-bbc7-012cfbaa065f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798836353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1798836353
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.930849432
Short name T274
Test name
Test status
Simulation time 557005785414 ps
CPU time 594.19 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 201648 kb
Host smart-ffc93b9e-2988-45c9-a59b-9b9242eec761
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930849432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.930849432
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1481061327
Short name T479
Test name
Test status
Simulation time 406005696453 ps
CPU time 408.95 seconds
Started Aug 12 06:09:13 PM PDT 24
Finished Aug 12 06:16:02 PM PDT 24
Peak memory 201640 kb
Host smart-a114bc75-ccbc-4945-b951-042b123f3d6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481061327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1481061327
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4065664845
Short name T409
Test name
Test status
Simulation time 24967875734 ps
CPU time 56.86 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:10:08 PM PDT 24
Peak memory 201432 kb
Host smart-13c14db6-e96d-40ce-a1af-3861a18fc1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065664845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4065664845
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4111968067
Short name T417
Test name
Test status
Simulation time 4172273443 ps
CPU time 5.8 seconds
Started Aug 12 06:09:11 PM PDT 24
Finished Aug 12 06:09:17 PM PDT 24
Peak memory 201452 kb
Host smart-7db70936-7a5d-4b44-a351-49777cba3bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111968067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4111968067
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4154409248
Short name T542
Test name
Test status
Simulation time 5902769269 ps
CPU time 13.16 seconds
Started Aug 12 06:09:07 PM PDT 24
Finished Aug 12 06:09:21 PM PDT 24
Peak memory 201472 kb
Host smart-69f85754-71d1-4b1b-a9b2-ce2d1f59fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154409248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4154409248
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2045638350
Short name T343
Test name
Test status
Simulation time 323941598713 ps
CPU time 594.89 seconds
Started Aug 12 06:09:06 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 201696 kb
Host smart-682e711e-6f50-461a-8121-daa771379123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045638350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2045638350
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2666712877
Short name T198
Test name
Test status
Simulation time 12618221731 ps
CPU time 7.11 seconds
Started Aug 12 06:09:10 PM PDT 24
Finished Aug 12 06:09:17 PM PDT 24
Peak memory 209936 kb
Host smart-c318c023-8680-49cc-95ce-0b93a5a02a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666712877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2666712877
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%