Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5816	1			T6	20		T7	20		T9	11
testmodes[AdcCtrlTestmodeNormal]	4855	1			T1	2		T2	1		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5146	1			T1	2		T6	13		T8	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2975	1			T6	19		T7	19		T9	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1531	1			T11	1		T53	3		T18	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1206	1			T6	1		T34	21		T58	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1451	1			T9	1		T53	3		T30	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1761	1			T3	1		T5	1		T9	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1291	1			T1	2		T12	1		T52	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1272	1			T34	22		T42	1		T58	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1239	1			T1	1		T12	1		T54	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2393	1			T6	12		T8	9		T41	10