Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20590

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

2954

1

T1

2

T12

37

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18048

1

T1

5

T6

34

T7

20

auto[1]

5496

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	137	1			T56	21		T254	28		T210	24
values[1]	763	1			T12	22		T195	1		T54	15
values[2]	604	1			T1	2		T49	25		T55	35
values[3]	578	1			T16	13		T53	12		T54	24
values[4]	2851	1			T2	13		T3	2		T4	1
values[5]	459	1			T53	31		T189	20		T61	8
values[6]	568	1			T11	3		T36	1		T58	8
values[7]	708	1			T52	3		T255	11		T55	12
values[8]	843	1			T12	27		T53	3		T70	24
values[9]	1115	1			T16	14		T55	1		T56	18
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1010	1			T12	22		T195	1		T54	15
values[1]	655	1			T1	2		T49	25		T55	35
values[2]	517	1			T12	15		T16	13		T53	12
values[3]	2940	1			T2	13		T3	2		T4	1
values[4]	396	1			T150	1		T189	20		T256	1
values[5]	667	1			T11	3		T52	3		T29	31
values[6]	678	1			T255	11		T55	12		T192	39
values[7]	779	1			T12	27		T53	3		T55	1
values[8]	861	1			T16	14		T56	18		T28	14
values[9]	123	1			T147	2		T257	1		T159	18
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T56	12		T36	1		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	11		T195	1		T54	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	14		T55	16		T193	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T31	11		T179	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	1		T53	1		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	8		T31	8		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	11		T31	4		T143	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T256	1		T45	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T150	1		T189	11		T159	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	3		T52	3		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	16		T36	1		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	7		T58	11		T148	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T255	1		T192	20		T169	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	16		T55	1		T70	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T53	3		T70	15		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T28	1		T188	1		T191	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	1		T56	10		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T147	2		T257	1		T159	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T65	1		T258	3		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T222	2		T186	1		T146	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	11		T54	7		T56	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	11		T55	19		T193	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	1		T31	3		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	12		T53	11		T54	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T12	7		T31	9		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T2	12		T13	8		T15	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	12		T31	3		T60	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T102	5		T259	2		T164	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T189	9		T223	4		T101	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	2		T158	3		T96	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T29	15		T58	7		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T55	5		T58	12		T161	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T255	10		T192	19		T169	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	11		T70	11		T162	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T70	11		T192	11		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	13		T188	8		T191	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	13		T56	8		T163	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T111	3		T260	14		T261	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T258	3		T262	14		T263	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T210	13		T66	9		T264	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T56	17		T254	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T56	12		T36	1		T186	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	11		T195	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	14		T55	16		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T96	6		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	1		T53	1		T54	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T31	23		T33	8		T179	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T2	1		T3	2		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	8		T14	11		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T53	15		T61	8		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T189	11		T265	9		T158	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	3		T256	1		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T36	1		T58	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	3		T55	7		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T255	1		T70	15		T29	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	16		T70	13		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T53	3		T192	10		T163	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T55	1		T28	1		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T16	1		T56	10		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T210	11		T66	7		T266	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T56	4		T254	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T186	1		T102	9		T154	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	11		T54	7		T28	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	11		T55	19		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	1		T229	6		T267	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	12		T53	11		T54	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T31	15		T144	1		T60	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T2	12		T13	8		T15	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	7		T14	12		T113	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T53	16		T259	2		T268	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T189	9		T158	7		T101	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T158	3		T96	7		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T58	7		T158	10		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T55	5		T42	2		T58	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T255	10		T70	11		T29	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	11		T70	11		T162	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T192	20		T163	11		T269	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T28	13		T188	8		T191	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T16	13		T56	8		T163	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T56	1		T36	1		T222	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	12		T195	1		T54	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	12		T55	20		T193	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	2		T31	4		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	13		T53	12		T54	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	8		T31	10		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	13		T31	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T256	1		T45	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T150	1		T189	10		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	3		T52	1		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	16		T36	1		T58	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T55	6		T58	13		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T255	11		T192	21		T169	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	12		T55	1		T70	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	1		T70	12		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T28	14		T188	9		T191	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	14		T56	9		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T147	1		T257	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T65	1		T258	4		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T56	11		T186	14		T179	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	10		T54	7		T56	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	13		T55	15		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	10		T179	25		T59	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T54	11		T223	12		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	7		T31	7		T33	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T53	14		T57	10		T32	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	10		T31	3		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T102	4		T270	13		T268	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T189	10		T159	15		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T52	2		T42	2		T158	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	15		T271	11		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	6		T58	10		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T192	18		T122	10		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	15		T70	12		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T53	2		T70	14		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T191	9		T272	10		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T56	9		T149	13		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T147	1		T159	17		T260	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T258	2		T273	12		T263	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T210	12		T66	8		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T56	5		T254	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T56	1		T36	1		T186	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	12		T195	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	12		T55	20		T222	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	2		T96	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	13		T53	12		T54	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T31	18		T33	1		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	13		T3	2		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	8		T14	13		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T53	17		T61	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T189	10		T265	1		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	3		T256	1		T158	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T36	1		T58	8		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	1		T55	6		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T255	11		T70	12		T29	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	12		T70	12		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T53	1		T192	22		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T55	1		T28	14		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T16	14		T56	9		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T210	12		T66	8		T264	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T56	16		T254	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T56	11		T186	14		T179	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	10		T54	7		T265	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	13		T55	15		T146	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T96	5		T229	4		T267	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T54	11		T223	12		T111	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	20		T33	7		T179	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T57	10		T32	13		T35	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	7		T14	10		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T53	14		T61	7		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T189	10		T265	8		T158	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	7		T96	8		T102	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T158	8		T159	15		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	2		T55	6		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T70	14		T29	15		T192	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	15		T70	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	2		T192	8		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T191	9		T272	10		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T56	9		T149	13		T163	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20179

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3365

1

T16

13

T49

25

T52

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17590

1

T1

3

T6

34

T7

20

auto[1]

5954

1

T1

2

T2

13

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T104	7		-	-		-	-
values[0]	50	1			T274	18		T275	7		T276	25
values[1]	665	1			T12	27		T53	31		T192	33
values[2]	821	1			T11	3		T255	11		T28	15
values[3]	632	1			T55	1		T56	39		T143	13
values[4]	601	1			T54	39		T70	24		T31	14
values[5]	2911	1			T2	13		T3	2		T4	1
values[6]	690	1			T1	2		T49	25		T52	3
values[7]	548	1			T55	35		T56	12		T70	26
values[8]	505	1			T16	14		T53	12		T28	14
values[9]	1196	1			T14	23		T16	13		T195	1
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	855	1			T11	3		T12	27		T53	31
values[1]	756	1			T255	11		T56	21		T36	1
values[2]	655	1			T56	18		T70	24		T143	13
values[3]	2893	1			T2	13		T3	2		T4	1
values[4]	669	1			T1	2		T12	22		T49	25
values[5]	650	1			T52	3		T56	12		T33	8
values[6]	529	1			T55	35		T70	26		T192	18
values[7]	588	1			T16	14		T28	14		T162	8
values[8]	853	1			T14	23		T16	13		T53	12
values[9]	178	1			T188	9		T158	9		T277	1
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	3		T12	16		T31	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	15		T28	1		T58	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T36	1		T169	1		T271	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T255	1		T56	17		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T179	28		T146	13		T193	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T56	10		T70	13		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T60	10		T278	1		T61	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T12	11		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T49	14		T53	3		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T56	12		T149	14		T189	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	3		T33	8		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T192	9		T44	4		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T55	16		T70	15		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	1		T28	1		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T162	1		T169	1		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	11		T29	16		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T16	1		T53	1		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T158	2		T277	1		T279	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T188	1		T159	18		T280	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	11		T31	9		T192	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	16		T28	14		T58	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T169	9		T164	13		T281	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T255	10		T56	4		T282	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	4		T193	3		T101	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T56	8		T70	11		T193	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T2	12		T12	7		T13	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	12		T145	11		T283	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T12	11		T60	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	11		T31	3		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T189	9		T254	10		T284	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T163	8		T158	10		T285	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T192	9		T223	4		T258	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	19		T70	11		T58	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	13		T28	13		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T162	7		T169	14		T286	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	12		T29	15		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T16	12		T53	11		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T158	7		T287	3		T38	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T188	8		T280	4		T288	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T104	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T276	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T274	9		T275	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	16		T192	12		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	15		T58	11		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	3		T31	8		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T255	1		T28	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	1		T179	28		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	27		T143	13		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T54	20		T272	11		T160	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T70	13		T31	11		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T2	1		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	3		T278	1		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T149	14		T189	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	14		T52	3		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T56	12		T192	9		T265	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T55	16		T70	15		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T28	1		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T53	1		T58	1		T179	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T14	11		T29	16		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T16	1		T195	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T104	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T276	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T274	9		T275	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	11		T192	21		T191	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	16		T58	12		T188	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T31	9		T169	9		T146	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T255	10		T28	14		T193	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	1		T193	3		T101	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T56	12		T193	2		T282	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T54	19		T272	8		T95	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T70	11		T31	3		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T2	12		T12	18		T13	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	17		T269	11		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T189	9		T60	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T49	11		T169	12		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T192	9		T254	10		T258	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	19		T70	11		T163	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	13		T28	13		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T53	11		T58	7		T162	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	12		T29	15		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T16	12		T222	2		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1