Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20351

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3193

1

T11

3

T12

64

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17402

1

T1

2

T6

34

T7

20

auto[1]

6142

1

T1

3

T2

13

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	501	1			T1	3		T11	2		T70	24
values[0]	37	1			T341	1		T342	14		T197	13
values[1]	543	1			T16	14		T53	12		T29	31
values[2]	2887	1			T2	13		T3	2		T4	1
values[3]	541	1			T16	13		T255	11		T222	3
values[4]	654	1			T53	31		T55	1		T31	17
values[5]	754	1			T11	3		T12	22		T28	15
values[6]	594	1			T54	24		T56	39		T149	14
values[7]	652	1			T1	2		T53	3		T192	33
values[8]	801	1			T54	15		T70	26		T143	13
values[9]	953	1			T49	25		T195	1		T55	12
minimum	14627	1			T6	34		T7	20		T8	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	566	1			T55	35		T28	14		T29	31
values[1]	2831	1			T2	13		T3	2		T4	1
values[2]	569	1			T16	13		T53	31		T255	11
values[3]	727	1			T55	1		T33	8		T222	3
values[4]	659	1			T11	3		T12	22		T56	21
values[5]	627	1			T53	3		T54	24		T56	18
values[6]	626	1			T1	2		T70	26		T192	12
values[7]	905	1			T49	25		T54	15		T56	12
values[8]	728	1			T55	12		T36	1		T58	1
values[9]	160	1			T195	1		T70	24		T163	13
minimum	15146	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T55	16		T28	1		T61	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	16		T36	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	1		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	24		T14	11		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	1		T31	8		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T53	15		T255	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T55	1		T33	8		T59	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T222	1		T61	8		T147	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T56	17		T28	1		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	3		T12	11		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	3		T54	12		T192	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T56	10		T150	1		T254	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T70	15		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T58	11		T256	1		T271	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T56	12		T143	13		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T49	14		T54	8		T272	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	7		T36	1		T60	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T58	1		T269	1		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T163	5		T256	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T195	1		T70	13		T223	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14912	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T16	1		T53	1		T31	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	19		T28	13		T95	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	15		T188	7		T146	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T2	12		T13	8		T15	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	18		T14	12		T169	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	12		T31	9		T163	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T53	16		T255	10		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T59	10		T282	7		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T222	2		T285	11		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T56	4		T28	14		T189	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	11		T31	3		T164	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T54	12		T192	10		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T56	8		T254	10		T96	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T70	11		T192	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T58	12		T145	11		T96	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	2		T186	1		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	11		T54	7		T272	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T55	5		T60	12		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T269	11		T98	3		T102	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T163	8		T282	10		T259	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T70	11		T223	10		T261	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T52	1		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T16	13		T53	11		T31	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T1	3		T11	2		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T70	13		T223	13		T107	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T342	9		T197	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T341	1		T199	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T162	1		T204	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	1		T53	1		T29	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T2	1		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	24		T14	11		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	1		T163	11		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T255	1		T222	1		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	1		T31	8		T33	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T53	15		T61	8		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	1		T169	1		T282	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	3		T12	11		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T54	12		T56	17		T189	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T56	10		T149	14		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T53	3		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T58	11		T145	8		T159	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T70	15		T143	13		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T54	8		T256	1		T271	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T55	7		T56	12		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T49	14		T195	1		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14542	1			T6	33		T7	20		T8	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T163	8		T282	10		T259	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T70	11		T223	10		T307	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T342	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T162	7		T285	14		T95	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	13		T53	11		T29	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T2	12		T13	8		T15	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	18		T14	12		T146	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	12		T163	11		T158	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T255	10		T222	2		T169	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	9		T59	10		T282	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T53	16		T152	12		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	14		T169	9		T102	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	11		T31	3		T285	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T54	12		T56	4		T189	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	8		T254	10		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T192	21		T58	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T58	12		T145	11		T96	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T70	11		T42	2		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T54	7		T95	13		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	5		T60	12		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	11		T272	8		T269	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T55	20		T28	14		T61	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	16		T36	1		T188	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T2	13		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	20		T14	13		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	13		T31	10		T163	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T53	17		T255	11		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	1		T33	1		T59	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T222	3		T61	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	5		T28	15		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	3		T12	12		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T53	1		T54	13		T192	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T56	9		T150	1		T254	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	2		T70	12		T192	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T58	13		T256	1		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T56	1		T143	1		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T49	12		T54	8		T272	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T55	6		T36	1		T60	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T58	1		T269	12		T98	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T163	9		T256	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T195	1		T70	12		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15006	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T16	14		T53	12		T31	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T55	15		T61	4		T165	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T29	15		T265	10		T223	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T57	10		T32	13		T35	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	22		T14	10		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	7		T163	10		T158	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T53	14		T154	13		T307	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T33	7		T59	9		T282	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T61	7		T147	20		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T56	16		T189	10		T282	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	10		T31	3		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T53	2		T54	11		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	9		T254	17		T96	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T70	14		T179	14		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	10		T271	11		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T56	11		T143	12		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T49	13		T54	7		T272	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T55	6		T60	9		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T98	8		T284	12		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T163	4		T282	9		T311	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T70	12		T223	12		T343	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T288	12		T210	12		T260	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T31	10		T192	8		T199	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	3		T11	2		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T70	12		T223	11		T107	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T342	6		T197	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T341	1		T199	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T162	8		T204	1		T285	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	14		T53	12		T29	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T2	13		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	20		T14	13		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	13		T163	12		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T255	11		T222	3		T169	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	1		T31	10		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	17		T61	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	15		T169	10		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	3		T12	12		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	13		T56	5		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T56	9		T149	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T53	1		T192	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T58	13		T145	12		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T70	12		T143	1		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T54	8		T256	1		T271	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T55	6		T56	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T49	12		T195	1		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14627	1			T6	34		T7	20		T8	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T163	4		T282	9		T23	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T70	12		T223	12		T307	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T342	8		T197	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T199	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T165	7		T320	4		T288	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T29	15		T31	10		T192	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T55	15		T57	10		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	22		T14	10		T52	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T163	10		T158	7		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T265	8		T193	2		T307	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	7		T33	7		T59	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	14		T61	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T282	2		T159	15		T102	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	10		T31	3		T147	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T54	11		T56	16		T189	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	9		T149	13		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T53	2		T192	10		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	10		T145	7		T159	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T70	14		T143	12		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	7		T271	11		T147	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T55	6		T56	11		T60	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	13		T272	10		T98	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13