Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20254

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3290

1

T1

2

T12

37

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17755

1

T1

5

T6

34

T7

20

auto[1]

5789

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	194	1			T36	1		T58	23		T99	1
values[0]	31	1			T95	14		T259	4		T229	11
values[1]	576	1			T1	2		T53	31		T255	11
values[2]	721	1			T11	3		T150	1		T61	5
values[3]	675	1			T12	22		T16	14		T53	3
values[4]	617	1			T52	3		T54	15		T55	35
values[5]	683	1			T28	15		T31	14		T58	8
values[6]	618	1			T12	15		T29	31		T186	16
values[7]	712	1			T56	39		T31	24		T59	20
values[8]	578	1			T195	1		T222	3		T191	18
values[9]	3221	1			T2	13		T3	2		T4	1
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	626	1			T53	31		T28	14		T189	20
values[1]	757	1			T11	3		T53	3		T150	1
values[2]	608	1			T12	22		T16	14		T52	3
values[3]	598	1			T54	15		T55	35		T31	14
values[4]	694	1			T28	15		T58	8		T150	1
values[5]	589	1			T12	15		T56	21		T29	31
values[6]	2912	1			T2	13		T3	2		T4	1
values[7]	574	1			T49	25		T191	18		T179	15
values[8]	963	1			T12	27		T14	23		T16	13
values[9]	114	1			T58	23		T271	12		T265	11
minimum	15109	1			T1	5		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T53	15		T158	2		T159	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	1		T189	11		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	3		T53	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T60	10		T61	5		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T58	1		T265	9		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	11		T16	1		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	11		T42	5		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T54	8		T55	16		T33	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T58	1		T150	1		T61	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T28	1		T158	9		T267	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T56	17		T29	16		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	8		T188	1		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T2	1		T3	2		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T195	1		T186	15		T147	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	14		T191	10		T179	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T278	1		T208	1		T148	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T12	16		T54	12		T56	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	11		T16	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T265	11		T283	1		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T58	11		T271	12		T325	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14864	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T1	1		T179	2		T163	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T53	16		T158	7		T164	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	13		T189	9		T146	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T254	10		T96	7		T102	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T60	12		T19	1		T280	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T193	2		T286	8		T307	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	11		T16	13		T192	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T31	3		T42	2		T192	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	7		T55	19		T257	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T58	7		T146	17		T223	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	14		T158	10		T267	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T56	4		T29	15		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	7		T188	7		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T2	12		T13	8		T15	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T186	1		T285	14		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T49	11		T191	8		T282	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T153	12		T154	10		T165	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	11		T54	12		T70	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	12		T16	12		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T283	11		T281	2		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T58	12		T325	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T52	1		T255	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T1	1		T163	11		T259	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T36	1		T99	1		T181	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T58	11		T344	14		T345	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T95	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	1		T229	5		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T53	15		T255	1		T55	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T28	1		T189	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	3		T150	1		T158	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	5		T45	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T53	3		T58	1		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	11		T16	1		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T42	5		T192	10		T265	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T52	3		T54	8		T55	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T31	11		T58	1		T61	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	1		T158	9		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	16		T150	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	8		T186	15		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T56	27		T31	12		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T269	1		T95	1		T279	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T222	1		T191	10		T179	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T195	1		T147	21		T148	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T2	1		T3	2		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	11		T16	1		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T167	5		T288	23		T317	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T58	12		T344	13		T345	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T95	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T259	3		T229	6		T312	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T53	16		T255	10		T55	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T28	13		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	7		T254	10		T102	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T146	1		T19	1		T280	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T193	2		T96	7		T165	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	11		T16	13		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	2		T192	20		T102	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T54	7		T55	19		T257	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T31	3		T58	7		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	14		T158	10		T98	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	15		T169	9		T284	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	7		T186	1		T188	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T56	12		T31	12		T59	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T269	11		T95	1		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T222	2		T191	8		T282	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T285	14		T153	12		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T2	12		T12	11		T13	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	12		T16	12		T53	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	17		T158	8		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	14		T189	10		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	3		T53	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T60	13		T61	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T58	1		T265	1		T193	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	12		T16	14		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	4		T42	5		T192	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	8		T55	20		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T58	8		T150	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T28	15		T158	11		T267	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T56	5		T29	16		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	8		T188	8		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	13		T3	2		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T195	1		T186	2		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T49	12		T191	9		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T278	1		T208	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	12		T54	13		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	13		T16	13		T53	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T265	1		T283	12		T281	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T58	13		T271	1		T325	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14981	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T1	2		T179	1		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T53	14		T158	1		T159	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T189	10		T279	10		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T53	2		T148	9		T254	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T60	9		T61	4		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T265	8		T147	21		T307	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	10		T52	2		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	10		T42	2		T192	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	7		T55	15		T33	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T61	7		T265	14		T146	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T158	8		T267	9		T291	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T56	16		T29	15		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T12	7		T163	4		T272	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T56	9		T57	10		T31	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T186	14		T147	20		T279	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T49	13		T191	9		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T148	12		T159	17		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	15		T54	11		T56	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	10		T70	12		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T265	10		T21	1		T316	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T58	10		T271	11		T325	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T55	6		T161	9		T300	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T179	1		T163	10		T160	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T36	1		T99	1		T181	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T58	13		T344	14		T345	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T95	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	4		T229	7		T312	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	17		T255	11		T55	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	2		T28	14		T189	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	3		T150	1		T158	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	1		T45	1		T146	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	1		T58	1		T193	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	12		T16	14		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T42	5		T192	22		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T52	1		T54	8		T55	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T31	4		T58	8		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T28	15		T158	11		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	16		T150	1		T169	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	8		T186	2		T188	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T56	14		T31	14		T59	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T269	12		T95	2		T279	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T222	3		T191	9		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T195	1		T147	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T2	13		T3	2		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T14	13		T16	13		T53	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T181	6		T288	27		T346	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T58	10		T344	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T229	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T53	14		T55	6		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T189	10		T179	1		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	1		T148	9		T254	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T61	4		T19	1		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	2		T147	21		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	10		T149	13		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	2		T192	8		T265	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T52	2		T54	7		T55	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	10		T61	7		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T158	8		T98	21		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	15		T284	12		T267	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	7		T186	14		T163	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T56	25		T31	10		T59	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T279	9		T113	1		T122	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T191	9		T179	14		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	20		T148	12		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T12	15		T49	13		T54	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	10		T70	12		T143	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13