Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20190

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3354

1

T16

13

T49

25

T52

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17584

1

T1

3

T6

34

T7

20

auto[1]

5960

1

T1

2

T2

13

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	148	1			T61	5		T277	1		T159	18
values[0]	41	1			T265	9		T275	7		T276	25
values[1]	615	1			T11	3		T12	27		T53	31
values[2]	877	1			T255	11		T28	15		T31	17
values[3]	624	1			T55	1		T56	39		T143	13
values[4]	612	1			T54	39		T70	24		T150	1
values[5]	2902	1			T1	2		T2	13		T3	2
values[6]	745	1			T49	25		T52	3		T33	8
values[7]	475	1			T55	35		T56	12		T70	26
values[8]	543	1			T16	14		T53	12		T28	14
values[9]	1044	1			T14	23		T16	13		T195	1
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	654	1			T11	3		T12	27		T28	15
values[1]	767	1			T255	11		T56	21		T36	1
values[2]	620	1			T55	1		T56	18		T70	24
values[3]	2904	1			T2	13		T3	2		T4	1
values[4]	650	1			T1	2		T12	22		T49	25
values[5]	696	1			T52	3		T56	12		T33	8
values[6]	485	1			T55	35		T70	26		T192	18
values[7]	603	1			T14	23		T16	14		T53	12
values[8]	936	1			T16	13		T195	1		T29	31
values[9]	97	1			T277	1		T159	18		T279	11
minimum	15132	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	3		T12	16		T31	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	1		T58	11		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	1		T169	1		T271	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T255	1		T56	17		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T55	1		T179	28		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	10		T70	13		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	1		T60	10		T278	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T12	11		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T49	14		T53	3		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T56	12		T189	11		T265	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T52	3		T33	8		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T192	9		T44	4		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	16		T70	15		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	11		T16	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	1		T162	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	16		T31	4		T61	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T16	1		T195	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T277	1		T279	11		T38	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T159	18		T351	2		T352	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14866	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T53	15		T180	14		T307	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	11		T31	9		T192	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	14		T58	12		T188	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T169	9		T146	3		T102	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T255	10		T56	4		T282	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	1		T101	4		T284	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T56	8		T70	11		T193	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T2	12		T12	7		T13	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T60	12		T145	11		T283	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	1		T12	11		T60	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	11		T31	3		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T189	9		T254	10		T101	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T163	8		T169	12		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T192	9		T258	3		T262	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T55	19		T70	11		T58	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	12		T16	13		T28	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	11		T162	7		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	15		T31	3		T158	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T16	12		T222	2		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T38	8		T325	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T353	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T52	1		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T53	16		T307	4		T225	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T61	5		T277	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T159	18		T96	9		T351	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T265	9		T276	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	3		T12	16		T192	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T53	15		T58	11		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T31	8		T36	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T255	1		T28	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T55	1		T179	28		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T56	27		T143	13		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T54	20		T272	11		T193	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T70	13		T150	1		T60	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T1	1		T2	1		T3	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	3		T31	11		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T149	14		T189	11		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	14		T52	3		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	12		T192	9		T265	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T55	16		T70	15		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T28	1		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	1		T58	1		T179	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	11		T29	16		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T16	1		T195	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T305	2		T104	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T96	8		T287	5		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T276	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	11		T192	10		T191	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	16		T58	12		T188	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T31	9		T192	11		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T255	10		T28	14		T193	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	1		T101	4		T284	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T56	12		T193	2		T282	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T54	19		T272	8		T193	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T70	11		T60	12		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T1	1		T2	12		T12	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	3		T42	2		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T189	9		T60	9		T254	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	11		T169	12		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T192	9		T258	3		T262	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T55	19		T70	11		T163	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	13		T28	13		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T53	11		T58	7		T162	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	12		T29	15		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T16	12		T222	2		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	3		T12	12		T31	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	15		T58	13		T188	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	1		T169	10		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T255	11		T56	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T55	1		T179	2		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T56	9		T70	12		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	1		T60	13		T278	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	2		T12	12		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T49	12		T53	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	1		T189	10		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T52	1		T33	1		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T192	10		T44	4		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T55	20		T70	12		T58	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	13		T16	14		T28	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	12		T162	8		T169	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	16		T31	4		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T16	13		T195	1		T222	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T277	1		T279	1		T38	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T159	1		T351	2		T352	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14977	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T53	17		T180	1		T307	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	15		T31	7		T191	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T58	10		T163	10		T59	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T271	11		T146	11		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	16		T282	18		T147	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T179	26		T101	9		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	9		T70	12		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T12	7		T54	18		T55	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T60	9		T61	7		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	10		T149	13		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	13		T53	2		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T56	11		T189	10		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	2		T33	7		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T192	8		T258	2		T270	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	15		T70	14		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	10		T223	2		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T148	9		T165	7		T291	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T29	15		T31	3		T61	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T186	14		T148	12		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T279	10		T38	9		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T159	17		T353	1		T326	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T192	10		T265	8		T276	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T53	14		T180	13		T307	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T61	1		T277	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T159	1		T96	9		T351	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T265	1		T276	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T275	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	3		T12	12		T192	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	17		T58	13		T188	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T31	10		T36	1		T192	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T255	11		T28	15		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T55	1		T179	2		T146	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T56	14		T143	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T54	21		T272	9		T193	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T70	12		T150	1		T60	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	2		T2	13		T3	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T53	1		T31	4		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T149	1		T189	10		T60	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	12		T52	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T56	1		T192	10		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	20		T70	12		T163	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	14		T28	14		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T53	12		T58	8		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	13		T29	16		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T16	13		T195	1		T222	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T61	4		T279	10		T305	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T159	17		T96	8		T288	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T265	8		T276	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	15		T192	10		T191	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	14		T58	10		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T31	7		T271	11		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T282	9		T147	20		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T179	26		T101	9		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T56	25		T143	12		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T54	18		T272	10		T193	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T70	12		T60	9		T61	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T12	17		T55	6		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T53	2		T31	10		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T149	13		T189	10		T254	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	13		T52	2		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	11		T192	8		T265	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T55	15		T70	14		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T223	2		T153	12		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T179	14		T158	7		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	10		T29	15		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T186	14		T148	12		T223	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13